A Power Loss Sharing Technique for Buck Converters via Current–Temperature–Resistance Model and Dynamic Current Balancing

Abstract

Multiphase buck converters are critical in data centers and base stations, where their efficiency and thermal performance dictate system reliability. Conventional current-sharing methods fail to equalize power losses under component mismatches, causing localized overheating and efficiency degradation. This paper introduces a dynamic current balancing strategy based on active power loss sharing. A coupled current–temperature–resistance model is developed to dynamically estimate the equivalent resistance of each phase, capturing the behavior of MOSFETs, inductors, and PCB traces. This model enables real-time, loss-based current weight adjustment to actively balance interphase losses. Experimental results demonstrate that the proposed approach improves peak efficiency by up to 3–8.6% and reduces the critical component temperature rise by 11.6 °C under typical loads, confirming its substantial value in enhancing the performance of multiphase power systems.

1. Introduction

Multiphase buck converters have emerged as a critical power architecture in various high-performance applications, leveraging their unique structural advantages to address demanding power delivery challenges. The interleaving operation inherent to this topology significantly reduces output current ripple and minimizes passive component size, making it particularly suitable for data centers and communication base stations that require high-current power solutions [1]. By incorporating fully integrated current-balancing schemes, these converters achieve precise current sharing among phases, not only enhancing power density but also improving thermal distribution characteristics—a crucial advantage for applications with strict spatial constraints such as detection lighting systems [2]. Advanced thermal management strategies, including optimized heatsink designs and airflow control techniques, further ensure operational reliability under high-temperature conditions, providing robust power support for high-performance computing equipment [3]. The development of three-dimensional integrated circuit technology has opened new possibilities for compact thermal solutions in multiphase converter designs [4]. Moreover, sophisticated control and optimization strategies enable these converters to achieve superior efficiency and dynamic performance in emerging applications like electric vehicle charging systems [5]. However, as power levels and integration density continue to rise, thermal management has emerged as a progressively critical challenge [6,7]. Discrepancies in device parameters, asymmetric layout configurations, and non-uniform operating temperatures contribute to imbalanced power loss distribution among phases, leading to localized overheating, efficiency degradation, and potential compromise of system reliability [8]. Consequently, achieving coordinated optimization between current sharing and thermal management under high-load conditions has become a pivotal challenge in the design of multiphase buck converters [9,10].

To mitigate phase imbalance in multiphase buck converters, conventional control strategies commonly utilize current-sharing techniques based on inductor or output current sensing, including master–slave and democratic current-sharing schemes [11,12]. While these methods enhance current distribution to a certain degree, their control objectives primarily target current balancing itself, often overlooking the actual loss distribution across phase components. Owing to the nonlinear temperature dependence of device impedance characteristics, merely achieving current equalization does not necessarily lead to optimal system efficiency [13,14,15]. In certain scenarios, it may even exacerbate localized temperature rise due to excessive losses in specific phases, thereby constraining further improvements in overall system performance.

In recent years, various improved strategies have been proposed for thermal management in multiphase buck converters, including temperature-feedback current sharing, loss model prediction, and thermal coupling optimization [16,17,18]. While these studies have made some progress in thermal-aware control, most still rely on simplified steady-state thermal models or offline calibration, making it difficult to accurately capture the temperature-dependent behavior of device parameters under realistic dynamic operating conditions. Moreover, existing approaches often treat current sharing and thermal management as separate issues, lacking a systematic model that accounts for the coupling between loss distribution and temperature fields. This limits their practical effectiveness in co-optimizing efficient energy conversion and thermal management.

To overcome these limitations, this paper proposes a control method for multiphase buck converters based on average loss allocation. Aiming at minimizing total system losses, the approach dynamically adjusts the current distribution among phases to achieve synergistic optimization of efficiency and thermal management. To improve modeling accuracy, an effective current–temperature–resistance model is developed, which predicts the equivalent impedance of key components such as inductors and MOSFETs based on their real-time operating temperatures, thereby providing accurate references for optimal current distribution. The proposed method not only compensates for the shortcomings of conventional current-sharing strategies in loss optimization but also enhances system adaptability under practical operating conditions through closed-loop feedback of temperature and electrical parameters.

The paper is organized as follows: Section 2 provides a theoretical analysis of the benefits of power loss sharing. Section 3 elaborates on the developed current–temperature–resistance model and analyzes the temperature-dependent characteristics of device parameters. Section 4 presents experimental validation of the proposed strategy in terms of efficiency improvement and temperature rise suppression, with comparative analysis against conventional methods. Finally, Section 5 summarizes the work and suggests potential directions for future research.

2. Quantitative Analysis of Power Loss Sharing

In high-power applications, the synchronous multiphase buck converter is the predominant topology, effectively mitigating the high-current stress on individual phases. This architecture enables high output current, reduced output ripple, and high power density. To meet increasing current demands, systems are often designed with a growing number of phases—frequently employing dozens or even more than twenty power modules in parallel, as illustrated in Figure 1a. However, as the number of parallel phases increases, conventional current-sharing strategies face limitations. Parameter mismatches, such as in duty cycle, lead to different desired current-sharing ratios among phases. Simply pursuing numerically equal current in each phase results in unequal power losses across modules, thereby reducing overall efficiency—which contradicts the core objective of high efficiency in high-power scenarios.

To optimize system-level efficiency, this paper proposes a control strategy aimed at average loss distribution. The loss mechanisms in high-power devices are multifaceted and complex [19]. This work comprehensively accounts for various loss components, including miscellaneous losses, PCB trace losses, switch on-state resistance losses, magnetic core and winding losses, switching losses, and gate driver losses. The relationship between total power loss and current variation has been systematically characterized. The loss challenge becomes most severe under high-power operating conditions. As illustrated in Figure 2, conduction-related losses dominate the total loss profile, accounting for 85.5% of the total losses at high output current conditions. Therefore, under full-load efficiency optimization, the following assumptions are adopted: (1) conduction losses dominate, allowing other loss components to be neglected; (2) strict current uniformity per branch is relaxed, permitting minor current deviations within predefined thresholds.

Based on power loss analysis and the Joule heating principle, the current in each branch is inversely proportional to the square root of its resistance:

$$I_{psi}={\displaystyle \frac{\frac{1}{\sqrt{R_i}}}{\sum _{i=1}^N\frac{1}{\sqrt{R_i}}}}{I}_{out}, P_{psi}=({\displaystyle \frac{\frac{1}{\sqrt{R_i}}}{\sum _{i=1}^N\frac{1}{\sqrt{R_i}}}}{)}^2{I}_{out}^2·R_i={\left({\displaystyle \frac{1}{\sum _{i=1}^N\frac{1}{\sqrt{R_i}}}}\right)}^2{I}_{out}^2$$

(1)

where $I_{psi}$ represents the effective current in the $i$-th phase under the average loss allocation strategy, $P_{psi}$ denotes the conduction loss of the $i$-th phase, and $N$ is the total number of phases. By dynamically adjusting the current in each phase, this strategy ensures that the power losses across all phases converge to a balanced distribution.

For conventional current-sharing control, the relationship between current and conduction loss is given by:

$$I_{csi}={\displaystyle \frac{I_{out}}{\mathrm{N}}}, P_{csi}=I_i^2·R_i$$

(2)

where $I_{\mathrm{csi}}$ denotes the effective current in the $i$-th phase under the current-sharing strategy, and $P_{\mathrm{csi}}$ represents the corresponding conduction loss of that phase.

In a multi-phase buck converter, the loss characteristics across phases often share common features. To facilitate a clear and tractable analysis, we consider a basic two-phase buck circuit as an illustrative example. Assuming the on-state resistances of the two phases are $R_1$ and $R_2$, respectively, and the total output current is $I_{\mathrm{out}}$, the total conduction losses under both conventional current-sharing and the proposed power loss sharing strategies can be derived as follows:

$$P_{cs}={\displaystyle \frac{\left(R_1+R_2\right)I_{out}^2}{4}},P_{ps}={\displaystyle \frac{2I_{out}^2}{\frac{1}{R_1}+\frac{1}{R_2}+\frac{2}{\sqrt{R_1{R}_2}}}}$$

(3)

A parametric analysis was performed to quantify the effect of differing parasitic resistances on power loss. Defining the ratio $k=R_2/R_1$ and substituting into Equation (3) yields the following expression for the loss difference between the two approaches:

$$P_{cs}-P_{ps}=I_{out}^2{R}_1\left({\displaystyle \frac{1+k}{4}}-{\displaystyle \frac{2}{{\left(1+1/\sqrt{k}\right)}^2}}\right)$$

(4)

To better demonstrate the advantage of average loss allocation, the result can be alternatively expressed as:

$${\displaystyle \frac{P_{ps}}{P_{cs}}}={\displaystyle \frac{8}{\left(R_1+R_2\right)\left(\frac{1}{R_1}+\frac{1}{R_2}+\frac{2}{\sqrt{R_1{R}_2}}\right)}}$$

(5)

As shown in Figure 1b, which plots the loss comparison derived from Equation (5) for different resistance mismatches, a resistance difference ratio exceeding 50% leads to a loss reduction of at least 10% with the power loss sharing strategy. This improvement is highly substantial in practical applications such as single-phase systems above 400 vW and multi-phase systems beyond 2 kW. Hence, accurate branch resistance estimation combined with the average-loss-based current distribution strategy provides an effective pathway to significantly higher system efficiency.

3. Modeling of Heat Transfer with Temperature–Resistance Coupling

3.1. Operating Principle of the Buck Converter

Figure 3 categorizes the various conduction resistances present in a buck converter. The primary equivalent resistances include the inductor’s DC resistance (DCR), the capacitor’s equivalent series resistance (ESR), the MOSFET on-state resistances (${\mathrm{R}}_{on1}$, ${\mathrm{R}}_{on2}$), PCB parasitic resistance (${\mathrm{R}}_c$), and wire resistance (${\mathrm{R}}_w$). The circuit consists mainly of a power inductor, capacitors, and power MOSFETs, which together convert a high input voltage to a lower output voltage. Its operation is based on cyclic energy storage and release among the inductor, capacitor, and switching devices. When the high-side switch is turned on and the low-side switch is off, the inductor stores energy, causing its current to rise linearly. During this phase, the capacitor charges while supplying power to the load. When the high-side switch turns off and the low-side switch turns on, the inductor releases energy, leading to a linear decrease in inductor current. The output voltage is maintained during this interval by capacitor discharge and the decaying inductor current. Under ideal conditions, the output voltage $V_{\mathrm{out}}$ can be expressed as:

$$Vout=D\cdot Vin$$

(6)

where D is the duty cycle, defined as the ratio of the high-side switch on-time to the entire switching period.

3.2. Control Strategy of Power Loss Sharing

Accurate average loss allocation first requires obtaining the actual impedance values of each phase branch under real operating temperatures. Equivalent impedances of power devices, such as ${\mathrm{R}}_{on1}$, ${\mathrm{R}}_{on2}$, and DCR, all exhibit significant positive temperature coefficient (PTC) characteristics. If power loss calculations rely solely on nominal impedance values at room temperature, the results will substantially deviate from the actual loss distribution under operating conditions due to temperature variations during circuit operation, leading to control strategy failure. To address this limitation, the paper establishes an effective current–temperature–resistance model. By real-time monitoring of temperatures under different load conditions, the model predicts the actual temperatures of various circuit sections, dynamically updates the impedance parameters of key components, and incorporates them into a DC resistance model to solve for the optimal current distribution, thereby achieving balanced power loss control.

The model comprises three interconnected sub-models: a surface temperature heat transfer model, a temperature-resistance calculation model, and a DC conduction loss calculation model. The overall logical relationship is shown in Figure 4, which enables sequential determination of the internal actual temperature, actual impedance values, and optimal current distribution set.

3.3. Principle of the Model

3.3.1. Surface Temperature Heat Transfer Model

This model utilizes infrared thermal imaging to track reference temperatures on the device surface, from which the internal temperature is derived. Given the complex packaging architecture of the power module and the multiplicity of heat transfer paths, suitable formulations must be applied according to the specific geometry and boundary conditions, as illustrated in Figure 5.

While this paper utilized an infrared thermographic camera for experimental validation, the associated cost of such a system may preclude its direct integration into commercial converter products. The primary role of the IR camera herein was to serve as a high-fidelity reference instrument for capturing detailed two-dimensional temperature distributions, which was indispensable for rigorously validating the accuracy of the proposed electrothermal model across the entire prototype.

(1)

Planar Package

In this configuration, the heat transfer path can be modeled as conduction through a flat plate with surface area A and thickness d, where internally generated heat flows from one side to the other:

$$T_t=T_B+{\displaystyle \frac{P\cdot d}{k\cdot A}}$$

(7)

where $T_t$ is the internal device temperature, $T_B$ is the reference point temperature, $P$ is the thermal power, and $d/kA$ defines the thermal resistance $R_{th}$. The temperature difference $T_t-T_B$ equals the product of the thermal power and the thermal resistance.

(2)

Cylindrical Package

This configuration typically consists of concentric cylindrical shells. The corresponding heat conduction is described by:

$$T_t=T_B+{\displaystyle \frac{P\cdot d}{2\pi kLr}}$$

(8)

where $L$ is the cylinder length, $r$ the radius, and $d$ the wall thickness. This expression is derived from a simplification of the standard cylindrical thermal resistance, $R_{th}=\mathrm{l}\mathrm{n}{\displaystyle \frac{r_2/r_1}{2\pi kL}}$. Under the condition $d\ll r$, the approximation $\mathrm{l}\mathrm{n}{r}_2/r_1\approx d/r$ applies. Consequently, the temperature difference $T_t-T_B$ is proportional to the thermal power and wall thickness, and inversely proportional to the thermal conductivity, circumference, and length.

(3)

Three-dimensional Packaging

For heat transfer through the six faces of a cube or rectangular prism, each face exhibits a thermal resistance given by $R_{th,i}=d/k{A}_i$. $A_i$ is the surface area of the $i$-th face. The overall thermal resistance $R_{total}$ results from the parallel combination of the individual face resistances. Equivalently, the total thermal conductance—the reciprocal of the total resistance—is the sum of the conductance of all faces:

$$R_{total}={\displaystyle \frac{d}{k\sum _{i=1}^6{A}_i}}$$

(9)

The temperature difference $T_t-T_B$ is therefore given by the product of the thermal power and the total thermal resistance:

$$T_t=T_B+P\cdot R_{total}=T_B+{\displaystyle \frac{P\cdot d}{k\sum _{i=1}^6{A}_i}}$$

(10)

3.3.2. Thermal-Resistance Model

Once the internal temperature is determined, the actual resistance of the device at that temperature can be derived using empirical formulas.

PCB copper traces, cables, inductor DCR, and MOSFETs exhibit a positive temperature coefficient (PTC), whereas ceramic capacitors display a negative temperature coefficient (NTC). For components experiencing large temperature variations and requiring high precision, the Arrhenius equation is employed. For those with minor temperature fluctuations, linear approximations or empirical formulas are sufficient. Accordingly, three models are established to address different device characteristics:

For metallic PTC components such as PCB copper layers and cables:

$$R\left(T\right)=R_0\cdot \left[1+{\alpha }_{Cu}\cdot \left(T-T_0\right)\right]$$

(11)

where $R_0$ is the initial resistance, $T_0$ the reference temperature, and ${\alpha }_{\mathrm{Cu}}$ the temperature coefficient.

For components such as MOSFETs and inductor DCR, accurate modeling requires the use of the Arrhenius equation to describe their nonlinear temperature dependence:

$$k\left(T\right)=A\cdot e^{-{\displaystyle \frac{E_a}{RT}}}$$

(12)

where $E_a$ is the activation energy. The $E_a$ values of the MOSFET and inductor are taken as 0.4 eV and 0.9 eV, respectively, and A is a normalized constant, which depends on the specific resistance value of the device.

For Negative-Temperature-Coefficient (NTC) Ceramic Capacitors:

$$C\left(T\right)\approx C_{25\mathrm{°C}}\cdot \left[1+{\alpha }_C\cdot \left(T-25\right)\right]$$

(13)

where ${\alpha }_C$ is the negative temperature coefficient.

3.3.3. DC Resistance-Current-Loss Calculation Model

This model integrates the updated resistance values with the assigned phase currents to compute the real-time loss. From a control-loop standpoint, this loss is then fed back as an input to the thermal model, establishing a closed-loop coupled system governed by the feedback sequence: current → temperature → resistance → loss. The total conduction loss per phase is given by:

$$P_{loss}={\left(I_{L}D\right)}^2{R}_{DS\left(on\right)}+I_L^2{R}_{DCR}+I_{C,ripple}^2{R}_{ESR}+I_{out}^2{R}_{PCB}+I_{out}^2{R}_{wire}$$

(14)

where $I_L$ denotes the inductor current, $I_{\mathrm{mos}}$ the MOSFET current, $I_{C,\mathrm{ripple}}$ the capacitor ripple current, and $I_{\mathrm{out}}$ the current through PCB traces or wires.

Depending on the type of resistance, the appropriate current expression—such as average, RMS, or ripple current—should be substituted into the corresponding loss calculation. For example, the current of MOS is:

$$I_{mos}=I_L\times D$$

(15)

The RMS values should be calculated for both the inductor current $I_L$ (including its ripple component) and the capacitor ripple current $I_{C,\mathrm{ripple}}$. For instance:

$$I_{C,\mathrm{ripple}}={\displaystyle \frac{\mathsf{\Delta }{I}_L}{\sqrt{12}}}$$

(16)

In contrast, the PCB or wire current $I_{\mathrm{out}}$ corresponds to the DC component of the load current.

3.3.4. Power Loss Sharing Strategy

In multiphase power systems, the proposed power loss sharing strategy optimizes thermal performance by appropriately distributing phase currents to equalize losses among all phases, thereby improving overall system reliability and performance.

Considering a conventional four-phase buck converter, the core objective is to ensure equal power loss in each phase:

$$P_1=P_2=P_3=P_4=P_{\mathrm{phase}}$$

(17)

The conduction loss per phase is given by $P_k=I_k^2{R}_k$, where $R_k$ represents the total conduction resistance of the $k$-th phase, including MOSFET on-resistance and inductor DCR. To achieve loss balancing, the phase currents $I_k$ should not be uniform; rather, they must be allocated inversely proportional to the square root of the corresponding path resistance. The total output current is the sum of the phase currents:

$$I_1+I_2+I_3+I_4=I_{\mathrm{out}}$$

(18)

From the loss balance condition $I_k^2{R}_k=P_{\mathrm{phase}}$, the current in each phase is:

$$I_k=\sqrt{{\displaystyle \frac{P_{\mathrm{phase}}}{R_k}}}, k=\mathrm{1,2},\mathrm{3,4}$$

(19)

Substituting into the total current equation yields the common power loss:

$$\sum _{k=1}^4\sqrt{{\displaystyle \frac{P_{\mathrm{p}\mathrm{h}\mathrm{a}\mathrm{s}\mathrm{e}}}{R_k}}}=I_{out}$$

(20)

Solving for $P_{\mathrm{phase}}$:

$$P_{\mathrm{p}\mathrm{h}\mathrm{a}\mathrm{s}\mathrm{e}}={\left({\displaystyle \frac{I_{out}}{\sum _{k=1}^4\frac{1}{\sqrt{R_k}}}}\right)}^2$$

(21)

The current distribution can be conveniently expressed using a weight vector:

$$\mathrm{w}={{\left[\begin{array}{cccc}{\displaystyle \frac{1}{\sqrt{R_1}}}& {\displaystyle \frac{1}{\sqrt{R_2}}}& {\displaystyle \frac{1}{\sqrt{R_3}}}& {\displaystyle \frac{1}{\sqrt{R_4}}}\end{array}\right]}^T}^2$$

(22)

The phase currents are obtained by normalizing this vector:

$$\left[\begin{array}{c}{I}_1\\ I_2\\ I_3\\ I_4\end{array}\right]={\displaystyle \frac{I_{out}}{\parallel w{\parallel }_1}}\cdot w={\displaystyle \frac{I_{out}}{\frac{1}{\sqrt{R_1}}+\frac{1}{\sqrt{R_2}}+\frac{1}{\sqrt{R_3}}+\frac{1}{\sqrt{R_4}}}}\cdot \left[\begin{array}{c}{\displaystyle \frac{1}{\sqrt{R_1}}}\\ {\displaystyle \frac{1}{\sqrt{R_2}}}\\ {\displaystyle \frac{1}{\sqrt{R_3}}}\\ {\displaystyle \frac{1}{\sqrt{R_4}}}\end{array}\right]$$

(23)

Equivalently, each current can be written as:

$$I_k={\displaystyle \frac{I_{out}}{\sqrt{R_k}\sum _{i=1}^4\frac{1}{\sqrt{R_i}}}}$$

(24)

To verify the loss balance, consider the ratio between any two phases $k$ and $m$:

$${\displaystyle \frac{P_k}{P_m}}={\displaystyle \frac{I_k^2{R}_k}{I_m^2{R}_m}}={\displaystyle \frac{{\left(\frac{1}{\sqrt{R_k}}\right)}^2{R}_k}{{\left(\frac{1}{\sqrt{R_m}}\right)}^2{R}_m}}={\displaystyle \frac{1}{1}}=1$$

(25)

The result confirms that conduction losses are perfectly equal across all phases, validating the proposed loss balancing strategy.

4. Results

To verify the effectiveness of the proposed power loss sharing strategy utilizing the current–temperature–resistance feedback model, a high-power multiphase buck converter test platform is constructed. Comparative experiments are designed to evaluate the strategy under two typical operating scenarios: parallel connection of the same devices and parallel connection of different devices, as illustrated in Figure 6.

The working mode chosen by the buck converter is the intermediate bus converter (IBC). IBC operates with an input voltage of 48 V and delivers an output of 12 V, which represents a mature and widely adopted voltage solution. For the single-phase power module discussed, the steady-state output current is limited to 35 A. A rated operating point of 12 V/30 A, corresponding to 420 W, is typically selected for the analysis in this work.

4.1. Experimental Platform Setup

The test platform is built around multiple single-phase buck converter prototypes, which can be interconnected to form a multiphase buck converter system. Key components are summarized in

Table 1. Main component listing of the converter.

	Comparison of the Same Type	Comparison of the Different Type
Gate Driver	ISG3202	2ED2748S01GXTMA1 (4 A)	UCC27282 (3 A)
MOSFET	ISG3202	IQD009N06NM5 (1.27 mΩ)	CSD18540 (3.3 mΩ)
Inductor	XAL1350-302(6.8 mΩ)	XAL1580-302 (3.1 mΩ)	IHLP-5050EZ-01 (9.2 mΩ)
Cout	EEV227M035A9(160 mΩ)	EEEFK1V151P (160 mΩ)	Wurth86508055 (210 mΩ)
PCB quality	Well-optimized PCB layout	Well-optimized PCB layout	Unoptimized PCB layout
Wire	0.5 m	0.5 m	1 m

. The test setup includes a high-power programmable DC source, electronic loads, a high-precision power analyzer, data acquisition equipment, a thermal imager, and thermal management infrastructure.

During experiments, the DC source supplies a stable high-voltage input, and the electronic load draws high output current under various static and dynamic operating conditions. The power analyzer simultaneously records input/output voltage and current for accurate calculation of system efficiency and total power loss. A digital oscilloscope is used to observe voltage and current waveforms at key test points, enabling verification of switching behavior and system stability.

Recognizing that thermal dissipation under high power density is a critical factor affecting system reliability, this study implements a comprehensive thermal management approach. A hybrid cooling system combining forced air and liquid cooling is employed to dissipate heat from critical components including MOSFETs and inductors. Thermocouples are strategically placed at thermal-sensitive locations, with temperature data continuously logged through a data acquisition system. Additionally, thermal imaging provides supplementary scanning to identify potential localized hotspots. An interrupt mechanism is implemented to immediately shut down the power supply when temperatures exceed predefined thresholds. This integrated testing methodology enables precise characterization of the converter’s electro-thermal performance across various load conditions, delivering reliable data to validate the effectiveness of the proposed control strategy in improving efficiency and thermal management.

4.2. Experimental Methodology and Results Analysis

4.2.1. Parallel Connection of Same Devices

In this configuration, all power modules are identical. With a total output current of 60 A, the conventional current-sharing approach enforces equal current distribution, yielding 30 A per branch as shown in Figure 7a. Due to component impedance variations, this results in unequal power losses among phases, causing a markedly uneven temperature distribution with a maximum difference of 10.4 °C.

In contrast, when the proposed loss-balancing strategy is applied, the control system dynamically allocates currents in a 25.8 A:34.2 A ratio based on real-time resistance estimations, as depicted in Figure 7b. This current distribution equalizes conduction losses across phases. Experimental results show significantly improved temperature uniformity and a reduction of approximately 11.6 °C in the peak temperature, effectively mitigating localized overheating concerns. The temperature distribution under both strategies clearly demonstrates the advantage of the proposed approach in achieving better thermal balance.

4.2.2. Parallel Connection of Different Devices

To evaluate the strategy’s adaptability under more extreme parameter variations, a system was configured with parallel-connected power modules of different models exhibiting significant on-resistance disparities. Under conventional current sharing (30 A:30 A:30 A), the module with the highest impedance experienced excessive loss, developing into a pronounced hotspot with rapid temperature rise, as shown in Figure 8a, which also limited overall system efficiency.

With the proposed strategy applied, current was redistributed in a 37.9 A:31.6 A:20.5 A ratio, as depicted in Figure 8b. Experimental results verify effective suppression of the system-level hotspot temperature, maintaining a more uniform temperature profile below 80 °C. Even with entirely dissimilar device combinations, the maximum temperature difference remains within 5 °C.

4.3. Quantitative Analysis and Efficiency Improvement

Table 2. Sources of on-resistances.

Component	Typical Range (mΩ)
MOSFET	1–5
Inductor	1–7
Capacitor (ripple current)	5 with parallel configuration
PCB	1–3
Wire	5–25
Total variation range	13–45

summarizes the DC resistance variations observed across different components, as obtained from theoretical calculations and experimental measurements. The results reveal a considerable spread in resistance values. When these values are mapped onto the characteristic curve in Figure 1b, they provide clear justification for implementing the average-loss allocation strategy.

Based on the data in Table 2, theoretical calculations were performed using the extreme values of total path resistance. Consider a two-phase system with path resistances of $R_1$ = 13 mΩ and $R_2$ = 45 mΩ, corresponding to a ratio ${k=R_2/R}_1$≈ 3.46, and a total output current $I_{out}$ = 60 A.

For total loss with conventional current sharing, current is split equally between phases, so $I_1=I_2=30 \mathrm{A}$, and $P_{\mathrm{cs}}=I_1^2{R}_1+I_2^2{R}_2\approx 52.2 \mathrm{W}$.

For total loss with power loss sharing strategy, current is allocated according to Equation (1), so $I_1\approx 41.2 \mathrm{A}, I_2\approx 18.8 \mathrm{A}$, and $P_{\mathrm{ps}}=I_1^2{R}_1+I_2^2{R}_2\approx 38.0 \mathrm{W}$.

Under severe mismatch conditions, the average-loss allocation strategy reduces the total conduction loss by 14.2 W—a 27.2% improvement over the conventional current-sharing approach. These theoretical results are consistent with the experimental trends illustrated in Figure 7 and Figure 8. In both identical and mixed device setups, the proposed strategy consistently improves overall system efficiency and leads to a more uniform temperature distribution.

5. Conclusions

This paper presents a current–temperature–resistance feedback-based strategy for loss balancing in multiphase buck converters. A coupled model is developed to dynamically estimate the impedance of individual phases, enabling balanced distribution of power losses across the converter. Experimental results show that under device mismatch conditions, the proposed approach improves system efficiency by 3–8.6% and reduces the temperature rise of critical components by 11.6 °C. Future work will focus on integrating device aging models and dynamic gate driving techniques, together with sensorless methods such as current observers, to further enhance long-term reliability in wide-bandgap semiconductor applications.