On-Chip Yagi Antenna Design at 38 GHz with 0.18 μm CMOS Techniques

Abstract

In this study, a 38 GHz millimeter wave Yagi antenna was designed and fabricated on a chip using a 0.18 μm CMOS process. The radiation performance of the antenna is improved by using a Yagi antenna with end-fire. The proposed antenna chip measures the reflection coefficient at less than −10 dB over a bandwidth range from 36.6 to 39.8 GHz, covering the 5G n260 band. The CMOS antenna chip has a size of $1.2\times 1.2{ \mathrm{m}\mathrm{m}}^2$. This study also proposes a solution for the easy measurement of the radiation characteristics to verify the performance in millimeter wave applications. For this purpose, the chip antenna uses bonding wire technology and is verified in a millimeter wave test system. Finally, the simulation and measurement results of the antenna pattern of the bondline technique yield similar radiation patterns.

1. Introduction

Advances in wireless communications have led to the development of the Internet of Things, smart cities, wireless energy transmission, radio frequency energy harvesting, biomedicine, drones, and self-driving cars. The millimeter wave band is believed to be the future of wireless communication [1], and body area networks operating in the millimeter wave band have been investigated for implantable, contact, and contactless communication technologies. For many short-range communications that require low power consumption and small size, system-on-chip integration technologies have shown numerous advantages and have attracted a great deal of attention for wireless communication applications [2,3]. These breakthrough wireless communication applications are highly dependent on the tremendous innovations in wireless communication devices, systems, components, and technology choices that ensure low power consumption, thinness, cost effectiveness, and high performance. For the wireless communication architecture of a chip system, such as the integration of RF components and antennas on the same chip, the antenna of this system is called Antennas-on-Chip (AoC). Antennas-on-Chip have the above advantages and potential for future applications [4].

The millimeter wave band is growing in a variety of applications, and chip antennas are also becoming popular in the band. The millimeter wave band offers miniaturized, low-cost, low-power, wide-bandwidth, and high-data-rate communication devices and systems with the help of chip antennas. The main use of silicon-based technologies, especially Complementary Metal–Oxide–Semiconductor (CMOS) [5,6,7] and SiGe BiCMOS [8] technologies. In terms of technology, silicon (Si) CMOS and silicon germanium (SiGe) BiCMOS-based technologies have become the best choice for chip antenna design.

The design of chip antennas faces many challenges. First, the gain and radiation efficiency are not comparable to conventional antennas because the Si substrate is not well suited for their design. For the typical 1 Poly 6 Metal (1P6M) CMOS process, this is the reason for the degradation of antenna radiation performance. The thickness between metal layers is only 10 μm, the Si substrate is about 500 μm, and the low resistivity of the Si substrate is 10 Ω cm. This causes most of the electromagnetic wave propagation from the wafer antenna to the substrate, which reduces the gain of the chip antenna. Similarly, the high dielectric constant of silicon substrate (${\epsilon }_r=11.9$) causes most of the electromagnetic waves of the chip antenna to be absorbed by the Si substrate and not to be propagated into the air, thus reducing the overall performance of the chip antenna [9,10,11].

The literature [5] presents an implantable medical device with a 2.4 GHz chip antenna with a size of 4 ${\mathrm{m}\mathrm{m}}^2$. This is achieved by minimalizing the antenna through the capacitive loading of the curved dipole arm. The gain of the chip antenna is −23.8 dBi in air, which is sufficient for implantable devices but may be slightly insufficient for other environments. To solve the antenna radiation inefficiency problem of chips, experts have proposed many options, such as artificial magnetic conductor (AMC) [12], electromagnetic bandgap (EBG) structures [13], high impedance surfaces (HIS) [14], and frequency selective surfaces (FSS) [15]. These technologies all utilize reflection to reduce radiation within the CMOS substrate, but when integrated with active circuits, these technologies still require significant space to implement. The dielectric resonator antenna (DRA) is also one of the methods to help enhance the gain of the chip antenna. Using a low-loss dielectric material on top of the chip as an additional component, the radiation is transferred from the chip substrate to the external dielectric resonator, thus freeing it from many of the limitations of CMOS processes [16,17].

In [18], chip antennas including the diamond, Yagi, and ring structures are presented, yet their gain remains inadequate. In [19], an end-fire Quasi-Yagi antenna is chosen, which is made with a bipolar antenna, two guides, and a truncated ground plane. This is a traditional Yagi antenna shape made on a standard silicon substrate. The antenna achieves a bandwidth of 10 GHz from 55 to 65 GHz with −12.5 dBi antenna gain. In [20], a bifurcated Yagi antenna with a 0.18 μm CMOS design is used and the gain is increased by 0.8 dBi through an arc design. As a result, the chip antenna design needs to be designed in order to obtain end-fire performance antenna design to improve the performance of the chip antenna without the use of auxiliary structures and external dielectric resonators.

In this article, a 38 GHz chip Yagi antenna [21,22] is designed using a standard 0.18 µm CMOS process. Its size is 0.53 × 0.78 ${ \mathrm{m}\mathrm{m}}^2$ and covers the range of 36.6 to 39.8 GHz. The radiation performance of the antenna is improved by using a Yagi antenna with end-fire. In addition, this work proposes a solution for measuring the radiation characteristics to verify the performance of millimeter wave applications. For this purpose, a bonding wire technique [23,24] was used for the chip antenna and verified in a millimeter wave test system. Simulation and measurement results indicate that parasitic radiation between the chip antenna and the carrier significantly affects radiation direction. Therefore, an analytical model was established to optimize this interface design.

The next section, Section 2, introduces the design flow of the chip antenna and simulates the bonding wire technique used due to measurement constraints. Section 3 presents the results of fabrication and measurement and compares the chip antenna design with recent research. Finally, conclusions on-chip antennas are drawn in Section 4.

2. On-Chip Antenna Design

2.1. Yagi Antenna-on-Chip

The metal stack model of this design is depicted in Figure 1 and consists of a passivation layer and six metal layers embedded in ${\mathrm{S}}_{\mathrm{i}}{\mathrm{O}}_2$ (${\epsilon }_e$ = 4.0, representing the inter-metal dielectric medium). The 2.34 μm thick top metal 6 (M6) layer is used to design the chip antenna, while the silicon substrate thickness is 500 μm.

In CMOS processes, the relative permittivity makes the effective wavelength much shorter than in vacuum. It can be quantified using the approximation of (1) [25].

$${\epsilon }_e={\displaystyle \frac{{\epsilon }_r+1}{2}}+{\displaystyle \frac{{\epsilon }_r-1}{2}}\left[{\left(1+12\left({\displaystyle \frac{h}{L}}\right)\right)}^{-1/2}+0.04{\left(1-\left({\displaystyle \frac{L}{h}}\right)\right)}^2\right]$$

(1)

where ${\epsilon }_r$ is the relative permittivity, ${\epsilon }_e$ is the effective permittivity, h is the substrate thickness, and L is the metal width.

In most chip antenna designs, the metal width is smaller than the substrate thickness, so the wavelength ${\lambda }_e$ can be calculated as shown in (2). Equations (1) and (2) describe the effective permittivity of the dielectric environment, not the metallic layers.

$${\lambda }_e={\displaystyle \frac{c_0}{f\sqrt{{\epsilon }_e}}}$$

(2)

For a 38 GHz design with L = 30 μm, ${\epsilon }_e$ = 2.67 is the relative permittivity and ${\lambda }_e$ = 4830 μm. Because of the edge effects, the actual physical dimensions will be shorter than the length of ${\lambda }_e$.

Due to the limited space available on the chip, the choice of antenna type is critical. For example, the tapered slot antenna and the Yagi antenna have often been proposed in recent studies as end-fire antennas that can meet the demand for highly directional radiation. To obtain the best performance, a tapered slot antenna requires a ¾ wavelength, and a Quasi-Yagi antenna can achieve λ/2 × λ/2 in a region. Therefore, to minimize the area occupied by the chip antenna, a Yagi antenna architecture is chosen.

Figure 2a shows the overall chip Yagi antenna, which was composed of a reflector, a driving element, and a ground plane. The design architecture is shown in Figure 2b, which consists of a coplanar waveguide (CPW) and a coplanar stripline (CPS), and then the signal is fed to the Yagi antenna. The signal is fed into the antenna driver through a ground–signal–ground (G-S-G) probe with a spacing of 100 μm, and then into the CPW. A proper distance must be maintained between the ground plane and the antenna because too short of a distance will produce coupling effects and deteriorate the performance of the antenna. The antenna layout area is 530 × 780 μm², including the G-S-G probe test points, and the overall wafer size is W_s × W_s (1200 μm × 1200 μm).

Figure 3a shows the simulated reflection coefficient using a high-frequency electromagnetic simulator at 37.5 to 40.2 GHz below the −10 dB standard, which covers the n260 frequency band for fifth-generation mobile communications. As shown in Figure 3b, the simulated surface current at 38 GHz is mainly concentrated along the CPS, with only a small portion distributed on the conductor element.

The ground plane spacing is investigated to prevent excessive coupling and performance degradation. Therefore, simulations were performed for the ground plane Lg from 130 to 330 μm and the change in the reflection coefficient was monitored. Figure 4 shows the simulation results of the ground plane Lg. According to the simulation results, the reflection coefficient with Lg = 230 μm exhibits a wider impedance bandwidth and superior matching performance compared with Lg = 130 μm and Lg = 330 μm.

2.2. Bonding Line Design

Since the chip is too small to measure, but in order to evaluate the antenna directivity, the chip antenna is designed to pass through the bonding line on the PCB carrier board as shown in Figure 5. Figure 5a–c show the simulated antenna architecture of the bare die through the bonding line to the PCB carrier board. After the simulation by the high-frequency electromagnetic simulation software, it can be observed in Figure 6 that the operating frequency remains at 38 GHz, although there is some change in the reflection coefficient of the through-bonding wire technique. Figure 7 shows the simulated 2D radiation patterns in two planes. The chip antenna without a bonding line in Figure 7a has end-fire performance at −50°. Although the antenna end-fire radiation is less significant due to the effect of the silicon substrate, the simulations with bonding lines have a more significant end-fire performance at −49°. It is possible that the PCB carrier reduces the CMOS substrate effect, giving it a significant end-emission direction, but the bondline effect does exist as well. As seen in Figure 7b, there are clearly three radiating ends with bonding lines, and the reason for this effect is the effect of the three bonding lines.

3. Measurement and Discussion

This section implements the proposed chip-based Yagi antenna, which will be measured and simulated to verify the design.

3.1. Reflection Coefficient Measurement

To validate the design, the chip antenna reflection coefficient was measured first, and the measurement equipment is shown in Figure 8. The feedback system includes a vector network analyzer, Agilent E8257D (Keysight Technologies, Inc., Santa Rosa, CA, USA), and a ground–signal–ground probe (GSG) with a spacing of 100 μm.

The reflection coefficient is measured directly using the calibrated vector network analyzer, and the state of the probe is shown in Figure 9, where three pin points with a spacing of 100 μm are evident. Figure 10 shows S₁₁ and S₂₁ of the measured Thru after the calibration, and it can be seen that the insertion loss is very small from 20 to 50 GHz, so it is clear that the calibration is good.

The relationship between the simulated and measured reflectance coefficients (S11) is shown in Figure 11. The operating frequency of the bare crystal measurement can be seen to be skewed from the simulated frequency, and the reflection coefficient is lower than the −10 dB standard for the measurement bandwidth from 36.5 to 40 GHz. The deviation between the simulated and measured curves can be attributed to the presence of the probe station and the probe itself in the near-field region, both of which provide an imperfect free-space environment in the antenna radiation range, which will affect the reflection coefficient. Finally, in order to measure the reflection coefficient from the chip antenna combined with the bonding line to the PCB, only 36 to 40 GHz was measured due to the limitation of the measurement system, but the reflection coefficient is in the range of 36 to 39.4 GHz at the −10 dB standard. This means that the bonding line feed does not have a significant effect on the reflection coefficient.

3.2. Radiation Direction Measurement

The proposed chip antenna can be measured in a reflectionless room by connecting the PCB through the bonding line, and the measurement environment is shown in Figure 12. The solid red line in Figure 12a shows the antenna location and the measurement probe station. The red box at the bottom of Figure 12b shows the antenna top view, and the orange box at the top of Figure 12b shows the micrograph of the chip antenna through the bonding line and the PCB connection. The network analyzer used for this measurement system is a KeySight ENA E5080B (Keysight Technologies, Inc., Santa Rosa, California, USA). In addition, the non-reflective room facilities measured cover −90° to +90°, mainly in the northern hemisphere of the sphere coordinate system.

The proposed antenna was measured at 38 GHz, and the radiation patterns are shown in Figure 13. While both the simulated and measured results confirm the existence of end-fire radiation, there are noticeable discrepancies in the gain magnitude and side-lobe levels. Specifically, the simulated antenna achieves an end-fire peak around −49°, whereas the measured antenna exhibits a main lobe at approximately −50°. However, the measured gain decreases significantly from −7.5 dBi (simulated) to −18.3 dBi, and the radiation patterns in the YZ plane show larger differences compared to the XZ plane.

The discrepancies are mainly attributed to the following factors:

(1)

Bonding wire variations, including length, bending angle, and soldering position.

(2)

Substrate-related effects, such as dielectric losses and coupling between the PCB carrier and the CMOS chip.

(3)

Measurement setup limitations, including the near-field effects of the probe station.

Despite these limitations, the end-fire radiation trend is still observed, and the results provide useful insights into the practical challenges of packaging and measuring CMOS on-chip antennas at mm-wave frequencies. Possible improvements include the use of flip-chip packaging, low-loss substrates, and array designs to enhance gain and measurement consistency.

3.3. Literature Comparison and Discussion

Table 1. Comparison of chip antenna.

Ref.	CMOS (μm)	fc (GHz)	Bandwidth (GHz)	Efficiency	Size (mm2)	Gain (dBi)	Pattern Measurement
Proposed	0.18	38	36.6–39.8	13%	0.53 × 0.78	−7.5	Yes
[5]	0.18	2.4	-	-	1 × 1	−25.9	Yes
[9]	0.028	33	28.6–36	37.3%	0.66 × 0.85	−1.8	Yes
[20]	0.18	60	-	45%	0.631 × 0.46	0.35	No
[26]	0.065	24	-	41%	2.5 × 2.5	−1	Yes
[27]	0.18	9.45	-	-	2 × 2.1	−29	No
[28]	0.065	28/60	-	-	0.25 × 0.3	−10/0	Yes

shows the comparison between the designed chip Yagi antenna and the published papers. The antenna gain is moderate in terms of unaided structure design for the end-fire antenna architecture compared to the literature in the table, while the smaller size is shown for similar frequency bands in [9,26]. It is worth mentioning that actual far-field measurements were carried out in this design and the results are similar to the simulations.

4. Conclusions

This paper has presented the design and characterization of a 38-GHz CMOS on-chip Yagi antenna fabricated using a standard 0.18 μm TSMC CMOS process. The antenna has a compact size of 1.2 × 1.2 mm², with a core dimension of 530 × 780 μm². Both simulated and measured results confirm that the antenna exhibits end-fire radiation, with the main lobe observed at approximately −50° on the YZ plane. The systematic study of the bare die, bonding wire, and PCB carrier board highlights the necessity of co-design between the chip antenna and its carrier, as parasitic radiation significantly affects the radiation direction. Nevertheless, the antenna gain and efficiency remain limited, primarily due to substrate losses and bonding wire parasitics. This reflects the inherent trade-off between compact on-chip integration and radiation efficiency in CMOS technologies. Future work can address these limitations by adopting low-loss substrates, advanced packaging techniques such as flip-chip or through-silicon via (TSV), and antenna array integration to enhance gain and efficiency. Despite these challenges, the presented design serves as a useful validation example and benchmark for on-chip millimeter-wave antennas. It demonstrates a cost-effective approach for circuit–antenna co-integration, which may benefit future 5G and beyond-5G applications, including wearable devices, smartphones, laptops, and other compact wireless systems.