A DRC Automatic Repair Strategy for Standard Cell Layout Based on Improved Simulated Annealing Algorithm
Round 1
Reviewer 1 Report
Comments and Suggestions for AuthorsThe manuscript presents a standard unit DRC automatic repair method based on an improved simulated annealing algorithm. The design is reasonable and the experimental verification is thorough. The results show that it outperforms the traditional methods in both repair efficiency and accuracy, and can significantly reduce manual intervention and time costs, demonstrating strong innovation and engineering application prospects. However, there are still several shortcomings that need to be addressed.
1. The main experiments of the manuscript were conducted on 28nm MOSFET and 14nm FinFET. Could you briefly discuss the applicability of the method under more advanced processes (such as 7nm FinFET)? Even without experiments, some simple analyses can be added.
2、The connection between the first and second paragraphs in the introduction is a bit stiff, and a summary sentence needs to be added.
3、Is the title in Figure 1 too simple? At present, only "Overall design process" is written. It is suggested that "of DRC automatic repair" be added.
4、The conclusion section needs to add a description of the application prospects.
5、There are unit input errors in the content of 3.1 of the manuscript, such as "0.085m" and "0.05m", which should be "0.085 μm" and "0.05 μm" respectively.
6、Some references (such as [15]) have capitalized titles. It is recommended to change them to start with lowercase.
Author Response
We have responded to each of the reviewers' comments one by one. Please refer to the attachment.
Author Response File: 
Author Response.pdf
Reviewer 2 Report
Comments and Suggestions for AuthorsThe paper deals with the design of a novel algorithm based on simulated annealing to solve DRC violations in integrated circuits. The algorithm was tested both on standard mosfet in 28nm and FinFET devices in 14nm, showing the possibility to solve layout violations in acceptable amount of time.
The following points are highlighted:
1) Section 2.2.1 immediately starts with a description of the work objective without giving details about the simulated annealing algorithm. I suggest adding an introduction to this algorithm, specifying the meaning of “temperature” and “temperature decay” concepts in this context. This will help also readers not used to this topic to understand the proposed method.
2) Define also the meaning of “conflicts” in the point (2) of line 147.
3) Please, organize section 2.2.2 adding more references to Fig. 2. Also the mathematical details of the algorithm should be collected in a dedicated flow chart to enhance comprehension. Try to improve also the graphic quality of Fig. 2 (the image is stretched, and some labels are not within their boxes)
4) In the result section, please add information about the computer/server used to verify the algorithm, specifying the king of CPU, frequency, amount of memory, operative system etc. Specify also how you verify the absence of violations after the algorithm (is the final verification with Calibre?).
5) The proposed work is mainly focused on the solution of spacing problems. However, other kinds of DRC violations demand for suitable care, like enclosure, latch-up, antennas etc.. Is there the possibility of extending this work also to the solution of these violations? I believe it is important to add some considerations about this part in the text.
6) It is suggested to add the following examples of integrated circuits to highlight the importance of solving DRC errors in handcrafted layouts while preserving electrical performance. This also help improve the literature contextualization of the paper in the realm of integrated circuit design:
Tegazzini, G. Di Meo, D. De Caro and A. G. M. Strollo, "High-Precision MUX-Based Digital Delay Interpolators Based on a Novel Transistor Sizing Algorithm," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 72, no. 7, pp. 938-942, July 2025, doi: 10.1109/TCSII.2025.3571482.
Marinberg, E. Garzón, T. Noy, M. Lanuzza and A. Teman, "Efficient Implementation of Many-Ported Memories by Using Standard-Cell Memory Approach," in IEEE Access, vol. 11, pp. 94885-94897, 2023, doi: 10.1109/ACCESS.2023.3310940.
Author Response
We have responded to each of the reviewers' comments one by one. Please refer to the attachment.
Author Response File: Author Response.pdf
Reviewer 3 Report
Comments and Suggestions for AuthorsComments in a PDF file
Comments for author File: Comments.pdf
Author Response
We have responded to each of the reviewers' comments one by one. Please refer to the attachment.
Author Response File: Author Response.pdf
Round 2
Reviewer 1 Report
Comments and Suggestions for AuthorsThis article has been well revised, and I agree to accept it.
Reviewer 2 Report
Comments and Suggestions for AuthorsThe authors responded to all my questions. There are no forther observations. From my side, the paper is ready for pubblication.
