A DRC Automatic Repair Strategy for Standard Cell Layout Based on Improved Simulated Annealing Algorithm

Huang, Wenli; Li, Bin; Liu, Wenchao; Wu, Zhaohui; Lei, Zonghan; Huang, Songting; Qin, Chaozheng

doi:10.3390/electronics14214267

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Open AccessArticle

A DRC Automatic Repair Strategy for Standard Cell Layout Based on Improved Simulated Annealing Algorithm

by

Wenli Huang

¹,

Bin Li

^1,*,

Wenchao Liu

²,

Zhaohui Wu

¹,

Zonghan Lei

¹,

Songting Huang

¹ and

Chaozheng Qin

²

¹

School of Microelectronics, South China University of Technology, Guangzhou, 510640, China

²

Guangzhou Primarius Electronic Technologies Co., Ltd., Guangzhou, 510663, China

^*

Author to whom correspondence should be addressed.

Electronics 2025, 14(21), 4267; https://doi.org/10.3390/electronics14214267

Submission received: 17 September 2025 / Revised: 28 October 2025 / Accepted: 29 October 2025 / Published: 30 October 2025

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Abstract

As the integrated circuit process nodes are continuously reduced, higher complexity and accuracy requirements are imposed on the design rule checking (DRC) of standard cell layouts. Traditional manual repair methods are inefficient and prone to errors. A standard cell layout DRC automatic repair strategy based on an improved simulated annealing algorithm is proposed to address this issue. The proposed method quantifies the degree of graphic conflict by dynamically adjusting the annealing parameters; the high-conflict areas and repair paths are optimized. Meanwhile, the proposed method supports the repair of DRC rules at different process nodes ranging from MOSFET (28 nm) to FinFET (14 nm). Experiments results demonstrate that the proposed method outperforms traditional methods in both repair time and quality. Compared to manual repair, about 70% (MOSFET process) and 80% (FinFET process) of time can be saved by the proposed method, and new violations can be avoided during the repair process. Compared with traditional simulated annealing algorithms, approximately 40% (MOSFET process) and 50% (FinFET process) of the running time can be saved, and 100% elimination rate of DRC violations is achieved. The proposed method provides a fully automated and highly reliable DRC repair solution for integrated circuit layout design.

Keywords: standard cell layout; DRC automatic repair; improved simulated annealing algorithm; adaptive optimization; multi-process compatibility

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MDPI and ACS Style

Huang, W.; Li, B.; Liu, W.; Wu, Z.; Lei, Z.; Huang, S.; Qin, C. A DRC Automatic Repair Strategy for Standard Cell Layout Based on Improved Simulated Annealing Algorithm. Electronics 2025, 14, 4267. https://doi.org/10.3390/electronics14214267

AMA Style

Huang W, Li B, Liu W, Wu Z, Lei Z, Huang S, Qin C. A DRC Automatic Repair Strategy for Standard Cell Layout Based on Improved Simulated Annealing Algorithm. Electronics. 2025; 14(21):4267. https://doi.org/10.3390/electronics14214267

Chicago/Turabian Style

Huang, Wenli, Bin Li, Wenchao Liu, Zhaohui Wu, Zonghan Lei, Songting Huang, and Chaozheng Qin. 2025. "A DRC Automatic Repair Strategy for Standard Cell Layout Based on Improved Simulated Annealing Algorithm" Electronics 14, no. 21: 4267. https://doi.org/10.3390/electronics14214267

APA Style

Huang, W., Li, B., Liu, W., Wu, Z., Lei, Z., Huang, S., & Qin, C. (2025). A DRC Automatic Repair Strategy for Standard Cell Layout Based on Improved Simulated Annealing Algorithm. Electronics, 14(21), 4267. https://doi.org/10.3390/electronics14214267

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A DRC Automatic Repair Strategy for Standard Cell Layout Based on Improved Simulated Annealing Algorithm

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