Development of High-Power DC Solid-State Power Controllers Using SiC FETs for Aircraft Electrical Systems

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

The main purpose of this research is to develop and validate a high-power solid-state power controller (SSPC) for aircraft high voltage direct current (HVDC) electrical networks. Specifically, it aims to design a 270V, 300A SSPC using discrete SiC Cascode devices that can effectively interrupt high fault currents by employing parallel SiC FETs with a passive current balancing strategy. Additionally, the research addresses voltage spike mitigation during fault interruption with an RC-TVS circuit and optimizes thermal management for reliable SSPC operation. The overall goal is to improve interruption performance and reliability in emerging aircraft HVDC systems.

The research gap is the lack of effective solutions for balancing current among parallel SiC devices, mitigating voltage spikes during fault interruptions, and optimizing thermal management in high-power SSPCs for aircraft HVDC networks. This study addresses these challenges with novel design strategies and validates them through a prototype.

 

In addition, there are a few comments needs to be covered as follows:

• In table 1 , Value , Primary power distribu- the word distribution is not complete
• In page 7 “Based on (5), the equivalent square wave of the power dissipation waveform has an amplitude of 0.7Psc, and duration of 0.7tsc, as shown in Fig. 5(b).”, there no fig 5(b). I think you mean 6 b
• Table 1, 3, 4, and 5 are with the same caption. You can’t duplicate a caption even in different places, “Overload Protection Time” of what ….
• The resolution of fig 13 is not good needs to be enhanced.
• In fig 17 the resolution is not good, also the focused part is not right
• Fig 19 resolution is not clear and the focused part needs revision
• In the experimental part the authors shoed in figure 16 the experimental setup as separate parts , a whole picture of the setup is more suitable for understanding
• The conclusion needs more details while concluding the work done in this research

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Reviewer 2 Report

Comments and Suggestions for Authors

Overall Impression:

The article "Development of High Power DC Solid-State Power Controllers using SiC FETs for Aircraft Electrical System" is in scope of the journal.
The abstract and introduction clearly describe the state of the art and the basic idea of the approach of the authors, who propose a 270 V / 330 A solid-state power controller SSPC by paralleling SiC cascode devices. This parallel connection is necessary to achieve the high current rating and to prevent excessive heating of the devices in the event of a short-circuit, when the SSPC must carry the fault current and subsequently turn off. 
The main contribution of the authors is the detailed and comprehensive discussion of the design process, especially the thermal design, the current balancing strategy based on a proper (irregular) shaped busbar, and the voltage spike suppression design. The theoretical design, which is carried out by a mix of analytical calculations and numerical (circuit and field simulations), is solid and comprehensive. The experimental results back the design description.  

Formal aspects:

• The manuscript is basically well-formatted, with some minor corrections: 
  Abbreviation CB is used without prior definition, although ECB is defined as an electronic circuit breaker.
• The authors should check the capitalization of some words. E.g., in the abstract, cascode should be written with lowercase c, on page 3, several times section is written with a capitalized "S" at the beginning, although it is used within the sentence and should start with a lower case letter.
• There is no space between numbers and units throughout the whole article.
• In Fig. 7,18, the axis labels and legends are very small and not very readable; also, the lines in the graphs are very thin; this should be improved.
• Fig. 17 lacks labels and legends for the curves. It is assumed that the red curve represents the voltage Vds and the green curve represents the current Id (of a single device, which is the overall SSPC). Although the text describes this as a test with a 270 V and 40 A load current, this should also be marked in the figure. (Compare Fig. 17 to Fig. 18 to 20).
• Reference [28] is not correctly cited using brackets. They are missing on page 12.

Critical issue: An unattributed figure reproduction
The surge response curve in Fig. 15 is directly copied from a datasheet (same color, same fonts, same Format) from Littlefuse, with only some annotations added. In the reference section, there is the Littlefuse catalog cited (ref. [28]), but it is not mentioned in the figure caption. To the reviewer, this is a case of unattributed content reproduction, which may violate copyright policies and ethical standards. At a minimum, a proper citation is required. The authors must clarify the origin and ensure correct Attribution. They may also need to get permission from the copyright holder.

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Reviewer 3 Report

Comments and Suggestions for Authors

The article presents a valuable design, resulting in a complete study that includes the design procedure, simulation-based assessment, circuit manufacturing, and both electrical and thermal tests.

It may be helpful to improve the positioning of the article:

- In the Introduction, several commercial products as well as academic journal papers are mentioned. However, it would be useful to include a comparison table, which would also help justify the specific or novel design ideas developed in this work.

- In addition, it is somewhat surprising that current sensors for converters are not mentioned, given that current is the primary source of information regarding reliability, fault states, and device health within a converter. See, for example, the recent work: M. Mengozzi et al., "Integrated Hall-Effect Broadband Current Sensor for SiC Traction Inverter," 2025 IEEE International Workshop on Metrology for Automotive (MetroAutomotive), Parma, Italy, 2025, pp. 180-185, doi: 10.1109/MetroAutomotive64646.2025.11119253.

Figures 10 to 12 are not very clear. The authors might consider plotting them from a different perspective or using heatmaps.

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Reviewer 4 Report

Comments and Suggestions for Authors

The manuscript “Development of High Power DC Solid-State Power Controllers using SiC FETs for Aircraft Electrical System” presents a 270 V/300 A unidirectional DC SSPC based on parallel SiC FETs, with two main technical contributions: (i) a passive current-balancing strategy using an irregularly shaped busbar to equalize parasitics across 9 parallel devices, and (ii) an RC–TVS clamping network tailored to mitigate turn-off overvoltage considering TVS foldback and loop inductance. A thermal methodology (Foster model + LTspice) guides the device count (N = 9) and heatsink sizing; experiments report dynamic and steady-state current imbalance ≤ 7%, V_DS peaks ≈ 475–500 V under ~1.8 kA short-circuit, and thermal images aligning with model predictions. Overall, the work is practical and well-motivated for MEA/AEA HVDC distribution. 
The paper is technically sound with a coherent design–model–prototype chain and useful engineering guidance. Revisions below will improve reproducibility, aerospace relevance, and presentation quality without requiring fundamental rework:

• Gate-driver and protection details for reproducibility.
  Please add key driver parameters (gate resistances, Miller clamp/use of Kelvin source, DESAT/blanking thresholds, soft turn-off profile, OC detect latency, common-mode dv/dt immunity). Current results are convincing, but driver specifics are essential for replication and to explain the observed turn-off spikes and the 7% dynamic imbalance at turn-off.
• The current-sharing analysis assumes “consistent parameters.” Provide limits/tolerances used (R_DS(on), Q_g, V_th spreads; thermal contact variation) and a sensitivity check showing how the unbalance factor degrades with realistic spreads.
• Since the manuscript cites SAE AS4805A and IEC 60898-3 for protection curves, briefly discuss alignment (or limitations) regarding DO-160 EMC/ESD/lightning surge and environmental/altitude deratings that could influence TVS choice, busbar spacing/partial discharge, and sensing/communication robustness (CAN). Even a short “applicability & limitations” subsection would help positioning.

 

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Round 2

Reviewer 1 Report

Comments and Suggestions for Authors

thank you for answering and enhancing the manuscript 

Reviewer 2 Report

Comments and Suggestions for Authors

The revised article represents a significant improvement compared to the first version. My issues have been adressed and are now much better integrated in the article.

Especially: Figures are now clearer described and are much easier to read. Also Fig. 18 and the corresponding refernce are now clearly referenced.