Characterization and Reliability Analysis of Enhancement-Mode PEALD AlN/LPCVD SiN_x GaN MISFET with In Situ H₂/N₂ Plasma Pretreatment

Abstract

An effective in situ H₂/N₂ pretreatment technique for enhancement-mode GaN MISFET with a PEALD AlN/LPCVD SiN_x Dual Gate Dielectric is presented. This technique features in situ H₂ (15%)/N₂ (85%) plasma pretreatment prior to AlN deposition. By using in situ H₂ (15%)/N₂ (85%) plasma pretreatment and a PEALD AlN protection layer, combined with an LPCVD SiN_x gate dielectric, the quality of the AlN/GaN interface can be further improved due to the reduced interface trap densities between the AlN/GaN interface. The interface protection technique enables the successful integration of a high-quality PEALD AlN/LPCVD SiN_x gate dielectric in an E-mode GaN MISFET with high performance, high stability, and high reliability. The fabricated enhancement-mode GaN MISFET exhibits a high gate swing and high channel effective mobility of 187.5 cm²/Vs, a threshold voltage of 2.9 V defined at 1 µA/mm, an on/off current ratio of 10⁸, and a breakdown voltage of 1760 V defined at I_D = 10 μm/mm. Our experiments showed a significant reduction in dynamic ON resistance and the suppression of current collapse when using the enhancement-mode GaN MISFET with PEALD AlN/LPCVD SiN_x under high drain bias switching conditions, especially when the V_DS is greater than the 60 V drain bias switch operating state.

1. Introduction

As a wide band gap semiconductor material, GaN has a bright future in the field of power semiconductor devices due to its advantages of high thermal conductivity, a high breakdown electric field, and high electron saturation drift velocity. Two-dimensional electron gas (2DEG) with high concentration and high mobility could be formed in the AlGaN/GaN interface due to its strong polarization effect in III-nitrides. Gallium nitride-based high electron mobility transistors (HEMT) could provide low ON resistance, fast switching speed, and high-power handling ability in power switching applications [1]. However, the channel of traditional AlGaN/GaN HEMT is very close to the material interface, so the phenomenon of current collapse is caused by the interface state [1,2,3], especially under the condition of high drain voltage switching [4,5]. Various techniques are used to suppress current collapse, such as PECVD SiN surface passivation technology [6,7,8,9,10,11]; moreover, it is combined with field plate technology to suppress current collapse. In addition, various surface pretreatment techniques are used to improve interface quality and suppress current collapse [12,13]. In situ low-damage plasma pretreatment can remove primary oxides on the surface and minimize surface damage [14,15,16]. In situ PR passivation of plasma surfaces, such as NH₃ [17,18] or N₂O [13], has been proven to suppress current collapse and improve AlGaN/GaN HEMT reliability [19,20,21]. Research work on the switch features of PEALD AlN/LPCVD SiN_x Dual Gate Dielectric power HEMTs switching from the OFF-state at a high drain bias larger than 200 V is very rare [22,23,24,25].

In this paper, the research results demonstrate an effective in situ H₂ (15%)/N₂ (85%) pretreatment technique for gate-recessed enhancement-mode GaN MISFET with a PEALD AlN/LPCVD SiN_x Dual Gate Dielectric. The feature of the technique is an in situ H₂ (15%)/N₂ (85%) plasma pretreatment prior to AlN deposition. By using in situ H₂ (15%)/N₂ (85%) plasma pretreatment and a PEALD AlN protection layer, combined with an LPCVD SiN_x gate dielectric, the channel interface quality can be further improved due to the reduced interface trap densities between the AlN/GaN interface. Experiments have proven that current collapse suppression and dynamic ON resistance significantly reduce the normally-off GaN MISFET with PEALD AlN/LPCVD SiN_x under high drain bias switching conditions.

2. Device Fabrication

The AlGaN/GaN epitaxial structure studied here was grown in 6-inch p-type (111) Si substrates by metal-organic chemical vapor deposition (MOCVD). This includes the GaN buffer layer (4.2 μm), GaN channel layer (420 nm), AlN spacer layer (0.7 nm), Al_0.25Ga_0.75N barrier layer (24.5 nm), and GaN cap layer (2.4 nm). Device fabrication commenced with gate region definition by optical lithography, and the photoresist was used as a mask; the GaN cap layer of the opened regions was removed by SF₆-based reactive ion etching (RIE). The etching rate of the GaN cap layer was about 1 nm/min. Then, the GaN cap layer was used as a recess mask; the AlGaN barrier layer was effectively eliminated through a two-step process [26,27]. In the first step, thermal oxidation was performed at 650 °C for 50 min in the l4,508 tube annealing furnace. Taking advantage of the easy oxidation of Al atoms in AlGaN materials, the N atoms around Al atoms are replaced by O atoms to form Al-O bonds or Al-O-Ga bonds during oxidation at high temperatures. The oxidized AlGaN layer can be corroded using hot alkali solution. However, GaN material will not be oxidized at 650 °C and will be oxidized at higher temperatures. Therefore, as long as the oxidation temperature and time are well controlled, only the AlGaN material can be oxidized, the GaN material will not be oxidized, and oxidation will stop at the AlGaN/GaN interface.

The second step involves wet corrosion by TMAH solution treatment at 80 °C for 60 min. The products (AlO_x and GaO_x) of the AlGaN layer after high-temperature oxidation can be corroded by an alkali solution. The Ga-plane gallium nitride material cannot be effectively corroded by the alkali solution at 25 °C to 85 °C, so the corrosion can stop at the AlGaN/GaN interface. Figure 1a presents the AFM image and the corresponding depth curve of the recessed gate formed after high-temperature oxidation and TMAH corrosion, clearly demonstrating the complete removal of the barrier layer after thermal oxidation and wet etching. Then, gate dielectric deposition is carried out. The thickness of the PEALD AlN and LPCVD SiN_x were 5 nm and 30 nm, respectively, and various in situ plasma treatments were performed in the ANAME Elegant I PEALD system before the PEALD AlN was deposited. Ohmic contact Ti/Al/Ni/Au (22/140/55/44 nm) metal stacks were fabricated by e-beam evaporation followed by rapid thermal annealing for 30 s at 870 °C. The device planar isolation was formed by F-ion implantation. Finally, the gate region was defined by lithography techniques, and the Ni/Au gate metal stack was completed by e-beam evaporation.

Three kinds of samples of enhancement mode, also known as normally-off mode GaN MISFET with PEALD AlN/LPCVD SiN_x, were fabricated by different interface processing pretreatments: Sample 1, without pretreatment; Sample 2, with 400 W in situ NH₃ plasma pretreatment for 2 min before the PEALD AlN was deposited; and Sample 3, with 400 W in situ H₂(15%)/N₂(85%) plasma pretreatment for 2 min before the PEALD AlN was deposited. The fabricated devices had sizes of L_GS/L_G/L_GD/W = 2/2/20/20 μm. The schematic structure of the fabricated enhancement-mode PEALD AlN/LPCVD SiN_x Dual Gate dielectric GaN MISFET is shown in Figure 1b.

3. Results and Discussion

The electrical properties of the fabricated enhancement-mode PEALD AlN/LPCVD SiN_x GaN MISFET were measured by an Agilent B1505A Semiconductor Device Analyzer. Figure 2a demonstrates the transfer characteristics of the fabricated devices with V_DS = 15 V in a linear scale. The voltage of V_GS swept from −2 to 15 V, and the threshold voltage V_th was determined to be 2.6 V, 2.8 V, and 2.9 V at the drain current criterion of 1 µA/mm for Sample 1, Sample 2, and Sample 3, respectively. The geometrical dimensions of the samples had a gate-source distance (L_GS) of 2 μm, a gate length (L_G) of 2 μm, a gate-drain distance (L_GD) of 20 μm, and a gate width (W_G) of 20 μm. The I_Dmax was ~492 mA/mm, ~601 mA/mm, and ~631 mA/mm for Sample 1, Sample 2, and Sample 3, respectively, and the peak transconductance (G_m) values were ~58 mS/mm, ~76.2 mS/mm, and ~80.25 mS/mm for Sample 1, Sample 2, and Sample 3, respectively. The I_Dmax of Sample 3 increased by 28% compared with that of Sample 1 and 5% compared with that of Sample 2. Figure 2b shows the output characteristics of the devices. The R_on values of Sample 1, Sample 2, and Sample 3 were 18.3 Ω·mm, 15.9 Ω·mm, and 13.6 Ω·mm, respectively. The R_on of Sample 3 decreased by 33.6% compared with that of Sample 1 and by 14.6% compared with that of Sample 2.

Figure 3 shows the I_D-V_GS transfer curves of Sample 1, Sample 2, and Sample 3 on a semi-log scale at V_DS = 1V. The device is completely turned off at 0 V gate bias, and a truly enhanced operation is achieved. The drain current on/off ratio of the three sample devices is beyond ${10}^8$. The hysteresis values of the Vth between the V_G up and down sweep transfer curves were 0.40 V, 0.29 V, and 0.22 V for Sample 1, Sample 2 and Sample 3, respectively. The sub-threshold swing (SS) was 290 mV/dec, 198 mV/Dec, and 149 mV/dec for Sample 1, Sample 2, and Sample 3, respectively. The threshold voltage hysteresis of Sample 3 is very small because the in situ H₂ (15%)/N₂ (85%) plasma pretreatment prior to AlN deposition can effectively reduce the interface state density of the AlN/GaN.

In order to analyze the improvement effect of pretreatment channel interface quality and evaluate the interface trap distribution of samples 1, 2, and 3 using the conductance method [10], the conductance method was adopted in the MIS capacitor ring with a radius of 40 μm to extract the AlN/GaN interface trap density of the three samples, as shown in Figure 4a. Among the three samples, Sample 3 had the lowest interface trap concentration, which was about one order of magnitude lower than Sample 1. It can be seen that the AlN/GaN interface trap density (D_it) could be effectively reduced by using the PEALD AlN dielectric combined with in situ H₂ (15%)/N₂ (85%) plasma pretreatment.

In addition, the field effect mobility at low fields (${\mu }_{FE}$) for the three samples is also extracted in the linear region (V_ds = 0.1 V), as shown in Figure 4b, by calculating the effective mobility based on ${\mu }_{FE}=G_{m}L/W{C}_{ox}{V}_{DS}$[6], where L is the gate length, W is the gate width, C_ox is the dielectric capacitor measured from the FAT-FET device with L_G = 100 µm, and G_m is extracted from the transfer characteristic curves at V_DS = 0.1 V. The maximum field effect mobility (${\mu }_{FEmax}$) values for Sample 1, Sample 2, and Sample 3 were 116.6 cm²/Vs, 175 cm²/Vs, and 187.5 cm²/Vs, respectively. The mobility of Sample 3 was the highest due to the interface trap concentration inhibited by using the PEALD AlN dielectric combined with in situ H₂ (15%)/N₂ (85%) plasma pretreatment.

Figure 5a illustrates the gate leakage current of the PEALD AlN/LPCVD SiN_x GaN MISFET with a grounded source and drain. The gate voltage is defined as the gate breakdown voltage at an I_G of 1 μA/mm. It can be observed from Figure 5a that plasma pretreatment did not have an impact on the gate leakage current. Due to the high quality of the double-layer dielectric material, the gate leakage remains below 1 µA/mm until V_GS reaches 24.8 V. The high critical breakdown field strength of the double-layer dielectric indicates that the fabricated enhancement-mode GaN MISFET exhibits a high gate swing. Figure 5b presents the breakdown voltage characteristics of samples 1, 2, and 3 with a floating substrate and V_GS = 0 V. Sample 3 demonstrates a strong ability to block the current when V_GS= 0 V with a breakdown voltage of 1760 V. These data show that within the range of 0–560 V for drain voltage V_DS, the gate current I_GS is equivalent to the drain current I_DS, and increases with an elevated V_DS, which indicates the predominant role of gate-drain leakage current at this stage. In the range of 560–1100 V for drain voltage V_DS, the increase rate of I_DS surpasses that of I_GS significantly, indicating that the buffer layer leakage I_vertical begins to play a leading role in I_DS. When the V_DS is in the range of 1100–1760 V, the I_DS remain relatively stable. However, there is a rapid surge in I_DS with the increase in V_DS, resulting in device breakdown when V_DS exceeds 1760 V.

The output characteristics of samples 1 and 3 with V_GS step up (or down) from (or toward) below the threshold voltage V_th, as shown in Figure 6a,b. The drain current of Sample 1 in the high gate bias region was significantly lower when the gate bias stepped up from below the threshold voltage. This indicates that there is significant current collapse without pretreatment in Sample 1. For Sample 3, the drain current difference was very small between the gate bias voltage step-up and step-down, indicating that the in situ H₂(15%)/N₂(85%) plasma pretreatment inhibited current collapse.

To demonstrate the Vth thermal stability, we conducted the transfer characterizations at a temperature ranging from 25 °C to 100 °C in DC mode. The temperature-dependent transfer characteristics in the DC mode of the PEALD AlN/LPCVD SiN_x MISFET with in situ H₂/N₂ plasma pretreatment were measured with a V_GS sweeping rate of 0.7 V/s, a step of 0.1 V, and V_DS = 8 V. Figure 7 shows the transfer characteristics of the PEALD AlN/LPCVD SiN_x MISFET with and without in situ H₂/N₂ plasma pretreatment.

The temperature dependence of Vth (defined at I_D = 1μA/mm) in PEALD AlN/ LPCVD SiN_x MISFETs with and without in situ H₂/N₂ plasma pretreatment is shown in Figure 8. Owing to the reduced interface trap density, the MISFET with in situ H₂/N₂ plasma pretreatment shows a much smaller V_TH shift up to −0.12 V from room temperature to 100 °C than that of the MISFET without in situ H₂/N₂ plasma pretreatment. It has been proven that the device has good V_TH thermal stability. However, it should be noted that the study described in [27] did not include an investigation of this aspect.

In order to further study the effect of pretreatment process suppression on current collapse, the current collapse in the normally-off GaN MISFET with PEALD AlN/LPCVD SiN_x under high drain bias switching conditions was characterized. In the OFF-state stress stage, a gate bias V_G = 0 V lower than the threshold voltage is applied to the gate of the device to make the device reliably in the OFF-state, while V_DS is swept from 0 V to the present value (such as 30, 60, and 90 V). The OFF-state stress duration is 46 s; at the end of the OFF-state stress, the voltage V_G = 12 V, and V_DS = 1 V is rapidly applied to switch the device from the OFF-state to the ON-state, and the switching time is equal to 70 ms. By monitoring the test characteristics, an I_D current of not less than 120 mA/mm was obtained. The output characteristics were measured at the moment the device transitioned from the OFF-state to the ON-state to evaluate dynamic resistance. White light was illuminated on the sample after each OFF-state to ON-state sweep to effectively refresh the devices. The output characteristics of samples 1, 2, and 3 were tested using the above method, and the results are shown in Figure 9. The output characteristics in the absence of any drain bias stress are defined as “Fresh” states. As can be seen from Figure 9a,b, the phenomenon of current collapse is obvious in samples 1 and 2, which becomes more serious with the increase in OFF-state drain bias. Sample 3 exhibits much smaller current collapse, as shown in Figure 9c. The role of in situ H₂/N₂ pretreatment is mainly reflected in two aspects. First, because the plasma has higher energy, it can remove suboxide in the channel. Second, the N element in plasma can fill the N vacancy in semiconductor material, and the H element can react with surface oxide to remove the surface oxide layer. Thus, the oxygen concentration at the AlN/GaN interface is reduced and the slow response interfacial states caused by oxygen are reduced, which improves the interface quality [9,24]. These results indicate a significant reduction in dynamic ON resistance and the suppression of current collapse under high drain bias switching conditions of 180 V. From a reliability viewpoint, these findings differ from the reference [27].

For various L_GD devices, normalized dynamic R_on values of samples 1, 2, and 3 with varied OFF-state drain bias stress are shown in Figure 10. When the drain bias stress is greater than 60 V, the dynamic resistance of Sample 1 increases rapidly, while that of Sample 2 and Sample 3 increases very slowly, and the dynamic resistance of Sample 3 remains at a very small value. Therefore, in situ H₂/N₂ plasma pretreatment inhibits current collapse and achieves very low dynamic resistance.

4. Conclusions

An effective in situ H₂/N₂ pretreatment technique for enhancement-mode fully-recessed GaN MISFET with a PEALD AlN/LPCVD SiN_x Dual Gate Dielectric has been demonstrated in this study. Through research on the traps at the AlN/GaN interface and dynamic R_on for the normally-off PEALD AlN/LPCVD SiN_x GaN MISFETs with and without in situ H₂ (15%)/N₂ (85%) plasma pretreatment, it was found that this pretreatment leads to a significant reduction in dynamic ON resistance and the suppression of current collapse under high drain bias switching conditions, thereby reducing device transmission loss and improving reliability and channel interface quality. This work can be used as a reference for further optimization of enhancement-mode GaN MISFET devices of Si substrate.