GPR-Based Framework for Statistical Analysis of Gate Delay under NBTI and Process Variation Effects

Abstract

With the aggressive scaling of feature size, Negative Bias Temperature Instability (NBTI) and Process Variation (PV) have become major issues for circuit reliability and yield. In this paper, we analyze the variation of gate delay by jointly considering NBTI and PV effects. Using Gaussian Process Regression (GPR) learning interface, a Statistical Gate Delay Extraction (SGDE) framework is proposed. Typical types of logic gates are simulated with commercial 28 nm technology for verifying the performance of SGDE in the experiment. Compared to the golden data, the results show that our proposed approach achieves minimal loss of accuracy with significant runtime speed-up.

1. Introduction

The rapid scaling of CMOS technology has resulted in new reliability concerns, such as Electro Migration (EM), Stress Migration (SM), Negative Bias Temperature Instability (NBTI), Time-Dependent Dielectric Breakdown (TDDB), and Hot Carrier Injection (HCI), etc. [1]. The state-of-the-art research shows that among different aging mechanisms of technologies below 90 nm, NBTI is the most dominant factor, threatening reliability, and degrading performance (down to 80%) [2]. In this paper, we mainly focus on NBTI aging and investigate the effects on the reliability.

NBTI occurs in pMOS and it can be viewed in two stages (i.e., stress and recovery). When the gate of pMOS is under negative bias ($V_{gs}<0$), the threshold voltage of the transistor increases, leading to the decrease of drive current ($I_D$). Then, the reduction of $I_D$ in turn, results in the performance degradation of a circuit, and may eventually cause the breakdown of the whole electrical system. During the recovery phase, when the gate bias is OFF ($V_{gs}=0$), $\left|V_{th}\right|$ will decrease and partially recover to its initial value. NBTI degradation increases gradually with the above two phases back and forth [3].

Moreover, the impact of NBTI is exacerbated by Process Variation (PV), which results in a complex analysis of circuit reliability [4]. PV occurs in the processing steps during semiconductor production, causing differences between the intended device parameters in the design stage and the actual device parameters. Most of the prior works treated NBTI and PV as two independent issues and addressed the impact of each effect on IC reliability and performance separately. However, with the scaling of the technology node, considering both effects is an urgent need for tape-out flow [5]. PV, such as oxide thickness ($T_{ox}$) and initial threshold voltage ($V_{th0}$), will affect NBTI potentially.

In this paper, NBTI and PV have become the most prominent effects able to affect the circuit reliability, making greater challenges against the traditional gate delay characterization. Fortunately, Machine Learning (ML) algorithms can capture the underlying correlations between predictor variables. Among many features offered by ML, we are particularly interested in accelerating applications by replacing computationally expensive tasks with fast predictions.

In this article, we present an ML based framework (i.e., SGDE) to evaluate the variation of gate delay by considering the combined effect of NBTI and process variation. The main contributions of this work are as follows:

• Derive an abstract expression related to gate delay. From the expression, the main factors affecting the variation of gate delay are explicit, and the predictor variables and targets of ML can be determined easily. Using the ML model, we can eliminate the time-consuming SPICE simulations by the traditional process.
• Apply the ML model to a fast Monte–Carlo simulation. Our goal is not only to predict the individual outcome for a specified set of input features but also to evaluate the distribution of gate delay from numerous outputs. With the ML model, a predicting process can be completed with fast runtime, which enables the designers to evaluate the statistical characteristics of gate delay in a Monte-Carlo fashion.

The sections below will be expanded in this order: Section 2 introduces the background and previous research concerning NBTI degradation and PV. Section 3 illustrates the main idea and main contributions of our research. Section 4 reports the detailed experimental results and comparison with previous work. A summary and outlook are provided in Section 5.

2. Background and Related Work

2.1. NBTI Degradation

Nowadays, the reaction–diffusion (R–D) model is widely used to interpret the NBTI mechanisms [6]. According to the numerical solution of the standard reaction diffusion (R–D) model, The NBTI aging model equations were formed, which built the basic foundation for reliability research.

When a pMOS transistor is suffering a continuous stress period from $t_0$ to $t$, the threshold voltage will increase eventually, which can be expressed by Equation (1) [7].

$$\Delta V_{th}=\sqrt{K_v^2.{\left(t-t_o\right)}^{1/2}+\Delta V_{th1}^2}+{\delta }_v,$$

(1)

where

$$K_v=A_{NBTI}\times T_{ox}\times \sqrt{C_{ox}\left(V_{dd}-V_{th0}\right)}\times e^{(\frac{V_{dd}-V_{th0}}{T_{ox}\times E_0}-\frac{E_a}{k\times T})}$$

(2)

For a detailed parameter description, please refer to reference [7].

In a real situation, the gate voltage of pMOS cannot be constant. However, it will change simultaneously with different workloads. When $V_{gs}$ = 0, the threshold voltage of pMOS will partially recover. Equation about the $\Delta V_{th}$ of a pMOS transistor assuming the recovery happens at $t_0$, i.e., dynamic NBTI, is shown below [7].

$$\Delta V_{th}=\left(\Delta V_{th1}-{\delta }_v\right)\left(1-\sqrt{\eta \left(t-t_0\right)/t}\right)$$

(3)

In order to save computing resources during the long-term NBTI dynamic effect, a closed form of the transient aging model was proposed [8], which includes the recovery effect and is useful for the estimation of degradation by years. In this model, the total $V_{th}$ degradation after time $t$ has passed ($\Delta V_{th,t}$) is expressed as Equation (4).

$$\Delta V_{th,t}={\left(\frac{\sqrt{K_v^2.T_{clk}.\alpha }}{1-{\beta }_t^{1/2n}}\right)}^{2n}$$

(4)

where $T_{clk}$ and $\alpha$ refers to clock cycle and stress probability, respectively. Here, $\alpha$ is defined as the time ratio of the stress phase in the whole working time, i.e., ($\raisebox{1ex}{$t_{stress}$}\!\left/ \!\raisebox{-1ex}{$t_{stress}+t_{recovery}$}\right.$). ${\beta }_t$ is a parameter that has a relation with temperature, $T_{clk}$, $\alpha$, and $t$. When the clock frequency is higher than 10 kHz, there is little relation between $\Delta V_{th,t}$ and $T_{clk}$ [8]. In this case, the relationship between $\Delta V_{th,t}$ and $\alpha$ can be formulated as Equation (5).

$$\Delta V_{th,t}\approx {\left(\frac{0.001n^2{K}_v^2\alpha Ct}{0.81T_{ox}^2\left(1-\alpha \right)}\right)}^n$$

(5)

To simulate the degradation of NBTI, an accurate aging model card and efficient simulation analysis are urgently needed. In the industry, there are three mainstream aging APIs, namely, MOSRA, RelXpert, and Eldo, which are the products of Synopsys, Cadence, and Mentor Graphics respectively. In this work, we will use MOSRA, which is fully compatible with HSPICE, to model the gate-level degradation behavior if not particularly indicated.

2.2. Process Variations

In general, process variation (PV) is caused by the minor fluctuations of dopant atoms during fabrication, resulting in the variation of the device’s electrical parameters, which can be seen as a stochastic deviation from the device’s nominal behavior [9]. The PVs can be divided into the global and the local ones. Global variations affect all devices and interconnect on a die equally. Local variations have different effects on devices or interconnect inside a die, leading to the deviation between device parameters inside a chip after manufacturing.

In the past, these PVs did not greatly affect circuit performance. As the nodes of technology are scaling down, these variations, however, do not follow the scaling linearly but lag behind the pace. Consequently, the ratio of process variations to the nominal dimensions of devices becomes larger, which will affect the delays of logic gates significantly [10]. In this case, traditional corner-based circuit analysis methods present many limitations in considering the effects of process variations, and the delays of logic gates need to be modeled as random variables instead of fixed values in nanometer manufacturing nodes [10].

In these PVs, $T_{ox}$ together with $V_{th0}$ has become an integral part of the degradation of reliability, specifically while catering to the NBTI mechanism [11]. In many cases, these critical process variations are assumed to satisfy the Gaussian distribution, which will determine the statistical characteristics of gate delay.

2.3. Explicit Analytical Model

With the increase in reliability challenges, researchers have focused on analyzing the variations of gate delay. Several works have been available in the literature to consider the NBTI and PV issues jointly, which can be classified into the following categories.

2.3.1. Explicit Analytical Model

Yinghai Lu et al. in [5] proposed a nonlinear scalable statistical gate delay model, which considers both run-time gate working conditions and fabrication-induced process variation. In this paper, a set of process parameters, such as $V_{th0}$, $T_{ox},$ the channel width ($W_{eff}$) and the channel length ($L_{eff}$) are considered as random variables conformed with Gaussian normal distribution. They use the polynomial chaos expansion on the set of random variables to characterize the variation of gate delay degradation. The aging effects of each gate, including the means and the variances, are compared against the results of the corresponding 5000-point Monte-Carlo simulation.

In [12], the effects of the variation of the major process parameters ($T_{ox}$ and $V_{th0}$) on NBTI were analyzed. By the means of strict derivation, the probability density functions (PDFs) of the electric field generated on the gate oxidized layer ($E_{ox}$) and $\Delta V_{th}$ were obtained. Then, an analytical model of the degraded gate delay was proposed, from which the corresponding mean and the standard deviation can also be deduced. In the experiment, the compact gate delay model was verified by a 10,000-point Monte-Carlo simulation.

In [5,12], the relative gate delay change is approximated as a linear function of $\Delta V_{th}$, where the analytical model only involves one $\Delta V_{th}$, ignoring the possible $\Delta V_{th}$ occurring on other pMOS transistors. For a multi-input cell, such as a 2-input NOR gate, whether the designated input port has a rising or falling arc, the other port may maintain a low voltage level, which will affect the degradation of gate delay potentially. Ignoring this consideration, an optimistic analysis will be obtained.

2.3.2. Implicit Analytical Model

To capture the dependence of the gate output delay on the $\Delta V_{th}$ and other PV effects, [4] also proposed a gate delay model. Different from the literature [5,12], the gate delay model in [4] does not explicitly express the relationship with PVs, but is implicitly expressed by two fitting parameters. The fitting parameters can be extracted by intensive SPICE simulations of individual gates under various PV parameters ($L_{eff}$, $W_{eff}$ $V_{th0}$, $T_{ox}$, and ${\mu }_0$).

In [4], all pMOS transistors are assumed to be degraded at the same rate. Obviously, it will lead to a pessimistic result because some transistors may not produce Δ$V_{th}$.

Obviously, previous research works mainly focused on the analytical model. Nevertheless, an approach that can evaluate the statistical characteristics of gate delay by a low-runtime and high-accuracy method has not yet evolved. Our main work is to suggest a GPR-based framework to obtain the statistical result of gate delay by jointly considering the NBTI and PV effects. In addition to PVs, the predictor variables of the ML model include all the $\Delta V_{th}$ occurring on any pMOS transistor in a gate, which can avoid the pessimistic or optimistic analysis.

3. SGDE: GPR-Based Framework for Statistical Analysis of Gate Delay under NBTI and Process Variation Effects

3.1. The Effect of PV on NBTI

NBTI actually depends on several process parameters including $V_{th0}$, $T_{ox}$, etc., so that process variations actually interfere with the aging statistical impact [13]. In [4,5,12], several process parameters are included for estimating the gate aging effects. These works claim that circuit aging by NBTI could severely be affected by the magnitude of the process variations.

The main purpose of this chapter is to analyze the effect of PV on NBTI. Taking the INV gate as an example, it is to study the influence of PV on the $\Delta V_{th}$ of pMOS transistor in the gate. The INV gate is modeled using commercial 28 nm technology, where $V_{th0}$, $T_{ox}$, channel length offset due to mask/etch effect (XL) and channel width offset due to mask/etch effect (XW) are characterized as Gaussian random variables. The variance of each random parameter is set as 5% of its mean.

Table 1. Process parameters with nominal values and variation assumptions.

PV Source	$\mathbf{u}$	$\mathsf{\sigma }$
$V_{th0}$	−0.39 V	$0.05$
$T_{ox}$	1.485 nm	0.05 u
XL	3.5 nm	0.05 u
XW	18 nm	0.05 u

lists their nominal and standard deviation values. The supply voltage, working temperature, and stress time are set as 0.9 V, 100 °C and 10 years, respectively. To maximize the NBTI effect, continuous low voltage stress is supplied to INV.

Firstly, we analyze the distribution of $V_{th}$ during two different conditions, one only considering the $V_{th0}$ variation, and the other taking both the $V_{th0}$ variation and NBTI effect into account. By means of the Monte-Carlo simulation, we can obtain the probability density of $V_{th}$. The experimental results are shown in Figure 1. It is true that, when considering the combined effects, in addition to increasing the mean of $V_{th}$, the distribution of $V_{th}$ will become narrower to some degree.

Secondly, we consider the variation of $\Delta V_{th}$ affected by four different process parameters separately. The experimental results are shown in

Table 2. The statistical characteristics of $\Delta V_{th}$ by separate PV source.

PV Source	μ (mV)	σ (mV)
Vth0	59.1	0.53559
Tox	59.1	2.3012
XL	59.1	2.9589 × 10−3
XW	59.1	1.0208 × 10−3

. As for different PV sources, the mean of $\Delta V_{th}$ remains constant. On the other hand, the standard deviation of $\Delta V_{th}$ is dominated by the variation of $V_{th0}$ and $T_{ox}$, whose values are larger than that of XL and XW by about three orders of magnitude.

Thirdly, we consider the pairwise combinations. The specific combination and corresponding results are shown in Table 3, from which it can be concluded that:

• Compared with the result of single $T_{ox}$ variation (shown in Table 2), the combination of ($T_{ox}$ + $XL$) or ($T_{ox}$+$XW$) has the same effect on the variation of $T_{ox}$.
• Compared with the result of single $T_{ox}$ variation, when the combination of ($T_{ox}$+$V_{th0}$) is considered, the standard deviation of ∆$V_{th}$ will increase by nearly 8%. In this context, NBTI and the combined PV of ($T_{ox}$+$V_{th0}$) have become the most prominent effects able to affect the statistical characteristics of $\Delta V_{th}$.

Table 3. The statistical characteristics of $\Delta V_{th}$ by pairwise combined PV sources.

PV Sources	μ (mV)	σ (mV)
Tox + Vth0	59.1	2.4921
Tox + XL	59.1	2.3026
Tox + XW	59.1	2.3013

Table 3. The statistical characteristics of $\Delta V_{th}$ by pairwise combined PV sources.

PV Sources	μ (mV)	σ (mV)
Tox + Vth0	59.1	2.4921
Tox + XL	59.1	2.3026
Tox + XW	59.1	2.3013

3.2. Problem Formulation of Gate Delay

Just as explained above, variations of $V_{th0}$ and $T_{ox}$ have the greatest impact on NBTI. Therefore, here we only consider the combined effects of ($T_{ox}$ + $V_{th0}$). Moreover, for simplicity, the supply voltage, working temperature, and stress time are assumed to be constant, and the pMOS is suffering from a static NBTI stress.

The degradation of $V_{th}$ caused by the NBTI effect, denoted as $\Delta Vt{h}_{NBTI}$, can be expressed as a function of $V_{th0}$ and $T_{ox}$. Based on Equation (1), $\Delta Vt{h}_{NBTI}$ can be expressed as Equation (6).

$$\Delta Vt{h}_{NBTI}=f\left(V_{th0},T_{ox}\right)=K\times t_{ox}\times \sqrt{C_{ox}\left(V_{dd}-V_{th0}\right)}\times e^{\left(\frac{V_{dd}-V_{th0}}{t_{ox}\times E_0}-\frac{E_a}{k\times T}\right)}\times t^{0.25}$$

(6)

Using the first-order Taylor expansion, $\Delta Vt{h}_{NBTI}$ can be expressed as Equation (7).

$$\Delta Vt{h}_{NBTI}=f\left(u_0,u_1\right)+f_{V_{th0}}^{\prime }\left(u_0,u_1\right)\times \Delta V_{th0}+f_{T_{ox}}^{\prime }\left(u_0,u_1\right)\times \Delta T_{ox}$$

(7)

where $u_0$ and $u_1$ stand for the nominal value of $V_{th0}$ and $T_{ox}$ in the fresh state, respectively, $f\left(u_0,u_1\right)$ corresponding to the normal NBTI effect value without PV consideration. $f_{V_{th}}^{\prime }\left(u_0,u_1\right)$ represents the value at $u_0$ and $u_1$ after $f\left(V_{th0},T_{ox}\right)$ takes the first-order derivation of $V_{th0}$. Similarly,$f_{T_{ox}}^{\prime }\left(u_0,u_1\right)$ corresponds to the derivation of $T_{ox}$. Moreover, $\Delta V_{th0}$, $\Delta T_{ox}$ means the variation of $V_{th0}$,$T_{ox}$ is caused by PV, respectively.

Supposing $f\left(u_0,u_1\right)$ = $\Delta Vt{h}_{NBTI0}$, $f_{V_{th}}^{\prime }\left(u_0,u_1\right)$ = $k_1$, $f_{T_{ox}}^{\prime }\left(u_0,u_1\right)$ = $k_2$, Equation (7) can be simplified to:

$$\Delta Vt{h}_{NBTI}=\Delta Vt{h}_{NBTI0}+k_1·\Delta Vt{h}_{pv}+k_2·\Delta T_{ox}$$

(8)

The total $V_{th}$ variation for a pMOS transistor p in the given gate, denoted as $\Delta Vt{h}_{sum,p}$, is the summation of the contributions due to NBTI and PV effects, as given by Equation (9):

$$\Delta Vt{h}_{sum,p}=\Delta Vt{h}_{NBTI,p}+\Delta V_{th0,p}$$

(9)

Substituting $\Delta Vt{h}_{NBTI,p}$ with Equation (8), $\Delta Vt{h}_{sum,p}$ can be expressed as:

$$\Delta Vt{h}_{sum,p}=\Delta Vt{h}_{NBTI0,p}+(1+k_1).\Delta V_{th0,p}+k_2.\Delta T_{ox,p},$$

(10)

The first term of Equation (10) gives the normal value of the $V_{th0}$ shift due to NBTI, and the left reflects the joint impact of NBTI and PV on the variability of $V_{th0}$.

Following the alpha-power law, the relative gate delay change, i.e., $\Delta D$, can be approximated as a linear function of $\Delta V_{th}$.

$$\frac{\Delta D}{D_0}=h\Delta V_{th},$$

(11)

where $D_0$ is the nominal gate delay at fresh state.

Equation (11) is applicable to a gate with only one pMOS transistor. In this paper, the above equation is expanded as Equation (12), where m is the total number of transistors in a gate.

$$\frac{\Delta D}{D_0}=f\left(\Delta Vt{h}_{sum,1},\Delta Vt{h}_{sum,2},\dots \Delta Vt{h}_{sum,m}\right)$$

(12)

The final aged gate delay D with NBTI and PV effects jointly is described as follows.

$$D=D_0+\Delta D=D_0\times \left\{1+f\left(\Delta Vt{h}_{sum,1},\Delta Vt{h}_{sum,2},\dots \Delta Vt{h}_{sum,m}\right)\right\}$$

(13)

Assuming the PVs of each pMOS in a gate follow the same distribution and are independent, we can construct a function $\mathit{g}$ to map a set of constants and random variables to $D$. Based on Equation (10), $\mathit{g}$ is demonstrated in Equation (14).

$$D=g\left(D_0, \Delta Vt{h}_{NBTI0,1},\Delta Vt{h}_{NBTI0,2},\dots ,\Delta Vt{h}_{NBTI0,m},\Delta V_{th0},\Delta T_{ox}\right)$$

(14)

Equation (14) implicitly expresses the main factors which will affect the variation of gate delay. In the next step, what we focus on is exploring an ML method to learn the best $\mathit{g}$ based on smaller samples, instead of manually adjusting or fitting the functions and parameters laboriously.

3.3. GPR: An Efficiency Predictive Model

Here, a predictive model can be defined as a regression problem via supervised learning. GPR is among the state-of-the-art ML algorithms for performing nonlinear regression [14], which has been widely applied in many cases, such as high interconnect design [15,16], signal integrity and microwave circuit applications [17], speech synthesis [18], soil moisture and temperature sensing [19], fault detection of chemical processes [20], etc.

3.3.1. Introduction of GPR

For supervised learning, GP regression is a non-parametric and kernel-based method, which has the excellent potential of predicting results only with a small number of datasets, which is helpful in our case, as the generation of training data (i.e., the characterization process of gate delay) is time-consuming and expensive. GPR fit the data according to the specified kernel and dataset. Besides, we can compute the empirical confidence intervals over the predictions to assess the quality of GPR fits, due to its probabilistic properties. A brief mathematical introduction of GPR is given below.

Given an assumption that the computational model $y=M\left(x\right)$ follows a Gaussian Process (GP) prior, which can be written as [21]:

$$y\sim M\left(x\right)=GP\left(m\left(x\right),k\left(x,x^{\prime }\right)\right),$$

(15)

where $m\left(x\right)$ and $k\left(x,x^{\prime }\right)$ are the trend function and the covariance function.

The function $m\left(x\right)$ provides the mean function among one of them drawn from the GP prior. In the input parameter space, the covariance provides the correlation between the values of f($x$) at different points (i.e., the distance of $x$ and $x$’). The prior mean $m\left(x\right)$ can be a deterministic function (e.g., a metamodel obtained through any deterministic regression method).

The covariance function, K can be modeled using a kernel same as the SVM kernel, such as radial basis function (RBF), rational quadratic (RQ), Matern, cosine kernel, or a combination of many other kernels.

Concisely, the final predictive equations for the mean and covariance function about posterior GP are shown below [21].

$${\mu }_{{\mathit{x}}_{\ast }}=m\left({\mathit{x}}_{\ast }\right)+{\mathit{k}}_{\ast }^T{\left(\mathit{K}+{\mathsf{\sigma }}_n^2\mathit{I}\right)}^{-1}\mathit{y},$$

(16)

$${\sigma }_{{\mathit{x}}_{\ast }}^2=k_{\ast \ast }-{\mathit{k}}_{\ast }{\left(\mathit{K}+{\mathsf{\sigma }}_n^2\mathit{I}\right)}^{-1}{\mathit{k}}_{\ast }^T,$$

(17)

where $\mathit{y}={\left[y_1,\dots ,y_N\right]}^T,\mathit{K}\in R^{N\times N}$ is the correlation matrix evaluated on the input samples, such as the entries $K_{ij}=k\left(x_i,x_j\right), \mathrm{and} {\mathit{K}}_{\ast }=\left[\mathit{k}\left({\mathit{x}}_{\ast },{\mathit{x}}_{\mathbf{1}}\right),\mathit{k}\left({\mathit{x}}_{\ast },{\mathit{x}}_{\mathit{N}}\right)\right]\in R^{𝟙\times N}$ is a vector. $k_{\ast \ast }=k\left(x_{\ast },x_{\ast }\right)$ is a scalar and ${\sigma }_n^2$ is a hyperparameter representing the variance of a possible additive Gaussian noise corrupting the training set.

3.3.2. Use of GPR in NBTI and Process Variation-Aware Gate Delay Estimation

As explained in Equation (14), the input features of the GPR model include three parts: (i) the fresh gate delay $D_0$, (ii) all the $\Delta V_{th}$ occurred in a gate caused by the NBTI effect, i.e., $\Delta Vt{h}_{NBTI0,i} \left(1\le i\le m\right)$, and (iii) the change value of $V_{th0}$ and $T_{ox} \mathrm{by} \mathrm{PV}$, i.e.,$\Delta V_{th0}, \Delta T_{ox}$. The output is the comprehensive gate delay $D$. Supposing there are j training samples altogether, the training data can be constructed as Equation (15), where $T{R}_{in}$, $T{R}_{out}$ present the input and output features. Although the training samples are generated based on intensive Hspice simulation, it is a one-time process and the count is limited, which has little overhead as a whole.

$$T{R}_{in}=\left[\begin{array}{ccccc}{D}_0\Delta Vt{h}_{NBTI0,1}& \dots & \Delta Vt{h}_{NBTI0,m}& \Delta Vt{h}_{pv}^1& \Delta T_{ox}^1\\ D_0\Delta Vt{h}_{NBTI0,1}& \dots & \Delta Vt{h}_{NBTI0,m}& \Delta Vt{h}_{pv}^2& \Delta T_{ox}^2\\ & & ....& & \\ & & ....& & \\ D_0\Delta Vt{h}_{NBTI0,1}& \dots & \Delta Vt{h}_{NBTI0,m}& \Delta Vt{h}_{pv}^j& \Delta T_{ox}^j\end{array}\right] T{R}_{out}=\left[\begin{array}{c}{D}^1\\ D^2\\ \dots \\ \dots \\ D^j\end{array}\right]$$

(18)

When performing predicting operations, the data formats are similar to Equation (18), which are omitted here for limited space. The overall training and predicting processes are shown in Figure 2. In the dashed box, the left block is the prior GPR model, with the input of training data referring to Equation (18), then it transforms into the fit GPR, i.e., GP model with fit hyperparameter. The fit GPR is used for predicting eventually.

It is worth noting that a given foundry library, consists of hundreds of estimators, i.e., the fit GPR instances. The number of estimators depends on the number of cells in the library, the number of input terminals in each cell, and the input signal arc (rising or falling), just equaling the total number of LUTs (Look-up Table) in an STA (Static Timing Analysis) library.

3.4. SGDE: A Framework for Statistical Analysis of Gate Delay

With the GPR based learning interface, a predicting process can be completed with low runtime. This enables the designers to evaluate the statistical characteristics of gate delay in a Monte-Carlo fashion, the whole framework as shown in Figure 3.

As a whole, SGED can transfer both the NBTI and PV effects to the gate delay. The leftmost image in Figure 2 is the normalized probability density of a joint Gaussian distribution by $\Delta V_{th0} \mathrm{and} \Delta T_{ox}$, and the rightmost image is the probability density of gate delay. One predicting flow in the Monto-Carlo fashion comprises three major steps which can be interleaved iteratively: (i) sample selection, constructing the complete input features together with other information listed in Equation (18), (ii) GPR inference, and (iii) outputting the predicted result.

By generating a sufficiently large number of PV samples, the variability distribution of gate delay is appropriately manifested in the collection of results, from which the statistical characteristics of gate delay, i.e., mean and standard deviation value, can be calculated.

4. Numerical Experiment

4.1. Experiment Setup

We use Google’s Tensorflow integrated with GPflow [22] package machine learning framework to build our proposed GPR model for statistical analysis of gate delay. It is implemented in Python and runs on a desktop machine with an Intel Core i7(2.9 GHz) processor and 16 GB of DRAM. SciPy module is used in our framework to optimize the hyperparameters of kernel functions.

Several typical logic gates, such as INV, 2-input NAND (NAND2), and 2-input NOR (NOR2), are simulated in the experiment with commercial 28 nm technology. For each type of gate, $T_{ox}$ and $V_{th0}$ are considered as the PV sources. The mean and standard deviation values of the two PVs, and other settings are consistent with Section 3.1.

As for the GPR model, the prediction accuracy can be measured by two types of errors, i.e., the relative root mean-squared error (rRMSE) and the maximum absolute error (MAE), which can be obtained by Equations (19) and (20), respectively.

$$rRMSE=\sqrt{\frac{1}{N}{\sum }_{i=1}^N{\left(\frac{\widehat{D_i}-D_i}{D_i}\right)}^2}\times 100\%,$$

(19)

$$MAE=\frac{1}{N}{\sum }_{i=1}^N\left|\widehat{D_i}-D_i\right|,$$

(20)

where $\widehat{D_i}$,$D_i$ are the predicted and golden result of gate delay for a given sample.

Different from the GPR model, the output of SGED is a statistical result, whose accuracy is measured by absolute error (Abs.E) with the following equation:

$$\mathrm{Abs}.\mathrm{E}=\frac{\left|\widehat{St{a}_i}-St{a}_i\right|}{St{a}_i}\times 100\%,$$

(21)

where $\widehat{St{a}_i}$ is the experimental statistical result calculated through 10,000-point GPR predicted result, and $St{a}_i$ is the golden statistical result corresponding to the 10,000-point HSPICE simulation.

Considering GPR’s excellent predictive abilities over smaller datasets, only 100 samples are used as training data for the balance of training time and prediction accuracy.

4.2. Experiment Result

4.2.1. Kernel Selection of GPR Model

GPR has a diversity of kernel functions that have unique properties, describing different types of data structures. In the experiment, RBF, RQ and linear kernel are combined as a composite kernel (e.g., a sum of two product kernels: RBF*Lin + RBF*RQ), which can attain the best result. In terms of prediction accuracy, several individual kernels, such as RQ, RBF, Matern32, and Matern52, are compared with our proposed composite kernel. For a fair comparison, the GPR model with different kernel configurations has been trained under the same 100-point training data and evaluated under the same 10,000-point testing data. As for INV, NAND2, NOR2, the rRMSE and MAE of each case are shown in Figure 4a,b, respectively, which indicates the proposed composite kernel shows the best fitness and the lowest error. The number of input features for INV, NAND2 and NOR2 are 4, 5, and 5, respectively. In the next experiment, GPR will use the composite kernel by default.

4.2.2. Accuracy Comparation with SVM and LR Model

In this section, the accuracy of the GPR model is compared with the linear regression and support vector machine (SVM) obtained from Scikit-Learn framework [23]. For LR, we use the Ordinary least squares Linear Regression model. For SVM, 𝜖-SVR model is selected with the RBF kernel, where C was tuned within [1 × 10⁻⁵, 1 × 10⁵] and gamma was tuned within [1 × 10⁻², 1]. Epsilon in SVR was tuned within [0.001, 0.1]. For GP, the GPR model with a composite kernel, including RBF, RQ and linear kernel, for modeling the covariance matrix to improve the generalization of the model. The RBF kernel’s length scale was allowed to vary between 1 × 10⁻¹⁰ and 1 × 10³ during the training process and the overall model noise variance was set to 1.0 by default. The rRMSE and MAE of different ML methods are shown in Figure 5a,b, respectively, where the proposed GPR model exhibits the best predictive performance.

4.2.3. Verification of the SGED Framework

This section evaluates the proposed SGED framework as shown in Figure 3. As mentioned before, the statistical characteristics of gate delay, i.e., mean and standard deviation value, can be calculated based on a collection of data composed of 10,000-point GPR predicting results.

As shown in

Table 4. The statistical accuracy of SGDE framework.

	$\mathit{\mu } (\times {10}^{-12} \mathbf{s})$			$\mathsf{\sigma } (\times {10}^{-12} \mathbf{s})$
	Golden	Proposed	Abs.E	Golden	Proposed	Abs.E
INV	1.2749	1.2755	0.087%	0.04413	0.04382	0.621%
NAND	3.6517	3.6540	0.026%	0.15879	0.16012	0.011%
NOR	6.3836	6.3781	0.033%	0.91522	0.90518	0.583%

, the suggested SGED framework has an excellent performance in the mean ($\mathit{\mu }$) and the standard deviation ($\mathit{\sigma }$) prediction with high accuracy compared to the golden data. The lower the Abs.E is, the better prediction and fitting performance of the SGED framework are. Figure 6 outlines the probability density of the golden and predicted results for INV, NAND2, and NOR2, which show a good agreement between the two datasets. To cast more light on the prediction accuracy, we also include a scatter plot for three gates shown in Figure 7. It shows that our predicted results are close to the values obtained from the Hspice simulation.

The computational process overhead can be significantly reduced by the proposed method, nearly a speedup beyond three orders of magnitude. Every 10,000-point test data take about 4 h for the Hspice simulation, which is performed on Intel Xeon Gold 5118 2.3 GHz CPU. While SGED only takes about 6 s for the same number of test data performed on Intel i7-10700k 2.9 GHz CPU. Exhaustive Hspice simulation is strongly associated with the number of transistors inside the gate and thus is time-consuming work. However, the runtime of ML methods barely changed.

4.2.4. Accuracy Comparation between SGED and Other Literature

In order to verify the accuracy of our proposed SGED framework, comparisons are made between our experimental result and other literature [12], as shown in

Table 5. Accuracy comparation with literature [12].

	$\mathbf{Abs}.$$\mathbf{E} (\mathsf{\mu })$		$\mathrm{Abs}.\mathbf{E} \left(\mathsf{\sigma }\right)$
	Proposed	Literature [12]	Proposed	Literature [12]
INV	0.052%	0.20%	0.701%	1.21%
NAND	0.062%	0.12%	0.838%	1.94%
NOR	0.086%	0.13%	1.097%	2.08%

. Abs.E ($\mathsf{\mu }$) represents the absolute error of $\mathrm{mean} \mathrm{value}$, Abs.E ($\mathsf{\sigma }$) and so on. What needs to be pointed out here is that, for the sake of fairness, this experiment will be performed by 45 nm Nangate FreePDK45 instead of commercial 28 nm technology, and the standard deviations of PVs are set as 10% of each mean value. The implementation results show that our proposed SGED framework is better than the literature.

5. Conclusions

Device parameters that determine circuit performance will change over time Moreover, the impact of NBTI is exacerbated by PV, which results in greater variability in circuit performance. This paper proposes a GPR based framework, i.e., SGED, to evaluate the variation of gate delay by jointly considering the NBTI and PV effect. The experimental results show that our suggested framework can greatly reduce the runtime while ensuring accuracy.

In future work, more variable features will be integrated into the GPR model, such as temperature, stress time, stress probability, etc. On the other hand, the SGDE framework can also be applied to the circuit level for analyzing the variation of path delay.