Broadband Millimeter-Wave 5G Power Amplifier Design in 22 nm CMOS FD-SOI and 40 nm GaN HEMT

Abstract

Three millimeter-wave (mm-Wave) power amplifiers (PAs) that cover the key 5G FR2 band of 24.25 to 43.5 GHz are designed in two different state-of-the-art device technologies and are presented in this work. First, a single-ended broadband PA that employs a third-order input matching network is designed in a 40 nm GaN/SiC HEMT (High Electron Mobility Transistor) technology. Good agreement between the measurement and post-layout parasitic extracted (PEX) electromagnetic (EM) simulation data is observed, and it achieves a measured 3-dB BW (bandwidth) of 18.0–40.3 GHz and >20% maximum PAE (power-added-efficiency) across the entire 20–44 GHz band. Expanding upon this measured design, a differential broadband GaN PA that utilizes neutralization capacitors is designed, laid out, and EM simulated. Simulation results indicate that this PA achieves 3-dB BW 20.1–44.3 GHz and maximum PAE > 23% across this range. Finally, a broadband mm-Wave differential CMOS PA using a cascode topology with RC feedback and neutralization capacitors is designed in a 22 nm FD-SOI (fully depleted silicon-on-insulator) CMOS technology. This PA achieves an outstanding measured 3-dB BW of 19.1–46.5 GHz and >12.5% maximum PAE across the entire frequency band. This CMOS PA as well as the single-ended GaN PA are tested with 256-QAM-modulated 5G NR signals with an instantaneous signal BW of 50/100/400/9 × 100 MHz at a PAPR (peak-to-average-power ratio) of 8 dB. The data exhibit impressive linearity vs. P_OUT trade-off and useful insights on CMOS vs. GaN PA linearity degradation against an increasing BW for potential mm-Wave 5G applications.

1. Introduction

5G eMBB (enhanced Mobile Broadband) applications target 10 Gb/s download speeds and ×100 more wireless connected devices compared to 4G for mMTC (massive machine type communication), and sub-1 mS latency time for UR/LL (ultra-reliable low latency), mMTC [1]. However, to achieve all these goals for broadband operation, it is necessary to move up from the sub-6 GHz FR1 band to the millimeter-wave (mm-Wave) 5G FR2 band where more of the frequency spectrum is available. The power-added efficiency (PAE) and linearity for electronics and especially the power amplifiers (PAs) will be considerably lower in the FR2 band due to its much higher operation frequency and thus higher loss compared to the FR1 band. Because the PA can be the most power-hungry component in front-end modules (FEM), the mm-Wave PA is a critical barrier to overcome for low-power 5G circuits and systems in the FR2 band. For example, we may have to use more complicated mm-Wave phased array systems to achieve 3-D beamsteering in the 5G FR2 band, due to higher path loss at these frequencies. With more FEMs needed for phased arrays, inefficient systems will generate added heat and reliability issues. Additionally, to potentially reduce the total number of FEMs needed to cover the entire ~20 GHz BW (bandwidth) of the mm-Wave 5G FR2 band, it would be very attractive to have highly efficient and broadband mm-Wave PAs. In 5G user equipment (UE) and femto/picocells, the PA’s P_OUT will only need to be in the sub-Watt range of less than 20 dBm [2]. Thus, in this proposed work, we will investigate the design of mm-Wave PAs with excellent broadband peak PAE and good linearity that can cover the key 5G FR2 band in two state-of-the-art technologies that target this medium output power range.

Output power, frequency performance, size, and cost are inherent characteristics in every technology. For instance, even though devices in smaller technology nodes can generally achieve higher f_T, and thus better frequency performance, they have limited output power due to lower breakdown voltage (i.e., Johnson’s Limit [3]) compared to larger technology nodes. Additionally, wide-bandgap III-V technologies tend to have higher breakdown voltages and larger carrier transport mobilities compared to silicon technologies. Thanks to the thicker process layers and their semi-insulating substrates, III-V technologies also provide better low-loss on-chip passives, which is crucial for the high Q needed to achieve great power efficiencies and on-chip EM structures (e.g., baluns). Thus, silicon designers must devise ways to work around these intrinsic device limitations to provide power-efficient and robust designs comparable to those of best III-V technologies. However, silicon-based technologies offer more integrability and significantly lower costs, allowing for switches, LNA, and PA to easily coexist in the same die, providing the possibility for a one-chip solution and reducing the need for SiP (system-in-package) or heterogeneous integration.

The GaN technology used in this work is HRL Laboratories’ T3 40 nm GaN HEMT (High Electron Mobility Transistor) technology on a SiC substrate, which achieves V_BR of 50 V, f_T of 220 GHz and f_MAX of 400 GHz with a knee voltage of ~2 V, and I_D,MAX of ~1.6 A/mm [4]. This technology will be used in a single-ended PA design (i.e., GaN PA #1) as well as a differential design (i.e., GaN PA #2).

This work will also use Global Foundries’ 22FDX technology, which is a 22 nm FD-SOI (fully depleted SOI) CMOS process to design a differential cascode mm-Wave broadband PA. Devices in this technology achieve lower off-state leakage current due to the buried oxide layer and a fully depleted channel [5]. Our design uses SLVTNFET (i.e., super low threshold voltage NFET), which can achieve a peak f_T of ~350 GHz and a peak f_MAX of ~370 GHz in the smallest device. The 22FDX technology also enables back-gate biasing, allowing us to change the NFET threshold voltage (V_T) by back-gate controls to possibly adjust for V_T variation (from poly CD and short-channel effects), and can thus improve the yield for nm-CMOS and possibly improve linearity as well [6].

Figure 1 shows the simulated f_T and f_MAX of the 40 nm GaN HEMT and 22 nm CMOS FD-SOI devices used in our mm-Wave PA designs. Although the 22FDX PDK (process design kit) offers layouts up to mid-level metal layers, the parasitic up to the top metal layer is extracted using Calibre xACT R + C + CC extraction [7]. Here f_T and f_MAX are extrapolated when H₂₁ (small-signal current gain) and the value of G_MAX (maximum transducer power gain) are equal to unity, respectively (note: $G_{max}=|\frac{S_{21}}{S_{12}}|(K-\sqrt{K^2-1})$). For a fixed current density, it is clear from Figure 1b that f_MAX of the GaN device is much higher than those of the CMOS (by ~×2), suggesting it may be more suitable for low-power operations, even though Figure 1a shows CMOS can reach about the same f_MAX as the GaN device at a higher bias current (i.e., >10 mA).

In each of the two technologies, we have designed a differential PA, using neutralization capacitors to increase the maximum stable power gain (MSG) and reverse isolation. This technique has been explored in many previous works [8,9] and thus will not be discussed in detail here but we will instead just provide a brief review. From the MSG equation and the small-signal model of a MOSFET, for a differential pair with a neutralization capacitor C_x, Equation (1) can be derived where the parasitic gate to drain capacitance, C_gd, can be reduced by adding the neutralization capacitor C_x, and thus can increase the MSG of a differential amplifier [8,9].

$$G_S=\frac{\left|Y_{21}\right|}{\left|Y_{12}\right|}=\sqrt{\frac{g_m{}^2}{{\omega }^2{(C_{gd}-C_x)}^2}+1}$$

(1)

2. Design Methodology

Different design techniques and methodologies will be explored using these two technologies to achieve a very broad BW with good PAE performance. For example, a high-order input-matching network (3rd-order) has been used for the GaN technology, which improves the BW by adding additional zeros and poles to the PA’s transfer function. In the CMOS PA, RC feedback is utilized, which improves the BW with a small sacrifice to the maximum gain with feedback and by also adding an additional pole to the transfer function.

Load-pull simulations are performed in both technologies to help design these broadband PAs. For broadband operation, it is desirable to have the device’s optimum load for PAE near 50 Ω so that minimal impedance transformation is needed, reducing the number of lossy components to realize the narrow-band impedance transformation. In addition, it would be great to have a very small reactance at the device’s optimum load to minimize frequency dependence in the impedance to achieve good broadband performance.

Using load-pull simulations on several GaN devices of different sizes with measurement-based models performed in the Cadence AWR (Applied Wave Research) design environment, a 4 × 37.5 µm device is chosen for a good trade-off of high PAE and gain. The fundamental load-pull simulations for maximum PAE circles for the 4 × 37.5 µm device are shown in Figure 2 for V_DD = 4/6/12 V at 24 GHz and 37 GHz, respectively. Not only is the PAE lower for a 12 V supply compared to a 4/6 V supply, but the optimum load also has higher reactance, and thus may make it more difficult to achieve broadband results with 12 V operation. First, a single-ended PA is designed with input and output matching networks, RF choke, and 1 pF bypass capacitors all on-chip. Using the load-pull simulations, the output matching is designed using only 3 matching components (including the RF choke) to minimize the loss for high PAE. To achieve good broadband S₁₁ and increase the usable gain bandwidth, a 3rd-order input matching network is utilized (see Figure 4). The PA is biased at class A/B mode for a good trade-off of linearity and PAE. After this single-ended PA was designed and tested, a differential version was designed where neutralization capacitors are added to increase the gain, as will be discussed later.

In the CMOS FD-SOI technology, PAE and P_OUT load-pull simulations are performed in Cadence Spectre. First, these simulations are performed on a single-ended cascode device pair with parasitic elements again extracted up to the top metal layer as shown in the schematic in Figure 3a. These simulations are performed at around OP_1dB and indicate that at 24/37 GHz, the cascode device can achieve maximum PAE of 35.0%/33.0% and P_OUT,MAX of 11.9/11.8 dBm, respectively. Load-pulls simulations are then also performed on a differential cascode device pair with small neutralization capacitors (see Figure 3d), and they achieve maximum PAE and P_OUT,MAX values of 33.5%/32.5% and 14.8/14.5 dBm at 24/37 GHz, respectively (still at around OP_1dB). The optimal load impedance of maximum PAE and P_OUT,MAX can occur close to each other on the Smith Chart as indicated by the load-pull simulations, and thus, these devices can almost be simultaneously optimized for both PAE and output power. Additionally, load-pull simulations suggest that these devices could achieve broadband performance as the optimal load does not move far from 24 to 37 GHz.

As discussed previously, this differential PA design utilizes neutralization capacitors for gain and reserve isolation improvement. An RC feedback path is also added to improve the BW of this design. On-chip baluns and transformers are offered in this mature PDK, and this design utilizes one of these center-tapped on-chip baluns to convert the differential output to a single-ended RF_OUT, for output matching and feeding the V_DD. Due to this small technology node, ESD double diodes are added to all the gate pads to protect the PA from ESD events. The cascode device pair presented here is not quite designed in a classical cascode topology, as a gate capacitor of ~450 fF is used at the top cascode device in this work instead of using a larger capacitor to make a CG (common-gate) device’s gate a classic RF ground. This choice of “hybrid” design between a stacked vs. a cascode topology can still effectively mitigate the breakdown concerns by sharing the total voltage swing of the output of the PA across the bottom CS (common-source) and the top cascode device [10].

3. Results

For all of the measurements shown in this work, the RF input is probed and the DC voltages are provided by gold wire-bonded pads to a custom PCB (printed circuit board), where more bypass capacitors are added for better stability on all DC traces. Later in this paper, modulated 5G NR data will be used as the RF input signal, and the PAs are measured with the state-of-the-art mm-Wave PXIE (PCI express extensions for instrumentation) system by National Instruments (NI), which can produce modulated 5G NR signals of up to 1 GHz BW and up to 44 GHz [11]. In the following discussions, besides the 3-dB BW conventionally used, the BW of these PAs is often also compared by the absolute BW, defined as $2(\frac{f_H-f_L}{f_H+f_L})$ [12] where f_H is the upper frequency and f_L is the lower frequency of the 3-dB BW.

3.1. Single-Ended GaN (GaN #1) PA Measurement Results

Figure 4 shows the final schematic of the single-ended broadband GaN PA as well as the S-Parameter measurement vs. post-layout EM simulation. The EM simulations for the HRL GaN PDK are performed using Cadence’s AXIEM in AWR to include all layout parasitic elements. This PA achieves maximum S₂₁ of 12.5 dB and a small-signal 3-dB BW of 18–38.7 GHz (absolute BW = 73.0%) at V_DD = 6 V, and S₂₁ = 10.3 dB with BW = 18–40.3 GHz (or an absolute BW = 76.5%) at V_DD = 4 V. Although not plotted here, S-Parameter measurements with V_DD = 12 V shown in [13] achieved maximum S₂₁ = 13.0 dB with BW = 18.3–32.7 GHz (absolute BW = 56.5%). Thus, as the load-pull EM simulations had suggested, lowering the drain voltage makes this design more broadband. The S₂₁ modeling at V_DD = 4 V is not as accurate vs. V_DD = 6 V, which may be due to the 4 V model being constructed from extrapolation whereas the 6 V models are directly from measurements. However, we do see that the S₁₁ and S₂₂ do match well with simulations for both supply voltages of 4 V and 6 V.

The large-signal measurement results vs. post-layout EM simulations are shown in Figure 5 for V_DD = 4 and 6 V at 24, 28, and 44 GHz. This PA achieves a maximum PAE/P_SAT of 34.0%/18.6 dBm at 24 GHz, 42.1%/18.6 dBm at 28 GHz, and 21.6%/17.8 dBm at 44 GHz. With a 6 V supply, there is once again good agreement between the measurement and simulation data, and the PA achieves maximum PAE/P_SAT of 28.9%/20.1 dBm at 24 GHz, 34.6%/20.3 dBm at 28 GHz, and 19.1%/19.3 dBm at 44 GHz. Figure 6 shows the measured P_OUT,SAT and maximum PAE plotted across the frequency, which highlights the broadband performance of this PA as it is able to maintain greater than ~20% PAE across the entire band of 18–40 GHz for V_DD = 4 V and greater than 14% PAE with V_DD = 6 V. The peak PAE for V_DD = 4 V is much higher at above 42% at 28 GHz.

PA Linearity is then tested with 50, 100, 400, and 9 × 100 MHz 256-QAM-modulated 5G NR inputs at PAPR (peak-to-average-power ratio) = 8.0 dB at 24 GHz and V_DD = 4 V (Figure 7). With P_OUT,AVE = ~11 dBm, this PA achieves ACLR −/+ (adjacent channel leakage ratio) of −27.6/−27.0 dBc with BW = 50 MHz (PAE_AVE = 13.3%), −27.4/−27.2 dBc with BW = 100 MHz (PAE_AVE = 12.1%), −26.7/−26.8 dBc with BW = 400 MHz (PAE_AVE = 11.8%), and −25.5/−26.0 dBc with BW = 9 × 100 MHz (PAE_AVE = 12.0%). The signal BW is varied from 50–900 MHz at 24, 28, 37, and 39 GHz, and the measured ACLR vs. BW is plotted in Figure 8 all at P_OUT,AVE ~11 dBm when V_DD = 4 V, and P_OUT,AVE = ~12 dBm with V_DD = 6 V. Figure 8 shows that there is not a significant degradation in the PA linearity increasing the 5G NR signal BW from 50 MHz to 9 × 100 MHz at 28, 37, and 39 GHz, and only a slight degradation (~2 dBc) in the measured ACLR at 24 GHz for both V_DD = 4 V and 6 V. Additionally, there is minimal degradation on the linear output power, increasing from 24/28 GHz to 37/39 GHz.

3.2. Differential GaN (GaN #2) PA PEX EM Simulation Results

The single-ended broadband GaN PA discussed above was then used to form a differential broadband mm-Wave 5G PA as shown in Figure 9, where the CS topology is used and the neutralization capacitors are added for improved MSG and for comparison purposes against a reasonably similar differential FD-SOI CMOS PA that will be presented later in this paper. Additional RC traps were added at the gates of these GaN transistors to further stabilize the PA, and this differential design has an area of 1.94 mm² (with pads), slightly larger than the 1.85 mm² area of the single-ended design. PEX EM simulations indicate that this differential GaN PA achieves a maximum S₂₁ of 13.4 dB, with a 3-dB BW from 20.1–44.3 GHz (or an absolute BW of 75.2%) at V_DD = 6 V, of which the BW is comparable to the single-ended GaN #1 design, but with a significantly higher gain and P_OUT.

The large-signal EM simulation results for this differential GaN PA are shown in Figure 10, which indicates that this PA can achieve a maximum PAE of 24.9%/26.6%/23.3% and P_OUT,SAT of 23.5/23.6/23.3 dBm at 24/28/44 GHz. Figure 11 shows the broadband nature of this PA, as it is able to achieve >20% maximum PAE across the 20–44 GHz band, and has a very high simulated 1-dB P_OUT,SAT BW and also P_OUT,SAT larger than ~23 dBm in the 5G FR2 band of interest. Compared to the measured GaN #1 PA, it achieves a similar maximum PAE, while having ~3 dB greater P_OUT,SAT than the single-ended design. We will discuss another broadband differential mm-Wave 5G PA designed in 22 nm FD-SOI CMOS next.

3.3. Differential Cascode CMOS PA Measurement Results

Figure 12 presents the schematic of the differential cascode CMOS PA designed in the 22FDX technology and the small-signal S-parameter measurement data compared to post-layout PEX simulations of this PA. Layout parasitic elements for this design were extracted using Mentor Graphic’s Calibre R + C + CC extraction. Small-signal measurement data agree well with the PEX simulations, exhibiting excellent broadband performance. PEX simulations achieve a maximum S₂₁ small-signal gain of 17.4 dB with 3-dB BW of 20.5–47.4 GHz (or an absolute BW of 79.2%), while measurement achieves a 3-dB BW of 19.1–46.5 GHz and a maximum S₂₁ = 16.4 dB (absolute BW of 83.5%). The RC feedback network allows for adequate input matching with S₁₁ < −5.5 dB across the entire ~27 GHz band in both simulation and measurement values. Thus, measurement data display virtually no degradation on the targeted small-signal broadband BW to cover the entire key 5G FR2 band of 24.25–43.5 GHz, as indicated by the PEX simulations, and only minimal degradation in measured vs. the simulated values of small-signal gain.

The effect of the RC feedback on this differential CMOS SOI PA design is also simulated here in post-layout PEX simulations in Figure 12d, where the original design is compared to the same design with the only change being that the RC feedback is removed (and the PA layout is re-extracted and re-simulated). Here, it shows that the overall gain is reduced by ~2 dB when RC feedback is added, as this PA without the RC feedback achieves a maximum S₂₁ = 19.6 dB. However, the BW is increased when RC feedback is added, as, without it, the 3-dB BW decreases to 20.9–39.6 GHz (or an absolute BW of 61.8%). Thus, the absolute BW is degraded by ~15% without the RC feedback, and the input/output matching worsened considerably as well.

The large-signal measured data vs. PEX simulation results at 24/28/44 GHz are shown in Figure 13, where degradation in the large-signal measurement data from simulations is seen, likely due to inaccuracies in the large-signal transistor modeling. These figures show that at 44 GHz, the measured gain is 3 dB higher than those of the PEX EM simulations. The measured gain values are usually reduced by 1–2 dBs from the simulated data at 24–39 GHz, while at 24/28/44 GHz this broadband PA achieves measured OP_1dB of 11.5/9.2/7.4 dBm with PAE @OP_1dB of 18.6%/11.2%/9.3%, P_SAT of 14.6/14.0/10.9 dBm, and maximum PAE of 26.1%/19.9%/12.5 %, respectively.

Figure 14 plots the measured maximum PAE, S₂₁, and P_OUT,SAT vs. the frequency from 20–44 GHz, which shows this PA maintains a maximum PAE ≥ 12.5% and P_OUT,SAT ≥ 11 dBm across this frequency range. It achieves a maximum PAE ≥ 15.1% and P_OUT,SAT ≥ 12.9 dBm across 24–39 GHz, highlighting the broadband performance of this CMOS PA.

As has been conducted with GaN design #1, this CMOS PA’s linearity is tested with 50/100/400/9 × 100 MHz 256-QAM NR input signals with the same PAPR = 8.0 dB and same NI PXI equipment at 24 GHz, and the PA output spectra are shown in Figure 15. With the same output power of P_OUT,AVE = ~7 dBm, at the instantaneous signal BW = 50 MHz this PA achieves an ACLR −/+ of −28.0/−29.4 dBc (PAE_AVE = 7.3%), with BW = 100 MHz, −27.6/−28.8 dBc (PAE_AVE = 7.0%), with BW = 400 MHz, −27.3/−27.0 dBc (PAE_AVE = 7.7%), and with BW = 9 × 100 MHz, −24.6/−25.9 dBc (PAE_AVE = 8.1%).

Similarly, this PA’s linearity is also tested at 50–900 MHz BW at several other frequencies in the 5G FR2 band. When varying the BW of a 256-QAM 5G NR signal (PAPR = 8 dB) at 24 GHz and 28 GHz, the P_OUT,AVE is about 7 dBm, and at 37 GHz and 39 GHz, P_OUT,AVE is approximately ~6 dBm. Figure 16 also shows interesting ACLR measurement data vs. signal BW. When the BW is increased from 50 MHz to 100 MHz, the linearity is not affected much, but when increasing it from 100 MHz to 400 MHz, the PA’s linearity is degraded by a small but noticeable amount of ~1–3 dB. Then, increasing the BW from 400 MHz to 9 × 100 MHz, the linearity becomes further degraded by an additional ~2 dB at all frequencies measured. Although, this CMOS PA’s linear output power only degrades by ~1 dB when its operating frequencies change from 24/28 GHz to 37/39 GHz.

4. Discussion

In the previous sections, three different PAs from two different technologies were presented. Typically, GaN is used for higher-power applications, but the designs in this work are all targeted to perform in the sub-Watt range. Small-signal measurements matched well with PEX simulations for both GaN #1 and the CMOS PA. However, large-signal measurement results did not match well for the CMOS PA, whereas large-signal measurements for the GaN #1 for V_DD = 6 V matched the simulation results rather well. Although measurements have not been taken on GaN #2 as this design is in the process of being fabricated, measurements on GaN #1 showed good agreement with EM simulations for V_DD = 6 V and thus will be compared to the other PAs here with V_DD = 6 V. Although the 22 nm FD-SOI CMOS PA used several power-performance improvement techniques (i.e., cascode and differential operation), the comparison of the three PAs in Figure 17 and

Table 1. Comparison of the three Broadband mm-Wave PAs presented in this work.

Tech.	Design	VDD (V)	3-dB BW (GHz)	Freq. (GHz)	POUT,sat (dBm)	P1dB (dBm)	Peak PAE (%)	Gain (dB)	Signal Type	ACLR (dBc)
22 nm CMOS FDSOI	Cascode with RC feedback; Differential	1.8	19.1–46.5 (79.2%)	24	14.6	11.5	26.1	15.7	400 MHz 256-QAM 5G NR	−27@POUT = 7.1 dBm
										PAE = 7.7%
									9 × 100 MHz 256-QAM 5G NR	−24.6@POUT = 7.3 dBm
										PAE = 8.1%
				28	14.0	9.2	19.9	14.5	400 MHz 256-QAM 5G NR	−27.1@POUT = 7.1 dBm
										PAE = 5.3%
									9 × 100 MHz 256-QAM 5G NR	−23.7@POUT = 6.6 dBm
										PAE = 6.2%
				39	12.9	9.6	15.2	14.7	400 MHz 256-QAM 5G NR	−26.6@POUT = 6.4 dBm
										PAE = 5.8%
									9 × 100 MHz 256-QAM 5G NR	−24.2@POUT = 5.6 dBm
										PAE = 5.0%
				44	10.9	7.4	12.5	15.5	N/A	N/A
40 nm GaN	3rd-Order Input Matching; Single-ended	4	18–40.3 (76.5%)	24	18.6	13.6	34	7.8	400 MHz 256-QAM 5G NR	−25.4@POUT = 11.9 dBm
										PAE = 15.4%
									9 × 100 MHz 256-QAM 5G NR	−27.7@POUT = 9.7 dBm
										PAE = 8.1%
				28	18.6	13.2	42.1	9.2	400 MHz 256-QAM 5G NR	−27.2@POUT = 11.2 dBm
										PAE = 13.1%
									9 × 100 MHz 256-QAM 5G NR	−27@POUT = 11.3 dBm
										PAE = 13.9%
				39	17.2	13.4	26.0	8.7	400 MHz 256-QAM 5G NR	−27@POUT = 11.1 dBm
										PAE = 11.1%
									9 × 100 MHz 256-QAM 5G NR	−25.6@POUT = 11.3 dBm
										PAE = 11.9%
				44	17.8	12.8	21.6	7.2	N/A	N/A
		6	18–38.7 (73.0%)	24	20.1	14.9	28.9	9.6	400 MHz 256-QAM 5G NR	−26.5@POUT = 11.9 dBm
										PAE = 10.2%
									9 × 100 MHz 256-QAM 5G NR	−27@POUT = 11.9 dBm
										PAE = 10.2%
				28	20.3	14.4	34.6	11.9	400 MHz 256-QAM 5G NR	−26.3@POUT = 14.0 dBm
										PAE = 13.0%
									9 × 100 MHz 256-QAM 5G NR	−26.8@POUT = 14.2 dBm
										PAE = 14.0%
				39	18.1	12.3	22.8	9.3	400 MHz 256-QAM 5G NR	−28.7@POUT = 11.4 dBm
										PAE = 9.2%
									9 × 100 MHz 256-QAM 5G NR	−28@POUT = 11.8 dBm
										PAE = 9.7%
				44	19.3	13.9	19.1	8.1	N/A	N/A
40 nm GaN *	3rd-Order Input Matching; Differential	6	20.1–44.3 (75.2%)	24	23.5	17.5	24.9	12.5	N/A	N/A
				28	23.6	18.3	26.6	13.3	N/A	N/A
				39	23.6	18.7	27.9	11.7	N/A	N/A
				44	23.3	17.4	23.3	10.4	N/A	N/A

* PEX EM Simulation.

show that the P_OUT,SAT is significantly higher for the broadband single-ended or differential GaN PAs vs. the CMOS PA. This could be explained by the superior breakdown performance of GaN over the CMOS technologies, enabling larger output voltage swings per device. GaN #2 and the 22FDX PA both used a differential topology and have similar gain, and the PAE as well as P_OUT appears superior for the GaN #2 PA vs. those of the CMOS-SOI PA. However, the broadband differential CMOS FD-SOI PA is much smaller than the GaN PAs in die size, with slightly higher power gain (but much lower P_OUT,SAT vs. GaN PAs), and it also includes an output balun, highlighting the excellent integrability of this CMOS technology. Using aggressive 256 QAM-modulated 5G NR input waveforms, great design insights can be gained from the measured ACLR vs. frequency on the signal BW vs. linearity and P_OUT,Linear for these two device technologies. When the signal BW is increased from 50 MHz to 900 MHz, the ACLR is degraded by ~2 dBc for GaN #1 for both V_DD = 4 V and 6 V at 24 GHz and virtually does not degrade at 28, 37, and 39 GHz. However, for the CMOS PA, the ACLR degrades with this broadened signal BW by ~4 dBc at all the carrier frequencies tested. Thus, this 40 nm GaN/SiC technology appears to have better linearity against very wide GHz 256QAM-modulated 5G NR signals across the FR2 band, and offers significantly higher P_OUT,Linear and P_OUT,SAT than the 22FDX CMOS technology. However, as we do not have measured P_OUT,Linear data for the differential GaN #2 yet, we could not ascertain if the superior P_OUT,Linear of broadband GaN PAs is mainly due to the device technology difference (i.e., GaN or FD-SOI), the cascode vs. common-source topology difference, the single-ended vs. differential topology difference, or something else (such as the output balun and/or matching details). Therefore, more detailed studies with additional measurement data are required to illuminate and clarify this important point in the future.

Our GaN PAs are compared to other state-of-the-art medium-power broadband mm-Wave 5G PAs in

Table 2. Literature comparison of the three broadband mm-wave PAs presented in this work to other broadband state-of-the-art mm-wave PAs.

Ref.	Tech.	Design	Supply Voltage (V)	3-dB BW (GHz)	Freq. (GHz)	POUT,sat (dBm)	P1dB (dBm)	Peak PAE (%)	Gain (dB)	Signal Type	ACLR (dBc)
[14]	65-nm CMOS	Multi-port load-pulling	1.1	26–42 (47.1%)	28	19	19	21	15	1 GHz 64-QAM OFDM	POUT = 7.5 dBm
											PAE = 5.1%
					37	19.6	16	21.9	16	2 GHz 64-QAM OFDM	−25@POUT = 9.8 dBm
											PAE = 10.2%
[15]	0.2 µm GaN on SiC	3-stage Harmonic Tuning	28	29–34 (55.1%)	33	39.5	-	36	25	-	-
[16]	0.1 µm GaN on SiC	One-order synthesized transformer network	12	18–40 (75.9%)	25	30	25 **	23.6	18 **	-	-
[17]	0.15 µm GaAs	Transformer-Coupled	4	21.6–32.5 (40.3%)	28	26.5	24.6	31	12.6	64QAM 6 Gb/s	−30@POUT = 21.6 dBm
											PAE = 13.5%
										64QAM 9 Gb/s	−30@POUT = 19.9 dBm
											PAE = 9.5%
[18]	130-nm SiGe	2-stage Doherty	1.5	23.3–39.7 (52.1%)	28	16.8	15.2	20.3	18.2	64-QAM 500 MSym/s	−28.4@POUT = 9.2 dBm
											Coll. Eff. = 18.5%
					37	17.1	15.5	22.6	17.1		−28.2@POUT = 9.5 dBm
											Coll. Eff. = 19.2%
					39	17	15.4	21.4	16.6		−29.8@POUT = 9.3 dBm
											Coll. Eff. = 17.2%
[19]	45-nm SOI CMOS	Continuous Hybrid Class F/F−1	2	23–40.5 (51.1%)	28	18.9	16.9	43.2	18.7	64-QAM 500 MSym/s	−28@POUT = 10.3 dBm
											PAE = 13.1%
					37	18.9	17	37	18		−30.5@POUT = 11.7 dBm
											PAE = 11.9%
					39	18.9	17.4	36	15.6		−28@POUT = 11 dBm
											PAE = 10.2%
[20]	45-nm SOI CMOS	Compensated Distributed Balun	2	25.8–43.4 (50.9%)	24	20.0	19.6	38.9	20.1 *	800 MHz 64-QAM 2-CC OFDM 5G NR	−25.2@POUT= 10.9dBm
											PAE = 14.2%
					37	20.0	18.9	38.7	19.9 *		−27.9@POUT = 10.2 dBm
											PAE = 13.6%
					39	19.1	18.0	38.6	20.0 *		−26.1@POUT = 10.2 dBm
											PAE = 13.4%
This work	22-nm CMOS FDSOI	RC feedback 1-stage diff.	1.8	19.1–46.5 (83.5%)	24	14.6	11.5	26.1	15.7	9 × 100 MHz 256-QAM 5G NR	−24.6@POUT = 7.3dBm
											PAE = 8.1%
					28	14.0	9.2	19.9	14.5		−23.7@POUT = 6.6 dBm
											PAE = 6.2%
					37	13.6	9.5	18.5	15.4		−23.7@POUT = 6.0 dBm
											PAE = 5.4%
					39	12.9	9.6	15.2	14.7		−24.2@POUT = 5.6 dBm
											PAE = 13.9%
This work	40-nm GaN	3rd-order input match 1-stage	4	18–40.3 (76.5%)	24	18.6	13.6	34	7.8	9 × 100 MHz 256-QAM 5G NR	−27.7@POUT = 9.7 dBm
											PAE = 8.1%
					28	18.6	13.2	42.1	9.2		−27@POUT = 11.3 dBm
											PAE = 13.9%
					39	17.2	13.4	26.0	8.7		−27.9@POUT = 10.8 dBm
											PAE = 12.6%
This work	40-nm GaN *	3rd-Order Input Matching; Differential	6	20.1–44.3 (75.2%)	24	23.5	17.5	24.9	12.5	N/A	N/A
					28	23.6	18.3	26.6	13.3	N/A	N/A
					39	23.6	18.7	27.9	11.7	N/A	N/A
					44	23.3	17.4	23.3	10.4	N/A	N/A

* PEX EM Simulation; ** Estimated graphically.

, as well as against some GaN PAs in the literature with higher power values, as most available mm-Wave GaN PAs in the literature are targeted at higher-power applications without optimizing for high PA linearity. Although GaN #2 still requires measurement results for validation, Table 2 shows that both of our GaN PAs achieve some of the best small-signal 3-dB BW as well as good PAE. Additionally, the GaN #1 design achieved excellent measured BW and good linearity with aggressive 5G NR signal modulation and instantaneous ~1 GHz signal BW, which have not been reported in prior medium-power mm-Wave GaN PAs [13]. Depending on the application, this GaN technology allows for the V_DD to be varied from 12 V to 4 V to achieve the optimal trade-off of PAE and output power. Although operating this PA at V_DD = 4 V reduces POUT with an increase in cost, being able to vary the supply voltage like this is not as easily feasible for silicon-based stacked broadband mm-Wave PAs. Thus, we conclude our GaN #1 PA exhibits excellent 3-dB BW, peak and linear PAE, and P_OUT,Linear with stringent 256-QAM modulation and a rather large instantaneous signal BW of 9 × 100 MHz across the key 5G FR2 band; it is among the best broadband linear mm-Wave medium-power PAs in the literature.

Our 22 nm broadband CMOS SOI PA vs. other state-of-the-art broadband medium-power mm-Wave PAs is also shown in Table 2. Our CMOS PA achieves the best small-signal 3-dB BW in the literature, and it has obtained good broadband linearity/PAE_LINEAR. It is also tested with the most stringent modulation (i.e., 256-QAM) and has a rather large instantaneous signal BW (i.e., 400 MHz and 9 × 100 MHz).

5. Conclusions

This work presented three different, very broadband, linear, and efficient PAs that can operate over the entire key mm-Wave 5G FR2 band of 24–44 GHz in two different state-of-the-art semiconductor IC technologies. Using a third-order input-matching network, a broadband, single-ended 40 nm GaN PA was designed (i.e., GaN PA #1), achieving excellent performance from 18 to 44 GHz, with the highest measurement maximum PAE/P_OUT,SAT of 42.1%/18.6 dBm at 28 GHz at V_DD = 4 V. Small-signal and large-signal CW measurement data matched EM PEX simulations well, with maximum PAE above ~20% across the entire frequency band. When inserting a 256-QAM 5G NR signal varying in BW from 50 MHz to 9 × 100 MHz at 24, 28, 37, and 39 GHz, there is virtually no degradation in the linearity as measured by ACLR for this GaN #1 PA. This PA is used to design a broadband differential PA with neutralization capacitors in the same GaN technology (i.e., GaN PA #2), which achieves similar PAE and BW in PEX EM simulations as the single-ended version, but with higher ~3 dB gain and higher P_OUT,SAT, as expected. Finally, a broadband 22 nm FD-SOI CMOS PA was designed, achieving excellent broadband results in the FR2 band with an RC feedback network and differential topology using neutralization capacitors. It achieves a 3-dB BW of 19.1–46.5 GHz and a good maximum PAE of 26.1% at 24 GHz and maintains a maximum PAE above 15.1% across the entire 24–39 GHz. Compared to the GaN #1 PA, increasing the 256-QAM 5G NR signal BW from 50 MHz to 9 × 100 MHz degrades the ACLR linearity of the CMOS PA more, suggesting that the GaN PA may be able to deliver significantly higher P_OUT,Linear and P_OUT,SAT than their CMOS counterparts for mm-Wave 5G applications, albeit at a considerably higher cost with a lower level of monolithic integration.