Valpreda, E.; Morì, P.; Fasfous, N.; Vemparala, M.R.; Frickenstein, A.; Frickenstein, L.; Stechele, W.; Passerone, C.; Masera, G.; Martina, M.
HW-Flow-Fusion: Inter-Layer Scheduling for Convolutional Neural Network Accelerators with Dataflow Architectures. Electronics 2022, 11, 2933.
https://doi.org/10.3390/electronics11182933
AMA Style
Valpreda E, Morì P, Fasfous N, Vemparala MR, Frickenstein A, Frickenstein L, Stechele W, Passerone C, Masera G, Martina M.
HW-Flow-Fusion: Inter-Layer Scheduling for Convolutional Neural Network Accelerators with Dataflow Architectures. Electronics. 2022; 11(18):2933.
https://doi.org/10.3390/electronics11182933
Chicago/Turabian Style
Valpreda, Emanuele, Pierpaolo Morì, Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Lukas Frickenstein, Walter Stechele, Claudio Passerone, Guido Masera, and Maurizio Martina.
2022. "HW-Flow-Fusion: Inter-Layer Scheduling for Convolutional Neural Network Accelerators with Dataflow Architectures" Electronics 11, no. 18: 2933.
https://doi.org/10.3390/electronics11182933
APA Style
Valpreda, E., Morì, P., Fasfous, N., Vemparala, M. R., Frickenstein, A., Frickenstein, L., Stechele, W., Passerone, C., Masera, G., & Martina, M.
(2022). HW-Flow-Fusion: Inter-Layer Scheduling for Convolutional Neural Network Accelerators with Dataflow Architectures. Electronics, 11(18), 2933.
https://doi.org/10.3390/electronics11182933
