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Article
Peer-Review Record

VLSI Implementation of a Cost-Efficient Loeffler DCT Algorithm with Recursive CORDIC for DCT-Based Encoder

Electronics 2021, 10(7), 862; https://doi.org/10.3390/electronics10070862
by Rih-Lung Chung 1,*, Chen-Wei Chen 1, Chiung-An Chen 2,*, Patricia Angela R. Abu 3 and Shih-Lun Chen 1,*
Reviewer 1: Anonymous
Reviewer 2: Anonymous
Electronics 2021, 10(7), 862; https://doi.org/10.3390/electronics10070862
Submission received: 23 February 2021 / Revised: 22 March 2021 / Accepted: 27 March 2021 / Published: 5 April 2021
(This article belongs to the Special Issue New Techniques for Image and Video Coding)

Round 1

Reviewer 1 Report

  1. In the abstract section define VLSI.
  2. The manuscript is missing a discussion about Machine Learning-based algorithms.
  3. Please highlight what is the novelty proposed in this work. What are the new ideas proposed here?
  4. Please provide a motivation for still using the image compression algorithm presented in Section 2. The research has evolved quite a lot over the last years. Many other methods have improved beyond JEPG, while the Deep-Learning-based algorithms provide an outstanding performance compared to JPEG.
  5. Please provide a more detailed discussion regarding Figure 4.
  6. Improve the quality of Figure 6.
  7. Figures 7-10 should have a similar size and the font size should be almost the same.
  8. Section 4 must be improved. The manuscript is missing a discussion regarding the obtained results.
  9. These results are obtained at which rate/compression ratio?
  10. The experiments must sustain the drawn conclusions.

 

The manuscript is well written and easy to read. It’s not clear what is the novelty of this work and how the proposed method improves beyond the state-of-the-art. The experiments section must be improved.

Author Response

Please see the attachment

Author Response File: Author Response.pdf

Reviewer 2 Report

Review of article VLSI Implementation of a Cost-Efficient Loeffler-2 DCT Algorithm with Recursive CORDIC for DCT-Based Encoder

In this very well written article, the authors have designed an improved 2D DCT implementation using CORDIC to avoid dependency on hardware multipliers and thus permit programmability on microcontrollers and low-power FPGAs for IoT applications. The author’s overall aim was to develop a reduced-complexity hardware JPEG compressor for IoT devices, based on a recursive CORDIC architecture. The authors tested their DCT implementation in the JPEG image compression of well-known test images and compared the PSNR of their algorithm against that of Sun and the Loeffler-DCT method. The author’s implementation was shown to achieve comparable PSNR values, which demonstrate comparable reconstruction quality. However, the author’s implementation required significantly fewer (64.1% reduction) gates, placement area, and operated under (22.5%) less power. The author’s implementation uses a recursive approach, which was shown to be superior (in terms of logic complexity and without requiring additional memory) to an iterative approach. The author’s implemented a fully pipelined architecture which increased image compression throughput by reducing cycle time. Using CORDIC, only adders and shifters were required in their pipeline architecture, which reduces implementation cost. In Table 3 and 4, PSNR values of the author’s implementation were approximately as good as Loeffler’s, and were all > 25 dB, which is typically needed for wireless transmission quality, even though Loeffler’s implementation requires 22 multipliers. With hardware sharing, the authors can implement a 2D DCT with only 28 adders and 11 shifters, and hence require a significantly reduced gate count, power, and layout area.

Author Response

Thank you so much for your positive comments in this article, moreover, our team will keep working on this field of researches.

Round 2

Reviewer 1 Report

The authors answered my questions and improved the quality of the manuscript.

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