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Article

On the VCO/Frequency Divider Interface in Cryogenic CMOS PLL for Quantum Computing Applications

1
Department of Enzo Ferrari Engineering, University of Modena and Reggio Emilia, Via Vivarelli, 10, int. 1, 41125 Modena, Italy
2
CNR-IMM Unit of Agrate Brianza, Via Olivetti, 2, 20864 Agrate Brianza, Italy
*
Author to whom correspondence should be addressed.
Academic Editor: Esteban Tlelo-Cuautle
Electronics 2021, 10(19), 2404; https://doi.org/10.3390/electronics10192404
Received: 1 September 2021 / Revised: 27 September 2021 / Accepted: 28 September 2021 / Published: 1 October 2021
The availability of quantum microprocessors is mandatory, to efficiently run those quantum algorithms promising a radical leap forward in computation capability. Silicon-based nanostructured qubits appear today as a very interesting approach, because of their higher information density, longer coherence times, fast operation gates, and compatibility with the actual CMOS technology. In particular, thanks to their phase noise properties, the actual CMOS RFIC Phase-Locked Loops (PLL) and Phase-Locked Oscillators (PLO) are interesting circuits to synthesize control signals for spintronic qubits. In a quantum microprocessor, these circuits should operate close to the qubits, that is, at cryogenic temperatures. The lack of commercial cryogenic Design Kits (DK) may make the interface between the Voltage Controlled Oscillator (VCO) and the Frequency Divider (FD) a serious issue. Nevertheless, currently this issue has not been systematically addressed in the literature. The aim of the present paper is to investigate the VCO/FD interface when the temperature drops from room to cryogenic. To this purpose, physical models of electronics passive/active devices and equivalent circuits of VCO and the FD were developed at room and cryogenic temperatures. The modeling activity has led to design guidelines for the VCO/FD interface, useful in the absence of cryogenic DKs. View Full-Text
Keywords: CMOS; PLL; VCO; qubit; design; modeling CMOS; PLL; VCO; qubit; design; modeling
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MDPI and ACS Style

Gira, G.; Ferraro, E.; Borgarino, M. On the VCO/Frequency Divider Interface in Cryogenic CMOS PLL for Quantum Computing Applications. Electronics 2021, 10, 2404. https://doi.org/10.3390/electronics10192404

AMA Style

Gira G, Ferraro E, Borgarino M. On the VCO/Frequency Divider Interface in Cryogenic CMOS PLL for Quantum Computing Applications. Electronics. 2021; 10(19):2404. https://doi.org/10.3390/electronics10192404

Chicago/Turabian Style

Gira, Gabriele, Elena Ferraro, and Mattia Borgarino. 2021. "On the VCO/Frequency Divider Interface in Cryogenic CMOS PLL for Quantum Computing Applications" Electronics 10, no. 19: 2404. https://doi.org/10.3390/electronics10192404

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