# On the VCO/Frequency Divider Interface in Cryogenic CMOS PLL for Quantum Computing Applications

^{1}

^{2}

^{*}

## Abstract

**:**

## 1. Introduction

## 2. Qubit and Silicon Microelectronics

^{5}Mqubit/cm

^{2}, which is significantly larger than superconductors and trapped ions qubits, for which it lies in the 10

^{−4}–10

^{−5}Mqubit/cm

^{2}range. In addition, the chip area, i.e., the area covered by 2 billion physical qubits, goes from 10–10

^{2}mm

^{2}for semiconducting qubits to 10

^{7}–10

^{10}mm

^{2}for superconductors and trapped ions qubits [9].

## 3. PLL/PLO and Quantum Microprocessors

_{OPT}, at which the required level of the input signal is minimum, making easier the design of the VCO. The larger the offset from f

_{OPT}is, the higher the amplitude of the VCO signal should be. If the frequency offset is too large, the PLL/PLO cannot achieve the locking condition. In this case, the VCO runs free, and its frequency goes out of control. As in a quantum microprocessor, the integrated CMOS PLL/PLO is placed close to the qubits, and it should operate at cryogenic temperature. In reality, this involves a practical issue for the microelectronics designer: the lack of commercial Design Kits (DK) available at cryogenic temperatures [11]. Currently, the silicon foundries usually release DK in the −50 °C to +80 °C temperature range. The actual praxis is therefore designing the RFICs at room temperature by using a standard process and then cooling down the prototypes to cryogenic temperatures for its characterization [27,28]. As the cooling down from 300 K to a cryogenic temperature may induce a frequency mismatch between the VCO and the Frequency Divider, the RFICs are designed with generous tolerances and tuning capabilities, entailing a sub-optimized design. In the worst cases, these tolerances may not be enough to prevent the PLL to achieve the locking condition. In this frame, the investigation of the critical interface between the VCO and the Frequency Divider when the temperature changes from room to cryogenic is of large interest. Nevertheless, in spite of that, this issue has not been systematically investigated in the literature. The present paper intends to investigate the frequency mismatch between the VCO and the Frequency Divider that may arise when the temperature drops from room to cryogenic values.

## 4. Cryogenic Models

_{S}

^{T}. At room temperature is provide by the usual expression:

_{TH}is the thermal voltage, n

_{i}the intrinsic carrier concentration, and N

_{A}the substrate doping concentration. When the temperature goes down to cryogenic, φ

_{S}

^{T}changes by Δφ

_{F}in the case of an n-channel MOSFET [34]:

_{A}exp[(E

_{A}− E

_{i})kT], with ${\mathrm{g}}_{\mathrm{A}}$ ground-state degeneracy factor, E

_{A}the energy level of the acceptor impurity and E

_{i}the intrinsic Fermi energy level. The quantity α accounts for the dopant incomplete ionization; in the case of complete ionization α = 0 and thus Δφ

_{F}= 0. The values of PHI computed from these equations are reported in Table 1. Moving from the work of Beckers et al. [34], it is possible to demonstrate that the threshold voltage V

_{TN}of an n-channel MOSFET with n-type doped poly-silicon gate is given by:

_{C}is the effective state concentration in the conduction band, ε

_{Si}the silicon dielectric permittivity, and C′

_{ox}the gate capacitance per unit area.

^{18}cm

^{−3}, typical for deep sub-micron CMOS technologies, the previous equation gives V

_{TN}= 0.53 V at room temperature and V

_{TN}= 0.61 V at cryogenic temperature, in good agreement with the range of the extracted values for VTO. Because of the field ionization occurring under the Si/SiO

_{2}interface [34,35,36], the N

_{A}was kept equal to its room temperature value. The thickness oxide model parameter TOX was set equal to 1.7 nm.

_{BD}and C

_{BS}, it was set CBD = CBS = 0.45 fF/μm (CBD = CBS = 0.6 fF/μm) for an n-channel (p-channel) MOSFET at room temperature. For the overlap capacitances C

_{GSO}and C

_{GDO}, it was set CGSO = CGDO = 0.5 fF/μm. When the temperature decreases from room to cryogenic values, the drain-substrate and source-substrate parasitic capacitances C

_{BD}and C

_{BS}drop by a factor of ten, because these parasitic capacitances are associated to the space charge region of a reversed biased on junction [42]. In agreement, the cryogenic values of the model parameter CBD and CBS are ten times smaller than the corresponding room temperature values. On the other hand, the overlap gate-source and gate-drain capacitances C

_{GSO}and C

_{GDO}are temperature independent.

## 5. VCO and Frequency Divider

#### 5.1. Voltage Controlled Oscillator: Design and Modeling

_{1}and M

_{2}providing the energy required to maintain the oscillation. The inductors and the capacitors C are the resonator, which fix the oscillation frequency f

_{OSC}. The capacitor C is designed by using MOM capacitors or similar, because their capacitance does not change with the temperature [48]. This frequency is tunable, because of the varactors, implemented by using capacitor connected p-channel MOSFETs. The tuning voltage V

_{tune}is applied on the gate of these transistors. The resistors R

_{p}and R

_{s}in the inductor model account for the losses in the inductors, as previously described.

_{0}:

_{Diff}. In this model the two cross-coupled transistors M

_{1}and M

_{2}are equivalent to the differential negative resistance R

_{NEG}= −2/g

_{m1(2)}, where g

_{m1(2)}is the transconductance of the transistors M

_{1}and M

_{2}, whose parasitic capacitances are accounted for by the two capacitors C

_{p}. As shown in the figure, the inductors, but not the fixed capacitors and the varactors, participate to define Y

_{Diff}. When the fixed capacitors and the varactors are also accounted for, one gets the linearized model of the VCO. In this way, Y

_{Diff}can be exploited as the core of the oscillator, whose oscillation frequency can be later tuned by adding the fixed capacitors C and the varactors. The linear model on the right side in Figure 3 returns the following mathematical expression:

_{Diff}on the frequency:

_{Diff}exhibits a negative real part, that is:

_{Diff}injects into the resonator more energy than that dissipated by R

_{p}and R

_{s}. Of course, the higher the injected energy, the higher the oscillation of the differential output signal v

_{out}= v

^{+}

_{out}− v

^{−}

_{out}. In particular, for a given v

_{out}, the value of the bias current I

_{BIAS}can be estimated from the inductor model by describing the transistor during the oscillator operation as an ideal switch [49]:

_{Diff}can be described, due to the series of two inductors whose inductance L

_{eq}is expressed by the following mathematical expression:

_{0}of the VCO, with these two equivalent inductors. The values for C can be therefore estimated through the usual formula of the LC resonance frequency:

_{0}, at the frequency of interest f

_{0}. The circuit is therefore described as a two port network through the four scattering parameters S

_{11}, S

_{12}, S

_{21}, and S

_{22}. The differential reflection coefficient Γ

_{Diff}can be obtained from these parameters through the following formula:

_{Diff}can be obtained as:

_{0}= 15 GHz, Equation (1) gives R

_{p}= 1413 Ω and Rs = 3.53 Ω. By choosing a peak-to-peak differential output voltage of 1 V, I

_{BIAS}results to be about 560 μA from Equation (9). The start-up condition, see Equation (8), implies g

_{m1(2)}> 1.4 mS. By choosing g

_{m1(2)}= 3.2 mS, the transistor overdrive is about 0.18 V; the aspect ratio of the transistors M

_{1}and M

_{2}results to be about 3.6/0.04. In order to keep the gate length in the range of 1 μm, each transistor was obtained as the parallel of three transistors with an aspect ratio of 1.2/0.04. The supply voltage V

_{DD}was set equal to 1V, in order to keep the dissipated power low.

_{Diff}= −(880 + j6440) μS at 15 GHz. The simulated value of the real part of Y

_{Diff}is close to the value of −893 μS, provided by Equation (7). The small difference has to be ascribed to the channel modulation effect. The transistor output characteristics in Figure 2 show its presence but, for the sake of simplicity, it was not accounted for in the equivalent small-signal model in Figure 3. The simulated value of the imaginary part of Y

_{Diff}results are very close to the value of 6470 μS predicted by Equation (7), by putting the transistor parasitic capacitance C

_{p}= 12.5 fF. At 15 GHz, the imaginary part of Y

_{Diff}corresponds to L

_{eq}= 0.82 nH, from which Equation (11) gives C = 68.6 fF.

_{out}generated by the oscillator working at 300 K. The start-up phase, during which the small-signal approximation applies, last about 4 nsec. Afterward, the transistor non-linearities make the oscillator enter the steady state regime, where the oscillation frequency is 15 GHz and the peak-to-peak amplitude is close to 1V. In order to get the desired frequency, the value of C was tuned to 69 fF. This tuning is a consequence of the non-linearities excited in the steady state regime.

_{p}increased by three orders of magnitude, R

_{s}reduced by about 40%, and L decreased by about 5%. The transistors model was modified in agreement with Table 1. As the tail bias current I

_{BIAS}was kept constant, the cryogenic transconductance resulted to be about 3.9 mS and the transistor overdrive weakly decreased to 0.14V. The obtained waveforms are depicted on the right side of Figure 4. The duration of the start-up phase reduced to about 1 nsec and the steady state oscillation differential amplitude increased to about 3.2 V, in agreement with the reduction of the losses in the inductor. The cryogenic values of the inductor model parameters give indeed a quality factor of about three times higher than that at 300 K. A more ideal reactive response of the inductor allows therefore to get oscillation amplitudes higher than the supply voltage. It is worth noticing that Equation (9) predicts a differential output amplitude v

_{out}= 3.15 V when the increased value of R

_{p}and the decreased value of R

_{s}at cryogenic temperature are used.

_{Diff,OSC}, in order to also take into account the fixed capacitances C and the varactors capacitance C

_{VAR}as well:

_{OSC}, the inductor resonate out with the capacitor and imaginary part of Y

_{Diff,OSC}(jω) should be zero:

_{OSC}:

_{Diff}. The value of C was reduced by about 32 fF with respect to the value of 69 fF, in order to account for introduction of the varactors (2C + C

_{VAR}= 2 × 69 fF). The obtained curves show a fairly good agreement; a small difference has to be expected, because of the transistor non-linearities excited during the simulations in the time domain. In particular, the differences are more pronounced at cryogenic temperatures, because the oscillation amplitudes are larger. The application of the model shows that the vertical shift in the two characteristics is due to the 5% variation in the inductance induced by the temperature.

#### 5.2. Frequency Divider: Design and Modeling

_{DD}is 1V, in order to save bias headroom, the clock differential pair MC was biased by applying a voltage V

_{Bias}on their gate, as in [50,51], instead of using the traditional tail current solution, that requires to stack further transistors. The CML is coupled to the VCO with the coupling capacitor C

_{Bias}. The R

_{Bias}resistors avoid that the AC component of the clock coming from the VCO is drained to ground. R

_{Bias}and C

_{Bias}work therefore as a bias tee. The latch is constituted by two differential pairs. The driver differential pair M

_{D}works like a differential amplifier; it is activated when the clock is high. The latch is in the transparent phase, because it samples the input differential signals D and Dbar. When the clock goes down, the circuit enters the opaque phase. In this phase the latching differential pair M

_{L}is active, and it stores the signal previously sampled by the M

_{D}pairs. When only the DC component of the clock is applied, because of the negative feedback used for the register, the Frequency Divider behaves like a CML ring oscillator [50,52] exhibiting a self-oscillation frequency f

_{SO}. The condition for the self-oscillation is captured by the following equation [52]:

_{D}and W

_{L}are the channel width of the driving and latching transistors, respectively. During the self-oscillation the oscillation amplitudes are usually large enough to excite the non-linearities. The transconductances of the transistors in the circuit are therefore time variant. In Equation (17) g

_{m,L}is the DC value of the time variant transconductance of the M

_{L}transistors [52] and C

_{PAR}is the parasitic capacitance, highlighted in red in the schematic, at each drain terminal of the M

_{D}transistors. The previous Equation (17) for the self-oscillation implies:

_{L}transistors should generate a small-signal equivalent negative resistance able to compensate the losses due to the load resistors R

_{D}. It is also worth presenting the mathematical expression of f

_{SO}reported in [53] in the case of a Frequency Divider constituted by n latches, where n is even.

_{LSO}| and |I

_{DSO}| are the modules of the phasors, rotating at 2πf

_{SO}pulsation, of the currents flowing in the M

_{D}and M

_{L}transistors, respectively, under the self-oscillation condition. For n = 2, as in the present case, the previous equation reduces to the following one:

_{DSO}|/W

_{D}should be equal to |I

_{LSO}|/W

_{L}.

_{CLK}is 2f

_{SO}[50,54]. In the case of a frequency offset Δf between 2f

_{SO}and f

_{CLK,}the minimum clock amplitude V

_{CLK,min}, needed to keep the Frequency Divider correctly working, increases; the larger Δf, the higher V

_{CLK,min}. The plot of V

_{CLK,min}versus f

_{CLK}, called the Frequency Divider sensitivity curve, exhibits therefore a typical V-shape centered around 2f

_{SO}[54]. For excessively large Δf, the Frequency Divider enters the cut-off region. The V-shaped sensitivity curve can be reproduced through the following formula [50]:

_{inj}is an injection parameter describing how much the current injected by the clock signal is stronger than the DC current.

_{D}was kept equal to 1070 Ω, requiring a g

_{m,L}higher than 935 μS, corresponding to a minimum bias current of about 20 μA for the M

_{L}transistors. This condition was satisfied, both at 300 K and 4 K, by choosing W

_{D}and W

_{L}equal to 4800 nm, leading to a bias current of about 139 μA and 120 μA at 300 K and 4 K, respectively, for both the M

_{D}and M

_{L}transistors.

_{SO}is inversely proportional to the time constant RC

_{PAR}, (see Equations (19)–(21)), to investigate the f

_{SO}shift induced by the temperature change it is useful to get a rough estimation of this time constant. Following [53] the parasitic capacitance C

_{PAR}was estimated as sum of several contributes. Focusing on the $\overline{Q}$ node in Figure 8, one can write:

_{DB,D1}and C

_{GD,D1}are the drain-bulk and the overlap gate-drain capacitances, respectively, of the M

_{D1}transistor, C

_{GD,L1}and C

_{GS,L1}are the overlap gate-drain and gate-source capacitances of the M

_{L1}transistor, C

_{GD,L2}is the overlap gate-drain capacitance for the M

_{L2}transistor, C

_{OX,L1}is the gate oxide capacitance of the M

_{L1}transistor and C

_{LOAD}is the capacitive load provided by the $\overline{D}$ input node of the following register. In Equation (23), the C

_{GD,L1}and C

_{GD,L2}capacitances are multiplied by two, because they are excited by a differential signal. Since the input node is constituted by the gate of the M

_{D2}transistor of the following register, the C

_{LOAD}capacitance can also decomposed in several contributes:

_{GD,D2}and C

_{GS,D2}are the overlap gate-drain and gate-source capacitances of the M

_{D2}transistor and C

_{OX,D2}is the gate oxide capacitance of the M

_{D2}transistor. Because the M

_{D}and M

_{L}transistors have been sized at minimum length and with the same channel width, it is reasonable to consider all the overlap parasitic capacitances equal to a given value C

_{OV}, C

_{DB,D1}and C

_{DB,L2}equal to a given value C

_{DB}, and C

_{OX,L1}and C

_{OX,D2}equal to a given value C

_{OX,LD}. By replacing Equation (24) into Equation (23) one gets:

_{OV}can be considered constant during the self-oscillation and independent of temperature. On the other hand, the capacitance C

_{DB}depends on time, because it depends on the voltage present at the drain of the transistor, and it depends also on the temperature [42] while the capacitance C

_{OX,LD}depends only on the time. For a given temperature, Equation (25) contains therefore two time-dependent capacitive contributes, whose average values have to be estimated. The estimation was carried out by assuming that the transistors behave like a switch during the self-oscillation with a given duty cycle δ.

_{OX,LD,ON}can be estimated to be 2/3ε

_{OX}/t

_{OX}. The drain current I

_{D}flowing in the channel causes now a voltage drop on the load resistor R and therefore the C

_{DB}exhibits its high value, C

_{DB,ON}, because the reverse voltage across the drain-bulk junction is -V

_{DD}+I

_{D}R

_{D}. Finally, the resistance R

_{DS}of the channel can be estimated as V

_{DS}/I

_{D}. In this case, the resistance at the drain node R

_{ON}, with the transistor on, can be estimated as reported in [52]:

_{OX,LD,OFF}capacitance was assumed to be 10% of C

_{OX,LD,ON}, because it is constituted only by the substrate space charge region capacitance, being that the channel is absent. The drain voltage can be assumed equal to V

_{DD}, because there is no voltage drop on the load resistor, zero being the drain current of the transistor. Therefore, the C

_{DB}exhibits its low value, C

_{DB,OFF}, because the reverse voltage across the drain-bulk junction is -V

_{DD}. In addition, the resistance of the channel can be assumed infinite, because the drain current of the transistor is zero. The resistance at the drain node R

_{D,OFF}, with the transistor off, is therefore simply equal to R

_{D}.

_{OX,LD}capacitance can be therefore estimated as:

_{DB}capacitance as:

_{PAR}and R into Equation (19):

_{D}/W

_{L}was taken equal to one, because the M

_{D}and M

_{L}transistors are sized with the same channel width.

_{PAR}> = 23.5 fF at 300 K and <R> = 873 Ω, <C

_{PAR}> = 20.9 fF at 4 K, leading to 2f

_{SO}= 14.9 GHz at 300 K and 2f

_{SO}= 16.9 GHz at 4 K. The comparison with the values of 2f

_{SO}obtained from the simulation (see Figure 8) gives an error of about 10% at 300 K and of about 8% at 4 K. On the other hand, the 2f

_{SO}shift predicted by Equation (30) results to be the same as obtained from simulations. This agreement suggests that the increase of the self-oscillation frequency is mainly due to the drop of one order of magnitude of the drain-substrate and source-substrate parasitic capacitances C

_{BD}and C

_{BS}[42]. The average value of the resistance at the drain node changes very little.

_{inj}= 1450mV for the sensitivity curve at 300 K and K

_{inj}= 800mV for the curve at 4 K. In both the cases, it is possible to remark that the agreement is better for frequency higher than 2f

_{SO}. A similar asymmetrical agreement between the upper side and the lower side of the sensitivity curve was observed also for the more complex model proposed in [52]. It is worth noticing that the injection factor decreases by about 50% as a consequence of the temperature drop, leading to wider sensitivity curve, as it is possible to observe this in the figure. For a given frequency offset from 2f

_{SO}, the Frequency Divider needs a lower amplitude of the clock signal at cryogenic temperature. At cryogenic temperature, the Frequency Divider seems therefore working better.

## 6. Design Guidelines

## 7. Conclusions

## Author Contributions

## Funding

## Data Availability Statement

## Conflicts of Interest

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**Figure 1.**Typical building block diagram of a PLL (on the

**left**) and phase noise shaping under locked conditions (on the

**right**).

**Figure 2.**Output characteristics of the large-size NMOS (

**upper**) and the small-size PMOS (

**lower**) transistors. Dashed lines: from [32], solid lines from MOS3 model. Red curves: 300 K, blue curves: 4 K.

**Figure 3.**N-type cross-coupled oscillator: schematic (

**left**) and small-signal model of the differential admittance Y

_{Diff}(

**right**).

**Figure 8.**Self-oscillation differential output waveforms (on the

**left**) and sensitivity curves (on the

**right**) of the Frequency Divider.

NMOS Large Size | PMOS Large Size | NMOS Small Size | PMOS Small Size | ||||||
---|---|---|---|---|---|---|---|---|---|

Parameter | Unit | Temperature [K] | Temperature [K] | Temperature [K] | Temperature [K] | ||||

300 | 4 | 300 | 4 | 300 | 4 | 300 | 4 | ||

PHI | [V] | 0.9579 | 1.156 | 0.9579 | 1.156 | 0.9579 | 1.156 | 0.9579 | 1.156 |

VTO | [V] | 0.55 | 0.65 | −0.55 | −0.71 | 0.5 | 0.6 | −0.5 | −0.63 |

KP | [µA/V^{2}] | 200 | 300 | 81 | 131 | 200 | 300 | 81 | 131 |

ETA | [–] | 0.16 × 10^{−3} | 0.23 × 10^{−3} | 0.21 × 10^{−3} | 0.23 × 10^{−3} | ||||

THETA | [V^{−1}] | 1.923 | 1.64 | 1.45 | 0.98 | ||||

CBD | [F] | 5.4 × 10^{−16} | 5.4 × 10^{−17} | 6 × 10^{−16} | 6 × 10^{−17} | 5.4 × 10^{−17} | 5.4 × 10^{−18} | 6 × 10^{−17} | 6 × 10^{−18} |

CBS | [F] | 5.4 × 10^{−16} | 5.4 × 10^{−17} | 6 × 10^{−16} | 6 × 10^{−17} | 5.4 × 10^{−17} | 5.4 × 10^{−18} | 6 × 10^{−17} | 6 × 10^{−18} |

CGSO | [F/m] | 5 × 10^{−10} | 5 × 10^{−10} | 5 × 10^{−11} | 5 × 10^{−11} | ||||

CGDO | [F/m] | 5 × 10^{−10} | 5 × 10^{−10} | 5 × 10^{−11} | 5 × 10^{−11} | ||||

KF | [FV^{2}] | 3 × 10^{−24} | 5.5 × 10^{−24} | 5.5 × 10^{−23} | 3 × 10^{−24} | 5.5 × 10^{−24} | 5.5 × 10^{−23} |

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**MDPI and ACS Style**

Gira, G.; Ferraro, E.; Borgarino, M.
On the VCO/Frequency Divider Interface in Cryogenic CMOS PLL for Quantum Computing Applications. *Electronics* **2021**, *10*, 2404.
https://doi.org/10.3390/electronics10192404

**AMA Style**

Gira G, Ferraro E, Borgarino M.
On the VCO/Frequency Divider Interface in Cryogenic CMOS PLL for Quantum Computing Applications. *Electronics*. 2021; 10(19):2404.
https://doi.org/10.3390/electronics10192404

**Chicago/Turabian Style**

Gira, Gabriele, Elena Ferraro, and Mattia Borgarino.
2021. "On the VCO/Frequency Divider Interface in Cryogenic CMOS PLL for Quantum Computing Applications" *Electronics* 10, no. 19: 2404.
https://doi.org/10.3390/electronics10192404