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Article

A Methodology to Design Static NCL Libraries

by 1,2,3, 1,2 and 1,2,*
1
Department of Electronics Engineering, Faculty of Electricals and Electronics Engineering, Ho Chi Minh City University of Technology (HCMUT), 268 Ly Thuong Kiet Street, District 10, Ho Chi Minh City 700000, Vietnam
2
Vietnam National University Ho Chi Minh City, Linh Trung Ward, Thu Duc District, Ho Chi Minh City 700000, Vietnam
3
Department of Electronics Engineering, Faculty of Electricals and Electronics Engineering, Ho Chi Minh City University of Food Industry (HUFI), 140 Le Trong Tan Street, Tay Thanh Ward, Tan Phu District, Ho Chi Minh City 700000, Vietnam
*
Author to whom correspondence should be addressed.
Academic Editor: Andrea Acquaviva
J. Low Power Electron. Appl. 2022, 12(2), 31; https://doi.org/10.3390/jlpea12020031
Received: 20 December 2021 / Revised: 3 March 2022 / Accepted: 20 March 2022 / Published: 6 June 2022
The Null Convention Logic (NCL) based asynchronous design technique has interested researchers because this technique had overcome disadvantages of the synchronous technique, such as noise, glitches, clock skew and power. However, using the NCL-based asynchronous design method is difficult for university students and researchers because of the lack of standard NCL cell libraries. Therefore, in this paper, a novel flow is proposed to design NCL cell libraries. These libraries are used to synthesize NCL-based asynchronous designs. We chose the static NCL cell library to illustrate the proposed design solution because this library is one of the most basic NCL libraries. Static NCL cells in this library are designed based on the Process Design Kit 45nm technology and are implemented by the Virtuoso and the Design Compiler (DC) tool. In addition, the Ocean script and Electronic Design Automation (EDA) environment are used for supporting designs and simulations. A complete library of 27 NCL cells was designed to serve for study and research. We also implemented synthesis for NCL full adders using this library and compared our synthesis results with the results of other authors. The comparison results indicated that our results were a 20% improvement on power consumption. View Full-Text
Keywords: NCL cell library; threshold gate; asynchronous method; Null Convention Logic NCL cell library; threshold gate; asynchronous method; Null Convention Logic
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MDPI and ACS Style

Thanh, T.L.; Tri, L.T.; Hoang, T. A Methodology to Design Static NCL Libraries. J. Low Power Electron. Appl. 2022, 12, 31. https://doi.org/10.3390/jlpea12020031

AMA Style

Thanh TL, Tri LT, Hoang T. A Methodology to Design Static NCL Libraries. Journal of Low Power Electronics and Applications. 2022; 12(2):31. https://doi.org/10.3390/jlpea12020031

Chicago/Turabian Style

Thanh, Toi Le, Lac Truong Tri, and Trang Hoang. 2022. "A Methodology to Design Static NCL Libraries" Journal of Low Power Electronics and Applications 12, no. 2: 31. https://doi.org/10.3390/jlpea12020031

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