# CORDIC Hardware Acceleration Using DMA-Based ISA Extension

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## Abstract

**:**

## 1. Introduction

## 2. Background

#### 2.1. Nios-II Custom Instruction

#### 2.2. Altera Hardware CORDIC Unit

## 3. Related Work

## 4. Methodology

#### 4.1. ISA Extension Basic Implementation

#### 4.2. ISA Extension Using Pipelined Approach

#### 4.3. ISA Extension Using DMA Approach

## 5. Results

## 6. Summary and Conclusions

## Author Contributions

## Funding

## Data Availability Statement

## Acknowledgments

## Conflicts of Interest

## References

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**Figure 1.**Custom instruction architecture. Intel’s website [2].

**Figure 6.**Single neuron with multiple inputs followed by activation function [7].

Function | Mode | x_in | y_in | z_in | Result | Phase Type |
---|---|---|---|---|---|---|

A*cos(B) | 1 | A | 0 | B | x_out | Circular |

A*sin(B) | 1 | A | 0 | B | y_out | Circular |

asin(A) | 1 | Unit | 0 | A | z_out | Circular |

atan(B/A) | 0 | A | B | 0 | z_out | Circular |

Mag(A,B) | 0 | A | B | 0 | x_out | Linear |

C-B/A | 0 | A | B | C | z_out | Hyperbolic |

A*cosh(B) | 1 | A | 0 | B | x_out | Hyperbolic |

A*sinh(B) | 1 | 0 | A | B | x_out | Hyperbolic |

A*exp(B) | 1 | A | A | B | y_out | Hyperbolic |

atanh(B/A) | 0 | A | B | 0 | z_out | Hyperbolic |

0.5*ln(A) | 0 | A + 1 | A − 1 | 0 | z_out | Hyperbolic |

sqrt(A) | 0 | A + $\frac{1}{4}$ | A − $\frac{1}{4}$ | 0 | x_out | Hyperbolic |

Macro | C Equivalent Function |
---|---|

CORDIC_COS(phase) | cos(phase) |

CORDIC_SIN(phase) | sin(phase) |

CORDIC_AMPCOS(amp,phase) | amp*cos(phase) |

CORDIC_AMPSIN(amp,phase) | amp*sin(phase) |

CORDIC_ROTATEX(x,y,phase) | x*cos(phase) − y*sin(phase) |

CORDIC_ROTATEY(x,y,phase) | y*cos(phase) + x*sin(phase) |

CORDIC_SIGMOID(x) | sigmoid(x) |

Macro | Functionality |
---|---|

DMA_CORDIC_COS(z_in*,x_out*,size) | x_out = cos(z_in) |

DMA_CORDIC_SIN(z_in*,y_out*,size) | y_out = sin(z_in) |

DMA_CORDIC_AMPCOS (z_in*,x_in*,x_out*,size) | x_out = x_in*cos(z_in) |

DMA_CORDIC_AMPSIN (z_in*,x_in*,y_out*,size) | y_out = x_in*sin(z_in) |

DMA_CORDIC_ROTATEXY (z_in*,x_in*,y_in*,x_out*,y_out*,size) | x_out = x_in*cos(z_in) − y_in*sin(z_in) y_out = y_in*cos(z_in) + x_in*sin(z_in) |

DMA_CORDIC_NEURON (x_in*,y_in*,y_out*,size) | y_out = sigmoid(${\sum}_{i=1}^{n}{x\_in}_{i}\ast {y\_in}_{i}$) |

LUTs | Registers | Memory | DSP | Speed (MHz) | |
---|---|---|---|---|---|

Component | |||||

Nios-II/f Core | 1290 | 376 | 10,240 | 6 | - |

FPU Accelerator | 415 | 198 | 144 | 7 | - |

CORDIC | 1099 | 170 | 0 | 0 | - |

scaler | 126 | 148 | 0 | 0 | - |

float2fix | 261 | 257 | 0 | 0 | - |

fix2float | 192 | 238 | 0 | 0 | - |

Basic CIC | 634 | 1039 | 768 | 4 | - |

Pipelined CIC | 658 | 1071 | 1280 | 6 | - |

DMA CIC (+Avalon I/F) | 1790 | 2382 | 4096 | 6 | - |

System | |||||

Nios with FPU | 1819 | 717 | 10,453 | 13 | 114 |

Basic Implementation | 4933 | 2463 | 12,032 | 10 | 145 |

Pipelined Approach | 4955 | 2495 | 12,544 | 12 | 143 |

DMA Approach | 6089 | 3796 | 15,360 | 12 | 146 |

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**MDPI and ACS Style**

Manor, E.; Ben-David, A.; Greenberg, S. CORDIC Hardware Acceleration Using DMA-Based ISA Extension. *J. Low Power Electron. Appl.* **2022**, *12*, 4.
https://doi.org/10.3390/jlpea12010004

**AMA Style**

Manor E, Ben-David A, Greenberg S. CORDIC Hardware Acceleration Using DMA-Based ISA Extension. *Journal of Low Power Electronics and Applications*. 2022; 12(1):4.
https://doi.org/10.3390/jlpea12010004

**Chicago/Turabian Style**

Manor, Erez, Avrech Ben-David, and Shlomo Greenberg. 2022. "CORDIC Hardware Acceleration Using DMA-Based ISA Extension" *Journal of Low Power Electronics and Applications* 12, no. 1: 4.
https://doi.org/10.3390/jlpea12010004