Reduction of Bias and Light Instability of Mixed Oxide Thin-Film Transistors

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Active-matrix displays and sensors.

Abstract

Despite their potential use as pixel-switching elements in displays, the bias and light instability of mixed oxide semiconductor thin-film transistors (TFTs) still limit their application to commercial products. Lack of reproducible results due to the sensitivity of the mixed oxides to air exposure and chemical contamination during or after fabrication hinders any progress towards the achievement of stable performance. Consequently, one finds in literature several theories and mechanisms, all justified, but most of them conflict despite being on the same subject matter. In this study, we show that under an optimized fabrication process, which involves the in situ passivation of a mixed oxide semiconductor, we can reduce the bias and light instability of the mixed-oxide semiconductor TFTs by decreasing the semiconductor thickness. We achieve a negligible threshold voltage shift under negative bias combined with light illumination stress when the mixed oxide semiconductor thickness is around three nanometers. The improvement of stability in the thin mixed-oxide semiconductor TFTs is due to a reduced number of oxygen-vacancy defects in the bulk of the semiconductor, as their total number decreases with decreasing thickness. Under the optimized fabrication process, bulk, rather than interfacial defects, thus seem to be the main source of the bias and light instability in mixed oxide TFTs.

1. Introduction

The interest in mixed oxide semiconductor-based thin-film transistors (TFTs) for applications in active-matrix displays (AMDs) has generated a large body of experimental and theoretical studies devoted to mixed oxide semiconductors, particularly amorphous indium-gallium zinc-oxide (a-IGZO) [1,2]. For applications in AMDs, reliability and stability of the TFTs used as pixel-switching elements are of primary concern [3]. Stability against negative-gate bias stress combined with visible light illumination (NBIS) is of particular importance, given that TFTs in a display pixel operate in an illuminated environment. Although many investigations have focused on the effects of NBIS, which include persistent negative threshold-voltage (V_TH) shift [4,5,6,7], they have not yet found ways to suppress them completely. Since the TFTs′ V_TH stability has a strong bearing on display uniformity, lifetime, and pixel architecture [3], some groups have proposed subjecting mixed oxide TFTs to post-deposition annealing at high temperatures under wet [8], oxygenated [9], ozonated [10], or nitrogenated environments as a way of minimizing the effects of NBIS. Other groups have proposed the use of light shields, nitrogen cap layers [11], high-quality dielectrics (both as gate insulators [12], and passivation [13] layers), but such methods suppress the NBIS-induced instability only to limited extents.

Recently, bulk accumulation, which is achieved by the use of a dual-gate structure in which the top gate and bottom gate are electrically shorted together, has been shown to reduce the NBIS instability of mixed oxide TFTs with thin semiconductor layers (<25 nm) [14,15]. However, similar to other stability improvement methods, bulk accumulation also suppresses the NBIS instability only to a limited extent. In addition, several reports have indicated the importance of the semiconductor thickness in the stability of the mixed oxide TFTs but different groups reached different conclusions [8,16,17,18]. For instance, for some groups, the bias stability of the TFTs became better as semiconductor thickness increased [16,17], whereas, for other groups, it worsened [18]. Nomura et al. also showed opposite trends for wet-annealed and non-annealed TFTs [8]. For wet-annealed TFTs, the V_TH shift (∆V_TH) decreased with increasing semiconductor thickness, and for non-annealed TFTs, ∆V_TH increased with increasing semiconductor thickness. Nomura et al., therefore, concluded that the density of trap states increased with increasing semiconductor thickness in the non-annealed TFTs, whereas in the wet-annealed TFTs, there was almost no bulk effect.

In this study, we investigate the effect of semiconductor thickness on the stability of mixed oxide semiconductor TFTs against NBIS. In contrast to previous reports [8,16,17,18,19,20], we fabricate the TFTs using an optimized fabrication process, which involves the in situ passivation of the mixed oxide semiconductor, and we investigate very thin (3–10 nm) and thick (20–100 nm) semiconductor layers. For the mixed oxide, we use the a-IGZO semiconductor, given that a-IGZO TFTs can be built with the simple and cost-effective inverted staggered structure, and exhibit high field-effect mobility (µ_FE) and low V_TH [1,2].

2. Materials and Methods

Figure 1 illustrates the fabrication process of the a-IGZO TFTs investigated in this study. The process begins with the deposition of a 60-nm thick Mo layer on glass by sputtering and its patterning by standard lithography to form the gate electrode (Figure 1a). This is followed by the consecutive deposition of a 250 nm-thick SiO₂ layer by plasma-enhanced chemical vapor deposition (PECVD) as the gate insulator at 380 °C, deposition of an a-IGZO layer by sputtering at 200 °C, and deposition of a 100 nm-thick SiO₂ back passivation layer by PECVD at 200 °C in a cluster deposition tool, without breaking vacuum (Figure 1b). This step ensures the in situ passivation of the a-IGZO, immediately after deposition, to realize an uncontaminated and very stable a-IGZO layer that is necessary for the detection of intrinsic characteristics, rather than fabrication process-related variations. Samples with a-IGZO thickness (t_IGZO) of ~3, 5, 10, 20, 50, and 100 nm are fabricated. The sputtering of the a-IGZO is performed using a polycrystalline IGZO target (In₂O₃:Ga₂O₃:ZnO = 1:1:1 mol %) at 200 °C. The Ar:O₂ gas ratio is set at 4:8 for sputtering.

The top SiO₂ layer, which is a protective layer, commonly referred to as the “etch stopper”, is patterned to expose the source and drain regions for the metal contacts (Figure 1c). During the fabrication process, the etch stopper protects the a-IGZO from exposure to air and also shields it from being etched away or contaminated by the etchant used to define the source/drain electrodes. The patterning of the a-IGZO layer to form active islands (Figure 1d) follows the etch-stopper process. Deposition of another Mo layer and its patterning to form the source/drain electrode contacts and a 200 nm-thick SiO₂ layer as the final TFT passivation layer (Figure 1e) follows the a-GZO process. The final step is the annealing of the TFTs at 250 °C in vacuum to ensure a reproducible unstressed state.

We confirmed TFT layer thicknesses by means of transmission electron microscopy (TEM) imaging as shown in Figure 2 and determined the crystallinity and chemical composition of the IGZO layers by X-ray diffraction (XRD) patterns and X-ray photon electron spectroscopy (XPS), respectively. In XRD (Figure 3a), the IGZO films do not exhibit sharp diffraction peaks assignable to a crystalline phase but have two halo peaks at 32° and 56°, indicating that they are amorphous. The a-IGZO film is transparent in the visible range (Figure 3b), owing to its large band gap = ~3.2 eV (Figure 3c). XPS results show that the a-IGZO chemical composition is In:Ga:Zn = 3:2:1 in an atomic ratio (Figure 3d).

We measured the current-voltage (I-V) characteristics using the Agilent 4156C precision semiconductor parameter analyzer, and the capacitance-voltage (C-V) characteristics using the Agilent E4980A Precision LCR meter by superimposing the gate DC voltage (V_GS) on a small AC signal (0.1 V) of frequency (f) at 1 kHz, keeping the source and drain shorted. Note that the f of the AC signal should be low enough to guarantee quasi-static conditions, 1/f ≫ RC time constant of the system, so that the induced AC variation of surface potential Ψ_S can be considered constant along the channel [21]. Consistent with previous reports, we accomplished the NBIS by holding the TFT V_GS at −20 V for 10,000 s, while biasing the source and drain electrodes at zero volts, under white-light illumination (9000 nit) and at room temperature [8,16,17,18]. TFT parameters were derived from the conventional metal-oxide, semiconductor field-effect transistor (MOSFET) equation. The µ_FE was derived from the transconductance (g_M) with V_DS = 0.1 V at a gate voltage (V_GS) of 10 V. The V_ON was taken as the V_GS at which the drain current (I_DS) started to monotonically increase. The subthreshold voltage swing (SS) was taken as the minimum value of (d log(I_DS)/d V_GS)⁻¹. We extracted the density of states (DOS) of the a-IGZO as a function of thickness before and after NBIS using a method, which involves a combined analysis of the TFTs’ I-V and C-V characteristics [21].

3. Results

TFT current-voltage (I-V) characteristics exhibit a clear dependency on t_IGZO (Figure 4a). Previous reports also show similar effects of t_IGZO on TFT parameters [17,18,19,20]. The drop in the on-state currents and positive shift of V_ON with decreasing t_IGZO are consistent with a decrease in carrier concentration [18] or an increase in deep electron traps at the a-IGZO film surface as the t_IGZO becomes very small, as previously reported [18,20]. However, it could also be as a result of 20 nm being the thickness in which gate modulation is effective, given that it becomes significant for t_IGZO < 20 nm. Similarly, the C-V characteristics shift to the negative V_GS direction with increasing t_IGZO (Figure 4b).

Table 1. Key thin-film transistor parameters.

tIGZO (nm)	VON (V)		µFE (cm2/V·s)		SS (mV/dec)
	Before NBIS	After NBIS	Before NBIS	After NBIS	Before NBIS	After NBIS
3	0.0	−1.6	1.60	1.68	100	196
5	−1.2	−6.0	17.05	17.43	127	136
20	−2.8	−10.0	18.49	18.88	152	171
50	−4.4	−13.2	19.15	19.47	276	375
100	−4.8	−18.0	20.02	20.19	426	439

NBIS is short for negative-gate bias stress combined with visible light illumination. t_IGZO, V_ON, µ_FE, and SS, are the amorphous indium-gallium zinc-oxide thickness, turn-on voltage, field-effect mobility and subthreshold voltage swing.

lists the TFT parameters as a function of t_IGZO.

For all the t_IGZO investigated, the a-IGZO semiconductor should be fully depleted, given that the off-state leakage currents do not significantly change with increasing t_IGZO [22]. The negative shift of V_ON with increasing t_IGZO is interesting, particularly because hydrogenated amorphous silicon (a-Si:H) TFTs do not exhibit such a dependency on semiconductor thickness [22,23]. It is also interesting to note that SS increases with increasing t_IGZO, consistent with the stretching out of the C-V characteristics of TFTs with thick a-IGZO layers (Figure 4).

The negative ∆V_ON induced by NBIS decreases with decreasing t_IGZO (Figure 5a–e). Table 1 also shows TFT parameters extracted after the application of NBIS and Figure 5e shows the time dependency of the ∆V_ON for the TFTs. Note that when t_IGZO = ~3 nm, the ∆V_ON is negligible.

4. Discussion

4.1. V_TH Dependency on Channel Thickness

Kim et al. noted that the last term in the TFT V_TH expression:

$$\begin{array}{cc}{V}_{\mathrm{TH}}=\left({\Phi }_{\mathrm{M}}-{\Phi }_{\mathrm{S}}\right)& +\frac{q\times N_{\mathrm{bulk}}\times {\left(E_{\mathrm{F}}-E_i\right)}_{\mathrm{threshold}}}{C_{\mathrm{OX}}}-\frac{Q_f}{C_{\mathrm{OX}}}+\frac{q\times N_{\mathrm{int}}\times {\left(E_{\mathrm{F}}-E_i\right)}_{\mathrm{threshold}}}{C_{\mathrm{OX}}}-\frac{Q_m}{C_{\mathrm{OX}}}\\ & -\frac{q\times \left(D_{\mathrm{D}}-D_{\mathrm{A}}\right)}{C_{\mathrm{OX}}}\hfill \end{array}$$

(1)

suggests that carrier concentration in the channel layer influences the V_TH [24]. In the V_TH expression, C_OX is the gate-insulator capacitance per unit area, Q_f is the oxide charge density, N_bulk and N_int are the shallow bulk trap density and the interface trap density, respectively, and Φ_M and Φ_S are, respectively, the metal and semiconductor work functions. D_D and D_A are respectively the donor and acceptor concentrations per unit area. In an n-type oxide semiconductor such as a-IGZO, D_A is negligible and the product of the donor concentration per unit volume (N_D) and the semiconductor thickness obtain D_D. For a-IGZO TFTs with varying t_IGZO, V_TH thus varies with q × N_D × t_IGZO/C_OX, given that all other terms in the V_TH expression are independent of the semiconductor thickness. For a 250 nm-thick SiO₂ gate-insulator, Figure 6 shows how V_TH varies with t_IGZO for N_D ranging from 10¹⁵–10¹⁷ cm⁻³. As the carrier concertation of the a-IGZO TFTs studied herein lies between 10¹⁶ and 10¹⁷ cm⁻³, simulated results in Figure 6 are consistent with the experimental results in Figure 4a. Kim et al. argued that this phenomenon is generally disregarded in a-Si:H TFTs, given that their carrier concentration is 2–3 orders of magnitude lower than that of the oxide TFTs, making the V_TH sensitivity on the channel thickness of a-Si TFTs negligible [24]. This is confirmed in Figure 6, where V_TH becomes insensitive to semiconductor thickness when N_D ≤ 10¹⁵ cm⁻³.

4.2. SS Dependency on Channel Thickness

Total shallow trap densities (N_T) can be estimated from SS values using the relation SS = log_e10 × k_BT/q × (1 + q(N_int + t_IGZO × N_bulk)/C_OX), where q is the elementary electric charge, k_B the Boltzmann constant, and T the temperature. N_int is the area density of the shallow traps close to the Fermi level (E_F) at the gate-insulator/semiconductor interface and N_bulk is the volume density of shallow traps in the bulk of the a-IGZO semiconductor. The sum N_int + (t_IGZO × N_bulk) gives the N_T. By linear regression of N_T = N_int + t_IGZO × N_bulk, N_int and N_bulk were estimated to be 1.25 × 10¹¹ cm^-2 eV⁻¹ and 1.07 × 10¹⁷ cm⁻³eV⁻¹, respectively (Figure 7).

4.3. Effect of Channel Thickness on NBIS Stability

The NBIS instability originates from the presence of gap states near the E_V, which play the role of absorption sites for visible light. Thermal desorption spectra (TDS) obtained by Ide et al. indicated that these defects may include trap states, which originate from the incorporation of the weakly bonded oxygen commonly known as oxygen vacancies [10,22,23]. Upon illumination, a neutral oxygen vacancy (V_O) releases one or two electrons to the conduction band (E_C), forming its ionized states, V_O⁺ or V_O²⁺, which are located in the vicinity of the mobility edge (Figure 8a). The negative V_GS applied during NBIS pushes the Fermi level (E_F) toward the E_V, decreasing the ionized vacancies’ formation enthalpy, ΔH, which is given by the term −q(E_F − E_V), q being the defect charge state [25]. Creation of additional defects is also possible due to the decrease in ΔH. Note that in an oxygen-deficient material, the shift of E_F toward E_V may result in a negative ΔH and spontaneous defect formation [25]. The energy distribution of the defects formed after application of NBIS should be very close to E_F because the SS increases after application of NBIS (Figure 5). Existing and created ionized oxygen vacancies can also drift toward the gate insulator interface, contributing to a buildup of a positive charge at the gate-insulator/active-layer interface. Note that trapped/accumulated positive charge may provide a positive bias effect on the n-type a-IGZO channel, consistent with the negative ΔV_ON after NBIS.

When the neutral V_O states lose electrons to form the ionized V_O⁺ and V_O²⁺, they undergo outward structural relaxation, suggesting higher energy for V_O⁺ and V_O²⁺ compared to the neutral state (V_O). Therefore, shallow states increase, while the deep states decrease, as illustrated in Figure 8b–e. The magnitude of the NBIS-induced negative ΔV_TH thus depends on the total number of ionized donors, because events occurring at the semiconductor/gate-insulator interface govern TFT operation. Figure 9 shows the DOS extracted from the combined analysis of I-V and C-V characteristics before and after application of NBIS. After NBIS, the DOS shows the formation of a broad peak between E–E_C of 0.2 eV and 1.0 eV, which increases in height and width with increasing t_IGZO. This peak is consistent with the increase in ionized donors, and as their total number increases with increasing t_IGZO, TFTs with the thin a-IGZO layers are, therefore, more stable against NBIS than the TFTs with thicker a-IGZO layers. This dependency of the NBIS stability on t_IGZO, thus, indicates that bulk, rather than interfacial defects, are the main source of the NBIS instability in mixed oxide TFTs.

These results are also consistent with previous reports. For instance, a recent publication by Flewitt et al. revealed a weak localization of carriers in a-IGZO that is over 20 nm [26]. This means that if the number of sites that electrons can migrate to is constrained in the vertical direction, the creation of charged donors should be less likely in TFTs with thinner active layers compared to those with thicker active layers. Li et al. also showed that electron concentration decreases with film thickness in a-IGZO thin films, such that films with t_IGZO < ~20 nm exhibited a bandgap expansion with decreasing t_IGZO [27]. Li et al. attributed this to a quantum confinement effect in very thin a-IGZO TFTs. Thicker films (t_IGZO > ~35 nm) demonstrated the free-electron effect (i.e., the Burstein-Moss shift) and an increase of free-electron absorption with increasing t_IGZO (i.e., increasing electron concentration) [27]. For thin layers, the quantum confinement effect is consistent with the large band offsets that the a-IGZO forms with the SiO₂ gate insulator and etch stopper (Figure 10).

4.4. Verification of the Effect of Oxygen Vacancies on NBIS Stability

To confirm that oxygen vacancies are indeed the cause of the NBIS instability, we investigated the NBIS stability of TFTs with a-IGZO layers that are 20 nm thick but deposited at different oxygen partial pressures (Figure 11). It is interesting to find that NBIS stability increases with an increase the oxygen partial pressure. This confirms that oxygen vacancies are indeed the cause of the NBIS instability in mixed oxide TFTs, given that the concentration of oxygen vacancies and, hence, carrier concentration decreases with the increasing oxygen partial pressure [1,28].

Figure 12 presents an additional piece of evidence confirming the role of oxygen vacancies in the NBIS instability of mixed oxide TFTs. Before application of NBIS (Figure 12a), V_TH shifted to the negative V_GS direction with increasing photon energy, indicating the increase in carrier concentration due to the ionization of V_O to V_O⁺ and/or V_O²⁺ [29,30,31].

Given that the band gap (E_g) of a-IGZO is ~3.1 eV, these results clearly indicate sub-gap photoexcitation, consistent with the ionization of V_O to V_O⁺ and/or V_O²⁺. However, after application of NBIS, light with a wavelength less than E_g of a-IGZO results in negligible change in the performance of the a-IGZO TFTs (Figure 12b). These results show that NBIS does indeed result in the ionization of V_O to V_O⁺ and/or V_O²⁺, such that further ionization by light illumination results in no significant sub-gap photoexcitation after NBIS. Only light with a wavelength greater than E_g causes a significant change due to band-to-band excitation. The stretching-out of the subthreshold characteristics of the TFT after NBIS is consistent with back channel conduction that randomly occurs after application of NBIS.

4.5. Fabrication Process Optimization

The variations in performance and theories from research group to research group are closely related to the sensitivity of mixed oxide semiconductors to air or chemicals. Exposure to air should be avoided, not only after device fabrication (Figure 1f), but also, more importantly, during the fabrication process itself (Figure 1b). If a device is fabricated with neither an etch stopper nor a passivation layer, the device stability will improve with increasing a-IGZO thickness. Thick a-IGZO layers will have a self-passivation effect by the intrinsic a-IGZO, even though the surface region is affected by moisture or oxygen from ambient air; that is, the thicker the a-IGZO layer, the farther away the front channel accumulation layer (bottom surface of the semiconductor layer) is from the desorption and adsorption properties occurring at the top surface. More importantly, if the vacuum is broken between the deposition of the a-IGZO and the etch stopper, in cases where the two processes have to be performed in two different chambers, significant contamination to the a-IGZO layer will occur during the transfer from the a-IGZO deposition chamber to the etch-stopper deposition chamber. This is very important, but often overlooked. In the case of the devices presented herein, a cluster deposition tool that allows consecutive deposition of the gate insulator, active layer, and etch stopper without breaking vacuum is used, thereby passivating the a-IGZO layer throughout the whole fabrication process. Therefore, we emphasize that due to fabrication process optimization, intrinsic, rather than process-related instability mechanisms, were detectable in this study.

Device structure and the type of dielectrics used can also be a source of the differences in the trends observed with varying semiconductor thickness. For instance, the stability of inverted, staggered devices without a passivation layer is more likely to improve with increasing semiconductor thickness because the thicker the semiconductor, the further away the front channel (bottom surface of the semiconductor layer) is from the absorption/desorption processes occurring at the top surface [8]. In this report, the root cause of these conflicting theories is not only attributed to the possibility of varying the types and/or ratios of the components making up a mixed oxide semiconductor, but it is mainly attributed to fabrication process variations, given the sensitivity of mixed oxide semiconductors to wet etchants, gasses, or air exposure. Therefore, we show here that under an optimized fabrication process, which involves the passivation of the mixed oxide semiconductor in situ, employing very thin mixed oxide semiconductors completely suppresses the NBIS-induced instability. It is, thus, reasonable to conclude that under the optimized fabrication process presented herein, bulk, rather than interfacial defects, are the main source of bias and light instability in mixed oxide TFTs.

It is important to note that the self-passivation effect of thick semiconductor layers is not useful in real applications, such as display panels, where TFTs are passivated/encapsulated by materials with very low water-vapor-transmission-rates. As good NBIS stability is of utmost importance, TFTs with thin semiconductor layers are thus more desirable. However, in TFTs with thin active layers, there is an NBIS stability versus on-state current trade-off. This can be minimized by the employment of large channel widths, if the intended application allows. Although a-IGZO TFTs are used as test devices, the conclusions made herein can also be extended to other varieties of mixed oxides or other forms of instabilities—particularly to explain the non-reproducible nature of the performance of these mixed oxide TFTs, and why, from one group to another, there is so much variation in results and theories.