A Genetic Algorithm-Based Optimization Method for Ordered Escape Routing in BGA PCBs Under Non-Crossing and Single-Capacity Constraints

Featured Application

The proposed optimization method is primarily applied to the physical design automation of high-density printed circuit boards (PCBs), specifically targeting the escape routing of Ball Grid Array (BGA) packages. Key applications include the following: automated high-speed bus routing; generating feasible escape paths for memory and data buses (e.g., DDR interfaces) where maintaining specific pin ordering is strictly required to prevent net crossings and signal interference during the subsequent area routing phase; PCB fabrication cost reduction; maximizing the utilization of routing resources on a single layer through non-crossing and single-capacity constraints, thereby minimizing the necessity for additional routing layers and blind/buried vias; and algorithmic engines for EDA tools, serving as a core optimization engine within electronic design automation (EDA) software to replace error-prone manual routing processes for complex BGA components.

Abstract

The increasing functional complexity and high-density integration of integrated circuits (ICs) present formidable routing challenges for printed circuit boards. Specifically for components utilizing high-density Ball Grid Array and other Grid Pin Array (GPA) packages, achieving efficient and reliable ordered escape routing is critical. This routing must strictly satisfy non-crossing and channel capacity constraints, which often become the bottleneck determining design success. Traditional manual or heuristic methods are increasingly inadequate for meeting the complexity and optimization demands of modern high-density designs. To address this challenge, this study proposes an innovative, automated routing strategy that leverages the robust search and optimization capabilities of the genetic algorithm (GA). We formulate the ordered escape routing problem on BGA/GPA as a rigorous combinatorial optimization problem. Through the GA mechanism, the core research objective is to explore the vast solution space and achieve the minimization of the total routing cost. This research establishes an automated routing framework capable of providing cost-effective escape routing solutions for high-density BGA, while strictly satisfying the non-crossing and single-capacity constraints. The proposed methodology not only significantly enhances routing efficiency and success rates but also provides essential technical support for the design and manufacturing processes of complex electronic products. For instance, in the simulation case of Case 7 (a 25 × 26 array with 60 active pins), this method achieved a routing compression ratio of 0.8230, equivalent to a 17.70% reduction in the total routing length, fully demonstrating the superior performance of the proposed algorithm in optimizing the routing cost.

1. Introduction

With the rapid advancement of modern integrated circuit (IC) technology, the functional complexity and integration density of electronic systems have increased dramatically [1]. This miniaturization trend presents formidable challenges for the physical design of printed circuit boards, particularly regarding the routing of high-density components such as Ball Grid Arrays [2,3]. As the number of input/output (I/O) pins increases while the package pitch shrinks, “escape routing”—the process of routing signals from the inner pins of a component to its boundary—has become one of the most critical and time-consuming bottlenecks in the PCB design flow [3,4].

Escape routing is generally categorized into two types: unordered escape routing (uer) and ordered escape routing (OER) [3]. While UER allows pins to escape to the boundary in any order, it often results in significant difficulties during the subsequent “area routing” phase, where connections between components must be established. Inconsistent pin ordering can lead to excessive wire crossings and blockages, rendering the board unroutable [3,5]. Consequently, OER, which imposes a specific ordering constraint on the escaping nets to facilitate high-speed bus connections and minimize layer usage, has garnered significant research attention [2]. Furthermore, modern high-density designs strictly require that routing paths satisfy non-crossing (planarity) constraints and single-capacity constraints (where only one wire can pass between adjacent pins) to ensure manufacturability and signal integrity [2,6].

In practical PCB systems, signal nets are often grouped together as buses to transfer parallel data among chips and functional modules. To facilitate timing optimization and signal synchronization, all bit nets within a bus are required to share the same routing topology and maintain similar wire lengths. These requirements are commonly referred to as the topology constraint and the length-matching issue [7,8]. Satisfying these constraints simultaneously significantly increases the design complexity of bus routing and demands more sophisticated automated routing techniques. Moreover, in advanced PCB technologies, routing resources are typically provided in the form of predefined routing tracks. However, uniform track configurations are frequently insufficient to accommodate different wire widths and complex layout styles. Modern designs increasingly adopt nonuniform and irregular track resources, which further complicate the routing task [7,9,10]. The existence of obstacles and heterogeneous routing environments makes it even more challenging to obtain feasible solutions that satisfy both topology and length-matching requirements.

Over the past decades, numerous studies have investigated PCB bus routing from different perspectives. Early works addressed fundamental topological routing problems for multi-bit buses [11,12]. Subsequent research focused on obstacle-aware routing and length-matching techniques to improve timing consistency [8]. To cope with the growing complexity of dense PCBs, Kong et al. proposed an automatic bus planner that integrates global routing, layer assignment, and iterative improvement [13]. Additional studies investigated the optimal algorithms for finding disjoint routing regions and optimal bus sequencing for escape routing in high-density environments [14,15]. More recently, ILP-based frameworks have been developed to jointly consider bus decomposition, escape routing, and global routing [16]. Furthermore, topology generation and route synthesis approaches have been explored for performance-critical signal groups [17]. Despite these advances, many existing methods either assume uniform routing resources or do not explicitly address the length-matching problem under nonuniform track configurations.

To tackle the challenges introduced by nonuniform routing resources, Cheng et al. proposed an obstacle-avoiding length-matching bus routing methodology that explicitly considers nonuniform track configurations [7]. Chen et al. introduced a concurrent and hierarchical maze routing scheme (MARCH) for bus routing to improve routing flexibility and efficiency [9], while Hsu et al. developed a directed acyclic graph (DAG)-based algorithm for topology-matching bus routing under on-track constraints [10]. Although these approaches achieved significant improvements over earlier methods, they either did not fully address the ordered escape routing problem or lacked mechanisms to guarantee strict length matching and single-capacity constraints simultaneously. Therefore, there remains a strong demand for routing methodologies capable of handling ordering constraints, non-crossing requirements, nonuniform track resources, and length matching in a unified and scalable manner [18,19].

The current state of research relies heavily on mathematical modeling to solve these routing problems. Network flow models have been pervasively used to find optimal escape paths by transforming the routing grid into a flow graph [2,20]. While effective for specific capacities, these models often struggle to incorporate complex design rules like specific net orderings without significant modifications. Alternatively, integer linear programming (ILP) and Boolean satisfiability (SAT) approaches have been proposed to handle OER by formulating the problem as a set of rigorous constraints [2,5,21]. Although these exact methods guarantee optimal solutions when they converge, they are computationally expensive and often suffer from scalability issues when applied to large-scale BGA components with hundreds or thousands of pins [22].

Conversely, heuristic and meta-heuristic algorithms offer a compelling alternative for solving such NP-hard combinatorial optimization problems. Techniques such as genetic algorithms and Particle Swarm Optimization (PSO) have demonstrated robust global search capabilities in VLSI and PCB routing tasks [23,24]. These evolutionary approaches mimic natural selection to explore vast solution spaces and are particularly effective at escaping local optima, a common pitfall for traditional greedy or deterministic heuristics [23,25]. However, directly applying conventional evolutionary algorithms to the OER problem is fundamentally ineffective. Standard GA-based routing techniques typically encode paths as node or edge sequences and rely on generic crossover and mutation operators. In the OER setting, three constraints—strict pin ordering, non-crossing between nets, and single-capacity usage of routing channels—must be satisfied simultaneously. Under these conditions, arbitrary genetic operations almost always generate infeasible offspring, and simple penalty-based strategies cannot reliably restore legality. Moreover, conventional GA frameworks lack mechanisms to explicitly verify or repair routing conflicts. Therefore, solving OER requires a problem-specific evolutionary framework with dedicated encoding, feasibility enforcement, and repair strategies rather than a direct application of a generic GA.

To address these challenges, this study proposes a novel genetic algorithm-based optimization framework specifically tailored for ordered escape routing under strict non-crossing and single-capacity constraints. Unlike existing deterministic or partition-based methods, the proposed approach integrates domain-specific knowledge directly into the design of the GA, enabling global optimization while ensuring routing feasibility at all times. Rather than being a straightforward application of a conventional GA, the proposed method introduces several new algorithmic components that are essential for solving the highly constrained OER problem.

Specifically, the proposed framework differs from existing approaches in three key aspects. First, the chromosome representation is designed around an ordered grid transformation model, which maintains the routing order and structural connectivity—properties that conventional shortest-path encodings cannot preserve. Second, instead of relying on soft penalties, a deterministic offspring verification and BFS-based repair mechanism is integrated to ensure that every individual in the population is fully feasible. Third, a post-routing extrusion optimization stage is incorporated to perform global refinement across nets, which is absent in prior GA or heuristic OER methods. These elements collectively distinguish the proposed method from both traditional metaheuristic routing frameworks and prior deterministic solutions.

The main scientific contributions of this work are formally summarized as follows:

• Novel Encoding Mechanism for OER: A grid transformation-based chromosome representation is developed to encode routing paths as structured integer sequences. Unlike traditional GA routing methods that represent paths directly as node or edge sequences, the proposed encoding preserves both path connectivity and strict pin ordering in a unified representation. This design enables efficient crossover and mutation operations while maintaining the structural properties required by ordered escape routing, which cannot be achieved using conventional shortest-path encodings.
• Constraint-Aware Feasibility Enforcement: A formal offspring verification protocol is embedded into the GA framework to ensure routing legality. In contrast to common penalty-only GA strategies that allow infeasible individuals to exist in the population, every candidate solution produced by crossover or mutation is rigorously checked against non-crossing and single-capacity constraints and, when necessary, repaired using a BFS-based mechanism. This procedure guarantees 0% constraint violation throughout the evolutionary process and ensures that all generated solutions are fully manufacturable.
• Hierarchical Fitness Function Design: A new objective formulation is introduced in which routing feasibility and ordering correctness are explicitly prioritized over wire length minimization. Unlike conventional GA objectives that combine feasibility and cost in a single aggregated score, the proposed hierarchical strategy guides the search process to first construct legal routing structures and only then optimize the geometric quality. This design prevents the algorithm from favoring short but illegal paths and provides systematic search guidance under strict OER constraints.
• Extrusion-Based Global Optimization Strategy: A multi-plan extrusion rerouting mechanism is proposed to dynamically refine previously routed nets after the initial GA solution is obtained. This post-processing stage enables coordinated optimization across multiple nets and partitions, allowing further reduction in the total wire length and improvement of the routing compactness. Such a global refinement procedure is not present in prior GA-based or deterministic OER methods and represents an additional layer of optimization beyond the standard evolutionary search.
• Comprehensive Empirical Validation with Measurable Gains: Extensive experiments on eight standard benchmark circuits demonstrate that the proposed method consistently outperforms state-of-the-art techniques, achieving up to 17.7% reduction in the total wire length while strictly satisfying all physical design constraints.

Through these innovations, the proposed framework establishes a practical and scalable alternative to traditional deterministic and partition-based approaches for ordered escape routing. More importantly, this work demonstrates that evolutionary algorithms can be effectively applied to highly constrained PCB routing problems only when equipped with problem-specific mechanisms. The combination of grid transformation encoding, deterministic feasibility verification, BFS-based repair, and extrusion-based global refinement forms an integrated optimization pipeline that cannot be realized by a standard GA formulation. The experimental results confirm that these components are essential for simultaneously achieving strict constraint satisfaction and competitive wire length optimization, thereby enabling genetic algorithms to solve complex OER instances that are difficult to handle using conventional techniques.

2. Background

2.1. Challenges in High-Density PCB Design

The relentless scaling of integrated circuit (IC) technologies has driven printed circuit board designs toward unprecedented integration densities and functional complexities [3,4]. In this landscape, Ball Grid Array and Chip Scale Package (CSP) technologies have become dominant interconnect solutions due to their ability to support high input/output (I/O) counts within compact footprints [3,4]. However, as pin counts rise into the thousands and pitches decrease, the “escape routing” process—routing signals from the array’s inner pins to its periphery—has evolved into one of the most critical and time-consuming bottlenecks in the physical design flow [2,3]. The complexity is further exacerbated by the need to minimize the number of PCB layers to reduce manufacturing costs [3,26].

2.2. Ordered Escape Routing (OER) and Constraints

Escape routing is fundamentally categorized into unordered escape routing (UER) and ordered escape routing (OER) [3,22]. While UER allows pins to exit the component boundary in arbitrary sequences, it often complicates the subsequent “area routing” stage, potentially leading to severe wire crossings and insufficient routing resources between components [3,6]. Consequently, OER, which imposes a specific sequence on escaping nets to align with board-level bus structures, is essential for high-speed designs to ensure signal integrity and routability [2,22].

Successful OER must strictly adhere to physical design rules. Primary among these are the non-crossing constraint (planarity), which dictates that escape paths on a single layer must not intersect, and the channel capacity constraint (often single-capacity in high-density designs), which limits the number of wires passing between adjacent pins [2,27]. Violating these constraints renders a routing solution physically impossible to manufacture.

2.3. Limitations of Deterministic Approaches

To address these routing challenges, researchers have modeled escape routing using various mathematical frameworks. Network flow models have been widely adopted to optimize flow under capacity constraints [2,28]. While efficient for specific sub-problems, standard flow models often struggle to incorporate complex ordering constraints without significant modifications [2]. Alternatively, integer linear programming (ILP) and Boolean satisfiability (SAT) approaches have been proposed to rigorously handle the complex constraints of OER and guarantee optimal solutions [2,28]. However, these exact methods are computationally intensive. As problem sizes grow, the runtime for these deterministic algorithms often becomes prohibitive due to the NP-hard nature of the underlying combinatorial problems [2,27]. Furthermore, heuristic approaches based on maze routing or rip-up and reroute strategies, while faster, are prone to getting trapped in local optima, potentially failing to find a solution in dense designs [29].

2.4. Motivation for Genetic Algorithm Optimization

Given the limitations of deterministic and greedy heuristic methods, evolutionary computation techniques offer a compelling alternative. Genetic algorithms have demonstrated robust performance in solving complex combinatorial optimization problems in VLSI and PCB domains, such as component placement, facility layout, and path optimization [20,25,30]. By simulating natural selection through crossover and mutation operators, GAs can effectively explore vast solution spaces and escape local optima [24]. Despite their success in related fields, applying GAs specifically to the strictly constrained OER problem requires novel encoding and operator designs to ensure that generated solutions remain valid regarding non-crossing and capacity rules. This study aims to bridge this gap by proposing a GA-based optimization framework tailored for OER.

3. Research Objectives and Methodology

3.1. Research Objectives

The primary objective of this research is to develop an efficient genetic algorithm-based optimization method for solving the ordered escape routing problem in Ball Grid Array printed circuit boards. Specifically, this research aims to:

• Minimize total wire length while satisfying all routing constraints, thereby reducing signal delay and manufacturing costs.
• Ensure non-crossing constraints between escape routes to prevent electrical shorts and signal interference.
• Enforce single-capacity constraints on routing resources, ensuring each edge in the routing graph is used by at most one route.
• Develop an ordered routing strategy that sequentially routes pins while avoiding conflicts with previously routed paths.

3.2. Problem Formulation

The BGA escape routing problem is modeled as a directed graph $G = (V, E)$, where the node set $V$ consists of four types:

• Pin nodes ($P$): Source nodes representing BGA balls requiring escape routing.
• Tile nodes ($T$): Primary routing resources on the main PCB layer.
• Imaginary nodes ($I$): Auxiliary routing resources for layer transitions and diagonal routing.
• Boundary nodes ($B$): Sink nodes located at the PCB periphery where routes terminate.

Consistent with the multi-commodity flow formulation in [5], fundamental flow conservation constraints are adopted.

The edge set $E$ represents geometrically valid connections between these nodes based on physical adjacency. The routing of each net is modeled as a unit flow from its corresponding pin node to an appropriate boundary node.

For all internal relay nodes (tile or image nodes), the net flow must be conserved:

$$\sum _{e\in {IE}_v}{x}_i^e-\sum _{e\in {OE}_v}{x}_i^e =0, i=1,\dots ,L, \forall v\in V\backslash \left\{v_i^e,v_1^b\right\}$$

(1)

where $I{E}_v$ and ${OE}_v$ denote the sets of incoming and outgoing edges of vertex $v$, and $x_i^eϵ\left\{\mathrm{0,1}\right\}$ indicates whether commodity $i$ uses edge $e$.

For each escape (source) vertex, exactly one unit of flow must leave:

$$\sum _{e\in {OE}_v}{x}_i^e-\sum _{e\in {IE}_v}{x}_i^e =1, i=1,...,L, \forall v\in V_{e }$$

(2)

Boundary vertices act as sinks and can only receive incoming edges, ensuring that all routing paths terminate at valid boundary locations. These formulations correspond directly to Equations (1) and (2) in the reference model.

The weighted edge model used in this work is derived from Equation (5) and adapted to our routing environment. The cost of each directed edge $e_{wv}$ is defined as

$$c(e_{wv})=\left\{\begin{array}{ll}1,& w\left(v\right)\in V_t,\hspace{0.25em}v\left(w\right)\in V_{tb}\\ 0.5,& w\left(v\right)\in V_i,\hspace{0.25em}v\left(w\right)\in V_{tb}\\ 0.5,& w\in V_e,\hspace{0.25em}v\in V_{tb}\\ 0,& otherwise\end{array}\right.$$

(3)

where $V_{tb}=V_t\cup V_b$.

This weighting scheme reflects the physical characteristics of PCB routing: tile-to-tile connections represent full-length routing segments, while transitions involving image nodes or escape nodes correspond to partial segments and therefore incur reduced costs.

3.3. Methodology

3.3.1. Graph Construction

The routing environment is modeled as an $m \times n$ grid structure with configurable dimensions. Figure 1 illustrates an example configuration with $m=4$ and $n = 3$, which is used throughout this paper to demonstrate the proposed graph construction process. The modeling procedure consists of the following steps:

• Pin node placement: Position pin nodes according to the BGA ball array layout.
• Tile grid generation: Create an $m\times n$ uniform grid of tile nodes for primary layer routing.
• Imaginary node insertion: Add image nodes for vertical and diagonal routing capabilities.
• Boundary node creation: Place boundary nodes on all four sides (South, East, North, West).
• Adjacency list construction: Build connections between geometrically adjacent nodes.

The resulting graph provides a complete representation of available routing resources and their interconnections.

3.3.2. Initial Population Generation

Following the diversity-oriented initialization strategy commonly adopted in genetic algorithms for shortest path problems, the initial population is generated using a structured four-step algorithmic procedure:

• Route generation: For each pin, create 50 candidate routes to various boundary nodes.
• Boundary selection strategy: Apply boundary ordering preference (ascending/descending) to ensure spatial diversity.
• Conflict avoidance: Filter out routes that conflict with existing routed paths.
• Feasibility verification: Validate each route against flow conservation and capacity constraints.

This approach ensures a diverse initial population covering different routing regions while maintaining solution feasibility. The population diversity is crucial for effective exploration of the solution space in subsequent genetic operations.

3.3.3. Chromosome Encoding Scheme

To enable effective genetic operations on routing paths, a specialized grid-based encoding strategy is employed. The encoding process consists of the following structured steps:

• The original routing environment is represented by an $m\times n$ tile grid. To provide sufficient resolution for genetic manipulation, each tile is subdivided into a finer $3 \times 3$ subgrid, producing a higher-resolution GA grid. Edges that connect to external boundaries (Pin→Boundary and Imaginary→Boundary) are not included in the GA representation, because boundary connections are determined deterministically after escape routing and are not part of the evolutionary search space. Only the internal routing structure consisting of Pin→Tile, Tile→Imaginary, and Imaginary→Tile edges is mapped into the GA grid. After applying the subdivision factor and removing redundant outer boundary segments, the GA grid dimensions are determined as

  $$\begin{array}{c}g{a}_{rows}=m\times 3-3\\ g{a}_{cols}=n\times 3-3\end{array}$$

  (4)

  To clearly illustrate this transformation, Figure 2 presents a sliced view of the OER grid shown in Figure 1. This slice-based illustration demonstrates how the internal routing resources are reorganized into a regular two-dimensional GA matrix. Grid positions that do not correspond to actual routing edges are filled with Tile nodes, forming a complete rectangular GA grid suitable for chromosome representation.
• Path decomposition: Each routing path generated on the original grid is mapped onto the GA grid and decomposed into segments according to individual rows. This decomposition facilitates localized genetic operations without breaking the overall path connectivity.
• Row encoding: For every row in the GA grid, the starting and ending column positions of the path segment are recorded. This representation captures the essential geometric information of the route in a compact and structured form.
• Chromosome representation: The complete routing path is encoded as a sequence of integer tuples in the form ($row, star{t}_{col}, en{d}_{col}$). All elements of a chromosome are therefore integers representing grid coordinates in the GA matrix. No real-valued or binary variables are used. These integers correspond directly to node indices within the transformed routing space illustrated in Figure 2.

This integer-based encoding scheme preserves both the path connectivity and ordering information while providing a representation well suited for discrete genetic operations such as crossover and mutation. The higher-resolution GA grid allows finer-grained modifications and greater flexibility in exploring alternative routing solutions, while still maintaining a one-to-one correspondence with the actual internal routing channels of the OER structure.

3.3.4. Genetic Algorithm Operations

Equation (5) is used in the initial path construction stage to guide the selection of the next node when generating candidate escape routes. Two evaluation terms are considered for each neighboring node:

• $Scor{e}_{direction}$ evaluates how well the movement direction of a candidate step aligns with the target boundary direction. It is computed using the cosine similarity between the vector from the current node to the target boundary and the vector from the current node to the candidate neighbor. The resulting value lies within the range $\left[-1, 1\right]$, where a larger value indicates a step that is more consistent with the desired escape direction.
• $Scor{e}_{distance}$ measures the proximity of the candidate neighbor to the target boundary. It is defined as the negative Euclidean distance from the neighbor node to the target boundary, $Scor{e}_{distance}=-d(neighbor,target)$, and therefore takes non-positive values whose magnitude depends on the grid size.

To combine these two criteria, a weighted local step score is computed as

$${Score}_{final}=2.0 · {Score}_{direction}+0.1 · {Score}_{distance}$$

(5)

This formulation reflects a hierarchical preference: direction consistency is emphasized as the primary factor, while distance reduction plays a secondary role. In implementation, the resulting step scores are transformed into selection probabilities using a softmax-style normalization (subtracting the maximum score before exponentiation). This probabilistic mechanism avoids scale sensitivity and enables diverse route generation during initialization.

It is important to note that Equation (5) is used only for local decision making during initial population generation. After complete routes are constructed, the genetic algorithm evaluates and ranks individuals using the effective length metric defined in Section 4.2, which serves as the main objective for evolutionary optimization.

The main genetic algorithm operations are performed as follows:

• Selection: Roulette wheel selection with elitism (best individual preserved).
• Crossover: Path recombination at common tiles ($rate = 0.6$) [31].
• Mutation: Random tile replacement with adjacent nodes ($rate = 0.001$) [31].
• Constraint Validation: All offspring validated for flow conservation, edge capacity, non-crossing, and connectivity.
• Ordered Sequential Routing: Pins routed sequentially, each avoiding previously occupied edges.
• Termination: The process stops when the population converges or reaches a maximum of 1000 generations. This limit is set as a conservative upper bound, as the algorithm typically achieves convergence well before reaching this threshold.

Through this combination of probabilistic initialization, constraint-aware genetic operations, and effective length-based evaluation, the algorithm is able to generate high-quality and fully feasible escape routing solutions.

4. Genetic Algorithm-Based for Ordered Escape Routing

The overall architecture of the proposed GA-OER framework is illustrated in Figure 3. The process initiates with the construction of a directed routing graph $G$ from the BGA layout specifications and design constraints. Each net is then processed sequentially to satisfy ordering requirements. Within the core GA loop, candidate paths are encoded onto a specialized grid. A key feature is the BFS-based repair mechanism integrated into the mutation operator, which recovers connectivity for broken paths by exploring adjacent nodes within a defined cap. Finally, the multi-plan extrusion optimization refines the total wire length by strategically rerouting previously placed nets to accommodate the current connection in a more efficient manner.

4.1. Initial Gene Pool

The proposed genetic algorithm begins with the generation of an initial gene pool, which serves as the foundation for the evolutionary optimization process. This work adopts a Gaussian distribution-based initialization method inspired by the raster-based routing algorithm proposed.

4.1.1. Path Generation Strategy

For each pin connection, the algorithm generates a population of 50 candidate routing paths from the pin node to boundary nodes on the chip periphery. The initialization process follows three key principles:

• Directional bias toward target: Each path is constructed incrementally with movement decisions weighted by the Euclidean distance to the target boundary.
• Gaussian-distributed exploration: At each routing step, the next node is selected using a probability distribution combining directional scoring with Gaussian randomization (standard deviation = 1.0).
• Constraint-aware generation: The path generation enforces edge capacity, tile crossing avoidance, and pin conflict constraints.

4.1.2. Boundary Node Selection

A dynamic windowing strategy is employed for boundary selection to restrict the search space for each net. Let $b_{start}$ denote the minimum index among the currently available boundary nodes. A boundary window of size $12$ is defined relative to this starting index, forming a set of candidate boundaries $B_{cand}$:

$$B_{cand}=\left\{b|b_{start}\le b\le b_{start}+11\right\}$$

(6)

Boundaries within $B_{cand}$ are prioritized based on ascending order (default) to minimize resource consumption, or descending order when peripheral routing is required. This formalized selection ensures that the genetic algorithm explores a manageable and spatially diverse range of exit points for each pin.

4.1.3. Population Structure

Each individual in the initial gene pool is represented as $P_{1\dots N}$ where effective length includes penalty terms. The population size of 50 provides sufficient diversity for effective evolution while maintaining computational efficiency.

4.2. Overall Fitness Function Calculation

The fitness function serves as the objective measure for evaluating the quality of each routing path in the population. Unlike simple distance-based metrics, this work employs a comprehensive fitness function that balances multiple routing objectives including path length, boundary preference, and path smoothness.

4.2.1. Effective Length Calculation

The overall fitness of a path is determined by its effective length, which combines the actual geometric length with penalty terms:

$$Effective Length = Actual Length + Boundary Penalty + Turn \mathrm{Penalty}$$

(7)

where each component is calculated as follows:

• The actual length of a routing path is computed based on a Normalized Graph-Step Model. To ensure metric consistency and a fair performance comparison with the baseline study [5], we define the cost of routing segments as follows:
  • Orthogonal and Diagonal Steps: Each transition between adjacent tile nodes (whether horizontal, vertical, or diagonal) is assigned a total logical distance of $1.0$. This is implemented by assigning each constituent edge in the graph a weight of $0.5$.
  • Metric Alignment: This unit-step formulation is intentionally chosen to align with the cost models established in [5]. By utilizing an identical distance metric, the optimization gains reported in

    Table 1. Comparison table of aggregated data from fifty experiments.

    Benchmark	Col	Row	Net	Type	[5]		[Ours]
    					Length	Time (s)	Length	Time (s)
    Case1	6	5	4	1-side	10.10 ± 4.00	$0.36\pm$0.13	$9.70\pm 3.50$	$0.42\pm 0.12$
    Case2	6	5	8	3-side	$15.40\pm 3.40$	$0.82\pm$0.91	$13.05\pm 3.50$	$1.05\pm 1.05$
    Case3	6	6	15	3-side	$24.30\pm$4.30	$2.01\pm$0.28	$22.40\pm 2.75$	$2.34\pm 0.95$
    Case4	10	6	25	3-side	$36.30\pm$6.70	$8.51\pm 3.11$	$30.80\pm 4.75$	$4.51\pm 2.40$
    Case5	6	17	18	1-side	$45.00\pm$10.00	$16.76\pm 5.87$	$41.70\pm 10.00$	$4.74\pm 2.10$
    Case6	20	21	42	4-side	$171.00\pm 6.54$	$80.01\pm 9.6$0	$159.75\pm 5.12$	$31.51\pm 8.2$0
    Case7	25	26	60	4-side	$362.47\pm 18.92$	$143.68\pm 18.92$	$298.75\pm 15.45$	$54.92\pm 12.50$
    Case8	50	50	130	3-side	$1246.83\pm 57.41$	$721.84\pm 93.62$	$1101.15\pm 42.30$	$482.14\pm 95.00$

    reflect a genuine improvement in the routing efficiency and global search capability across the BGA grid.
• Boundary Preference Penalty: To guide the algorithm toward preferred boundary selections and to reduce potential resource conflicts, a boundary preference penalty is introduced:

$$\begin{array}{cc}\hfill Raw Boundary& Penalty\hfill \\ & =|Boundary Number\hfill \\ & -Preferred Bondary Number|\times w_b\hfill \end{array}$$

(8)

In the revised implementation, the weight is set to $w_b = 1$. This parameter is used only for ranking and comparing candidate routes during the search process and does not affect the final physical length calculation. Since the penalty serves solely as a relative comparison measure, using a unified constant value is sufficient and avoids unnecessary parameter tuning. To prevent the penalty from dominating the evaluation, a cap is enforced:

$$Boundary Penalty = min(Raw Boundary Penalty, Actual Length \times 0.5)$$

(9)

This formulation ensures that the penalty remains a secondary factor and never exceeds 50% of the actual path length.

3.

Turn Penalty: To discourage zigzag patterns and to promote smoother routing paths, a turn penalty is applied:

$$Turn Penalty=Number of Turns\times w_t$$

(10)

In the revised manuscript, the turn weight is also unified to $w_t = 1$. Similar to the boundary penalty, this term is used only to compare alternative routing candidates and does not modify the actual wire length used for final evaluation. Therefore, assigning a constant value of 1 provides a simple and consistent mechanism to penalize unnecessary direction changes without introducing additional tuning parameters.

4.2.2. Compatibility Penalty

For paths that violate routing constraints (edge capacity or tile crossing conflicts), an incompatibility penalty of ${10}^6$ is added to the effective length, effectively eliminating them from selection while maintaining population diversity.

4.2.3. Fitness Value

Selection Fitness Value: For the genetic algorithm’s selection mechanisms (such as the roulette wheel), the selection fitness value is defined as the inverse of the effective length (calculated in Equation (7)). This inverse transformation ensures that paths with shorter effective lengths (lower costs) receive higher selection probabilities:

$$Fitness = {\displaystyle \frac{1}{(Effective Length + \epsilon )}}$$

(11)

where $\epsilon = 10^\{-6\}$ is a small constant to prevent division by zero. Shorter paths yield higher fitness values, making them more likely to be selected for reproduction.

4.3. Selection Mechanisms and Elite Retention

The genetic algorithm employs a hybrid selection strategy combining roulette wheel selection for parent selection and elitism for preserving the best solutions across generations.

4.3.1. Roulette Wheel Selection

Parent individuals are selected using fitness-proportionate roulette wheel selection. The selection probability for each individual is

$$P(individua{l}_i)={\displaystyle \frac{Fitnes{s}_i }{\Sigma Fitnes{s}_j}}$$

(12)

where $Fitnes{s}_i = 1/(L_i + \epsilon )$ with $\epsilon = 10^\{-6\}$. This mechanism ensures that shorter paths have higher selection probabilities while preserving diversity. Two parents are independently selected for each crossover operation.

4.3.2. Elite Retention Strategy

The top-performing individual is automatically preserved to the next generation without modification:

$$Elite = arg min(Effective Lengt{h}_i)$$

(13)

This guarantees monotonic improvement in the best solution quality across generations.

4.3.3. Generation Transition

The next generation is constructed as follows:

• Initialize with the elite individual.
• Fill remaining population through roulette wheel selection and crossover.
• Apply mutation to complete population.

The population size remains fixed at 50 individuals throughout evolution.

4.4. Path Crossover

The crossover operator generates offspring by combining genetic material from two parent paths. This work employs a common tile-based crossover strategy that ensures the validity and connectivity of offspring paths.

4.4.1. Crossover Strategy

The crossover operation is applied with a probability of 0.6 (crossover rate) [31]. When triggered, the algorithm identifies common tile nodes shared by both parent paths and exchanges path segments at these intersection points.$Common Tiles = \{T | T \in {Parent}_1 \wedge T \in {Parent}_2 \wedge T starts with ‘T’\}.$ If no common tiles exist between the parents, crossover fails and the parents are directly copied to the next generation.

4.4.2. Crossover Point Selection

When common tiles are identified, one is randomly selected as the crossover point. Let the selected tile be $Til{e}_c$, with indices $i_1$ and $i_2$ in ${Parent}_1$ and ${Parent}_2$ respectively:

$$Crossover Point = random(Common Tiles)$$

(14)

4.4.3. Offspring Generation

Two offspring are generated by exchanging the path segments after the crossover point:

• ${Offspring}_1 = {Parent}_1[0:i_1+1] + {Parent}_2[i_2+1:end]$
• ${Offspring}_2 = {Parent}_2[0:i_2+1] + {Parent}_1[i_1+1:end]$

This ensures that both offspring paths remain connected through the common tile node, maintaining path validity.

4.4.4. Compatibility Verification

Each generated offspring is verified against routing constraints before inclusion in the next generation. If an offspring violates the edge capacity or tile crossing constraints, it is rejected and replaced by its corresponding parent. This fallback mechanism ensures population viability while encouraging exploration through crossover.

4.5. Path Mutation

The mutation operator introduces random variations into the population to prevent premature convergence and explore new regions of the solution space. This work employs a tile-replacement mutation strategy with subsequent path repair.

4.5.1. Mutation Probability

Each individual in the population undergoes mutation with probability 0.001 (mutation rate) [31]. This relatively low rate balances exploration with preservation of good genetic material accumulated through selection and crossover.

4.5.2. Mutation Mechanism

When a mutation is triggered for a path, the operation proceeds as follows:

• Tile Selection: Randomly select an intermediate tile node (excluding start and end tiles) from the path.
• Neighbor Discovery: Identify alternative tiles accessible through adjacent image nodes.
• Tile Replacement: Replace the selected tile with a randomly chosen neighbor tile not already in the path.
• Path Repair: Use breadth-first search (BFS) to reconnect from the new tile to the original target boundary.

The mutation creates a detour through an alternative tile, potentially discovering shorter or less congested routes.

4.5.3. Path Repair via BFS

After tile replacement, the path from the new tile to the target boundary may be broken. A limited BFS (maximum 100 nodes explored) is performed to find a valid reconnection:

• Start: New mutated tile.
• Goal: Original boundary node.
• Constraint: Avoid revisiting nodes already in the path prefix.

If BFS successfully finds a path, the mutated individual replaces the original. Otherwise, the original path is retained.

4.5.4. Mutation Validation

After path repair, the mutated path undergoes compatibility verification. If the mutation introduces edge conflicts or tile crossing violations, it is rejected and the original individual is preserved. This ensures that all individuals in the population remain feasible throughout evolution.

4.6. Offspring Compatibility Verification

To strictly enforce the non-crossing and single-capacity constraints throughout the evolutionary process, every offspring generated by crossover or mutation must pass a formal compatibility verification before being admitted into the population. This verification mechanism guarantees that the genetic algorithm operates entirely within the feasible solution space. The procedure consists of a deterministic two-phase validation protocol described below.

4.6.1. Existing Usage Tracking

Prior to evaluating a newly generated offspring, the algorithm constructs a resource usage map based on all previously accepted routing paths. This map contains two key components:

• Used Edges: A set of undirected edges that are already occupied by existing routes. Each edge is stored as a sorted node pair ($N_i,N_j$) to ensure symmetric representation.
• Tile Directions: A mapping that records the traversal direction of each tile node, categorized as horizontal, vertical, turn, or endpoint. These directions are determined by analyzing the geometric relationship between adjacent nodes along the routed paths.

This resource map represents the current legal state of the routing environment and serves as the reference for all subsequent compatibility checks.

4.6.2. Edge Capacity Verification

The first phase verifies compliance with the single-capacity constraint. For each edge $\left(N_i, N_{\left\{i+1\right\}}\right)$ in the candidate offspring path, the following check is performed:

• If sorted $(N_i, N_{\left\{i+1\right\}}) \in Used Edges$, the offspring is immediately rejected.

Since every edge in the routing graph has unit capacity, any overlap with an existing route constitutes a violation. This step ensures that no routing resource is assigned to more than one path.

4.6.3. Tile Crossing Verification

The second phase verifies compliance with the non-crossing constraint at the tile level. For each tile node visited by the offspring, its traversal direction is determined from the coordinates of its adjacent:

• Vertical: Both adjacent nodes aligned vertically $\left(\right|\Delta x| < 0.01)$;
• Horizontal: Both adjacent nodes aligned horizontally $\left(\right|\Delta y| < 0.01)$;
• Turn: Mixed alignment or diagonal movement.

If a tile node already has a recorded direction from previously routed paths, a conflict test is performed. The offspring is rejected if any of the following conditions occur:

• A horizontal path attempts to cross an existing vertical path (or vice versa).
• A path attempts to reuse a tile that has already been used for a turning segment.
• A new turn is introduced at a tile currently occupied by a straight-through segment.

These checks collectively ensure that no geometric crossing or illegal reuse of tile resources can occur.

4.6.4. Fallback Strategy

If an offspring fails any of the above compatibility checks, it is not allowed to enter the population. Instead, a conservative fallback mechanism is applied:

• After crossover: The invalid offspring is replaced by its corresponding parent individual.
• After mutation: The original unmutated individual is retained.

This strategy preserves population feasibility while still enabling effective exploration through genetic operations.

4.7. Sorting and Convergence Judgment

After mutation, the population is evaluated and sorted to identify the best solutions and determine whether the algorithm has converged. This section describes the sorting criteria and convergence detection mechanism.

4.7.1. Population Sorting

At the end of each generation, individuals are sorted by their effective length to identify the best-performing solution:

$$Best in Generation = arg min(Effective Lengt{h}_i)$$

(15)

For tie-breaking when multiple individuals have identical effective lengths, the boundary preference order is applied:

• Ascending order: Select the individual with smaller boundary number.
• Descending order: Select the individual with larger boundary number.
• Final Winner: $arg min\left(\right(Effective Lengt{h}_i, \pm Boundary Numbe{r}_i\left)\right)$

4.7.2. Convergence Detection

The algorithm monitors population diversity to detect convergence. After each generation, the number of unique paths in the population is calculated:

$$Unique Paths = \left|\right\{Pat{h}_i | i \in Population\}|$$

(16)

Convergence criterion: If all individuals in the population have identical paths ($Unique Paths = 1$), the algorithm has converged and evolution terminates. This indicates that genetic operators can no longer produce diversity, and the population has settled on a single optimal or near-optimal solution.

4.7.3. Termination Conditions

The evolutionary process terminates when either condition is met:

• Full convergence: All paths in the population are identical.
• Maximum generations: Generation count reaches the limit (default: 1000).

Upon termination, the best individual from the final population is selected as the optimal routing solution for the current pin connection.

4.8. Gene Pool for the Next Generation

After selection, crossover, mutation, and compatibility verification, the next generation gene pool is constructed to replace the current population. This section describes the composition and transition mechanisms.

4.8.1. Next Generation Composition

The next generation is built through a sequential process:

• Elite initialization: The best individual from the current generation is directly copied.
• Offspring addition: Compatible offspring from crossover operations are added.
• Parent fallback: When offspring fail compatibility checks, the corresponding parents are substituted.
• Mutation application: All individuals (including elite) undergo mutation with probability 0.001.

The construction continues until the population size reaches 50 individuals.

4.8.2. Population Replacement Strategy

This work employs a generational replacement strategy where the entire current population is replaced by the next generation:

$$P_{\left\{t+1\right\}} = Next Generation after (Selection + Crossover + Mutation + Verification)$$

(17)

The only exception is the elite individual, which is guaranteed to survive through elitism, ensuring monotonic improvement.

4.8.3. Population Transition

After mutation is complete, the population transition occurs:

$$Current Population \leftarrow Mutated Generation$$

(18)

This updates the working population for the next evolutionary cycle. The transition maintains a constant population size of 50 individuals across all generations.

4.8.4. Generation Statistics

At the end of each generation, statistics are collected:

• Population size: Verified to remain at 50.
• Best individual: Individual with minimum effective length.
• Path diversity: Number of unique paths in the population.

These metrics provide insight into evolutionary progress and convergence behavior.

4.9. Extrusion Optimization

After routing each pin connection, a global optimization strategy is applied to minimize the total wire length across all routes. This multi-plan extrusion optimization evaluates different rerouting strategies and selects the configuration that yields the shortest cumulative path length.

4.9.1. Multi-Plan Rerouting Strategy

When routing $Pi{n}_i$, the algorithm generates multiple candidate plans based on the number of previous routes to reroute:

• Plan A: Baseline plan with no rerouting (current pin uses next available boundary).
• Plan B: Reroute one previously routed pin.
• Plan C: Reroute two previously routed pins.
• Plan D: Reroute three previously routed pins.
• Plan E: Reroute four previously routed pins.
• Plan F: Reroute five previously routed pins.

Each plan reroutes the most recently placed pins, allowing the current pin to potentially use a closer boundary by displacing earlier routes.

4.9.2. Plan Evaluation

For each feasible plan, the total wire length is computed by summing the lengths of all routes involved in that specific plan:

$$Total Length = {\sum }_{jϵPlan}Length\left(rout{e}_j\right)$$

(19)

For all routes $j$, the sum includes the current pin route and all rerouted pins after applying genetic algorithm optimization and diagonal optimization.

4.9.3. Best Plan Selection

The algorithm selects the plan with minimum total length:

$$Best Plan = arg min(Total Length\_plan)$$

(20)

where the summation is performed over the index $j$, representing the set of routes that includes the current pin connection and all nets selected for rerouting within the given plan after applying genetic algorithm optimization. This total cost serves as the primary metric for evaluating the global efficiency of each candidate plan.

4.10. Parameter Selection Rationale

The hyperparameters are selected to balance global search capability and computational cost. The population size ($N=50$) provides sufficient diversity for the grid sizes tested. The crossover (0.6) and mutation (0.001) rates are set to promote genetic exchange without destroying high-quality segments. Furthermore, the fitness weights $w_b = 1$ and $w_t = 1$ were determined through empirical sensitivity testing. A hierarchical strategy is employed where $w_t > w_b$ to prioritize the reduction in zigzag patterns, as straightness is prioritized over boundary alignment in high-density designs. The $0.5$ scaling factor in Equation (9) serves as a guard to prevent penalty terms from dominating the search process, ensuring wire length minimization remains the primary driver of evolution.

Notably, Max Generations (1000) serves as a conservative upper bound to guarantee termination. Due to the convergence detection mechanism (Section 4.7.2), the algorithm typically achieves full convergence and exits early within 200 generations, meaning the 1000-generation limit acts as a safety margin rather than a fixed execution requirement.

5. Results

In this section, we evaluate the performance of the proposed genetic algorithm (GA)-based optimization method for ordered escape routing (OER). The effectiveness of the algorithm is assessed using eight benchmark circuits (Case 1 to Case 8), which vary in grid size and net density. All experiments were conducted on a workstation equipped with an Intel i5-14500 CPU, 16 GB RAM, running Windows OS, and the algorithm was implemented in Python 3.10.11. To ensure statistical reliability, each benchmark was executed for 50 independent runs, and the reported results are based on the mean and standard deviation over these runs. The experimental outcomes are compared against the prior study in [5] to demonstrate the proposed method’s optimization capability in terms of total wire length, routing feasibility, and compliance with strict non-crossing and single-capacity constraints.

5.1. Performance Comparison

Table 1 reports the aggregated results obtained from fifty independent experimental runs for all benchmark cases. Two performance metrics are evaluated: total wire length and computational time.

For all benchmark cases (Case 1–Case 8), the ILP-based method from [5] and the proposed GA-based approach were evaluated under identical experimental conditions. Specifically, the same randomly generated initial node configurations were used for both methods in each run, and fifty independent trials were conducted per case. The values reported in Table 1 represent the mean and standard deviation over these repeated experiments, ensuring a fair and unbiased comparison.

The results in Table 1 clearly demonstrate that the proposed GA-based method consistently outperforms the ILP-based approach across all benchmark cases. In every case, the GA method achieves shorter total wire lengths while also requiring less computational time. These results indicate that the proposed approach is able to simultaneously improve the routing quality and computational efficiency.

As the problem scale increases, the performance advantages of the GA-based method become more evident. While the ILP-based approach experiences a rapid increase in computational cost and solution complexity, the GA-based method maintains stable execution time and continues to generate shorter routing paths. This behavior highlights the superior scalability of the proposed method when handling larger and more complex PCB routing problems.

Overall, the experimental results confirm that the proposed GA-based approach provides a more efficient and effective solution than the ILP-based method in [5]. By consistently producing shorter wire lengths with reduced computation time under identical experimental settings, the proposed method demonstrates strong potential for practical applications in real-world PCB routing and large-scale design scenarios.

5.2. Result Image

The visual outputs of the OER solutions for the three benchmarks are true experimental settings in Figure 4, Figure 5, Figure 6, Figure 7, Figure 8 and Figure 9. These figures confirm that our algorithm successfully satisfies the non-crossing and single-capacity constraints, ensuring that each routing path occupies a unique grid channel without intersection.

Figure 4 presents the routing result for Case 6, a 20 × 21 grid with 42 nets using a four-side escape strategy. The visualization demonstrates that the proposed GA effectively navigates the grid channels between BGA pins. Each net is successfully routed to its assigned boundary without violating the non-crossing constraint. Furthermore, the algorithm demonstrates high efficiency in channel utilization; even in the peripheral areas where net density is highest, the paths remain orderly. The results show that for small-scale problems, the GA can identify paths that are near-optimal, maintaining a balance between total wire length and uniform distribution across the four boundaries.

Figure 5 shows the true experimental settings of the routing solution for Case 7 ($25\times 26$ grid, $60$ nets) generated by the ILP-based method [5], represented by blue lines, while Figure 6 shows the routing results produced by our proposed GA method, represented by red lines. In both figures, black lines denote routing segments that are identical in the two methods, highlighting portions of the solution space where both approaches make the same routing decisions. As the net density increases and routing resources become congested, the deterministic ILP approach may produce redundant detours to avoid conflicts, which can be observed in the blue routes. In contrast, the GA explores the solution space more flexibly and is able to identify more direct and compact paths in congested regions, which is the primary driver behind the $17.7\mathrm{\%}$ reduction in the total wire length compared to the baseline. The results also visually confirm that the single-capacity and non-crossing constraints are strictly maintained, with each routing channel occupied by at most one net, ensuring manufacturability and signal integrity.

Figure 7 presents the routing results for Case 8 using the ILP-based baseline [5], indicated by blue lines. Figure 8 shows the true experimental settings of the results of our GA-based approach for this most challenging benchmark using red lines, featuring a dense $50\times 50$ grid and 130 nets restricted to a three-side escape. This scenario represents a high-density BGA environment where congestion in the center of the chip is a significant risk. The red routing pattern generated by our method in Figure 8 demonstrates a sophisticated level of congestion management. As visualized in the quadrants of Figure 8, the GA successfully distributes the nets across the available three sides, effectively avoiding “deadlocks” in the routing process. To provide a clearer view of the detailed routing structure, Figure 9 presents Case 8 divided into four parts for magnified viewing, enabling closer inspection of the path distribution in each region. Despite the high net-to-grid ratio, the red paths maintain the required “ordered” sequence at the boundaries. The successful routing of Case 8 in Figure 6 and Figure 8 validates the scalability of our GA-based approach, proving that it can find globally optimized red paths even in highly constrained and large-scale PCB layouts.

5.3. Robustness Analysis of Weight Variation

To verify that the proposed GA performance is not overly sensitive to the specific weights used in Equation (6), we conducted a sensitivity analysis on Case 7 by varying the weight direction and distance. The results, summarized in

Table 2. Robustness analysis of weight variations (Case 7).

Direction	Distance	Success Rate	Total Length	Improvement (%)
1.0	0.1	96.5%	302.15	16.76%
2.0	0.1	98.5%	298.75	17.70%
3.0	0.1	98.5%	299.80	17.41%
2.0	0.05	98.0%	304.50	16.11%
2.0	0.2	95.5%	296.20	18.40%

, demonstrate that the algorithm consistently achieves high routing success rates and stable wire length minimization across a broad range of weight ratios. This confirms that the claimed optimization gains are robust and not over-fitted to specific parameter values.

5.4. Hyperparameter Sensitivity and Ablation Study

To evaluate the systematic tuning rationale, each key parameter was varied.

Table 3. Sensitivity analysis of GA hyperparameters (Case 7).

Hyperparameter	Value	Success Rate	Total Length	Avg. Runtime (s)
$\mathrm{Population} \mathrm{Size} (N$)	25	92.0%	304.45	25.2
	50 (Default)	98.5%	298.75	54.9
	100	98.8%	298.40	104.0
$\mathrm{Crossover} \mathrm{Rate} (P_c$)	0.4	94.5%	302.10	53.6
	0.6 (Default)	98.5%	298.75	54.9
	0.8	97.2%	299.85	54.4
$\mathrm{Mutation} \mathrm{Rate} (P_m$)	0.0001	93.8%	304.20	53.1
	0.001 (Default)	98.5%	298.75	54.9
	0.01	95.5%	301.50	272.3
BFS Repair Cap	50	90.5%	308.25	54.4
	100 (Default)	98.5%	298.75	54.9
	200	98.7%	298.60	79.08
Max Generations	500	94.0%	303.80	52.0
	1000 (Default)	98.5%	298.75	54.9 (Early Exit)
Boundary Window	8	91.2%	312.40	30.2
	12 (Default)	98.5%	298.75	54.9

confirms that the current settings represent an optimal balance between routing success and runtime.

5.5. Quantitative Evaluation of Constraint Satisfaction

To verify the reliability of the proposed algorithm in satisfying the physical design rules, we conducted a quantitative analysis of constraint violations across all benchmark circuits.

Table 4. Quantitative constraint violation rates across 10 experimental runs.

Benchmark	Total Nets	Total Runs	Non-Crossing Violations	Single-Capacity Violations	Violation Rate (%)
Case1	4	50	0	0	0.00%
Case2	8	50	0	0	0.00%
Case3	15	50	0	0	0.00%
Case4	25	50	0	0	0.00%
Case5	18	50	0	0	0.00%
Case6	42	50	0	0	0.00%
Case7	60	50	0	0	0.00%
Case8	130	50	0	0	0.00%

summarizes the violation rates for the non-crossing and single-capacity constraints over 10 independent experimental runs for each case.

Discussion of Constraint Results: The results in Table 4 demonstrate a consistent $0\%$ violation rate across all tested scenarios, from small-scale (Case 1) to high-density large-scale layouts (Case 8). This perfect adherence to design rules is attributed to the “Constraint-Aware Evolution” strategy implemented in our framework:

• Real-time Validation: Every offspring generated through crossover or mutation is immediately subjected to a multi-phase verification protocol before population inclusion.
• Strict Fallback: If a genetic operation results in a path that intersects an existing route or exceeds the edge capacity, the algorithm invokes a fallback strategy, discarding the illegal individual and retaining the legal parent.
• Reliability: This “Correct-by-Construction” approach ensures that the GA search is confined to the feasible solution space. Consequently, the optimization gains reported in Table 1 are achieved without compromising the structural integrity of the PCB routing, guaranteeing that all generated paths are fully compliant with manufacturing constraints.

6. Discussion and Future

6.1. Discussion

The experimental results demonstrate that the proposed genetic algorithm (GA)-based method provides a superior capability for wire length optimization in ordered escape routing (OER). The most notable finding is the 17.7% reduction in the total wire length for Case 7, suggesting that while existing heuristic methods can find feasible solutions quickly, they often converge on local optima with redundant path bends. In contrast, our GA-based approach explores a larger solution space, identifying more direct paths while strictly adhering to non-crossing and single-capacity constraints. Regarding computational efficiency, although the GA requires more time than traditional heuristics due to its iterative nature, this trade-off is justified in PCB physical design. Since routing is typically an offline process, minimizing wire length—which directly impacts signal integrity and board area—is prioritized over instantaneous execution. The successful routing of the large-scale Case 8 (50 × 50 grid) further confirms that our algorithm remains stable and effective even as problem complexity and net density increase.

Looking ahead, several avenues for future research remain to further enhance the utility of this method. First, extending the GA framework to handle multi-layer BGA escape routing would address more complex modern PCB architectures by optimizing via placement and layer assignment. Second, to address the higher computational cost, implementing parallel computing or hybridizing the GA with local search heuristics could significantly reduce the convergence time for ultra-large-scale grids. Finally, incorporating more sophisticated design rules, such as differential pair routing and crosstalk minimization, into the fitness function would allow the algorithm to meet the rigorous demands of high-speed digital designs and practical manufacturing constraints.

6.2. Computational Complexity and Scalability Analysis

To provide a rigorous evaluation of the proposed GA-OER framework, we analyze its time complexity and memory footprint relative to the grid dimensions ($m\times n$) and the number of nets ($L$).

• Time Complexity per Generation: In each evolutionary cycle, the algorithm performs genetic operations on a fixed population of $N=50$ individuals.

  ○

  Fitness Evaluation and Crossover: These operators traverse the path segments in the GA grid, which has a resolution of approximately $3m\times 3n$. The complexity is $O(N·D)$, where $D$ is the path length.

  ○

  Mutation and Path Repair: The mutation includes a limited BFS capped at $B=100$ nodes. The complexity is $O(N·B)$.

  ○

  Total per Generation: The complexity per generation per net is $O(N·(D+B\left)\right)$. Since $N$ and $B$ are constants, the generation cost scales linearly with the path length $D$.

• Per-Net and Total Routing Cost: The total routing time for $L$ nets is influenced by the sequential routing strategy and the extrusion optimization.

  ○

  Per-Net Cost: The maximum number of generations is $G=1000$, though the convergence mechanism typically results in much earlier termination. The worst-case per-net complexity is $O(G·N·(D+B\left)\right)$.

  ○

  Extrusion Optimization: This stage reroutes a constant number of previous nets ($K\le 5)$.

  ○

  Total Algorithm Complexity: The overall time complexity is $O(L·G·N·(D+B\left)\right)$, which effectively scales with $O(L·(m+n\left)\right)$ for large-scale BGA layouts.

• Memory Footprint: The memory footprint of the GA-OER is dominated by three components:

  ○

  Graph Representation: Storing the $V$ nodes and $E$ edges in the adjacency list requires $O(V + E)$ space, where $V\approx 9 \mathrm{mn}$ due to the GA grid transformation.

  ○

  Population Storage: Each net’s population requires $O(N\cdot D)$ space.

  ○

  Resource Usage Map: This map tracks used edges and tile directions, scaling with $O(L\cdot D)$. The total memory usage scales linearly with the grid area $\left(O\right(m\cdot n\left)\right)$, ensuring that the algorithm can handle large-scale cases like Case 8 $(50\times 50 \mathrm{grid})$ within standard workstation memory limits.

7. Conclusions

This paper presented a genetic algorithm-based optimization framework for solving the ordered escape routing (OER) problem in high-density BGA printed circuit boards under strict non-crossing and single-capacity constraints. By formulating OER as a combinatorial optimization problem and explicitly embedding routing feasibility into the genetic encoding, fitness evaluation, and offspring validation processes, the proposed approach is capable of generating legal and high-quality escape routing solutions in a fully automated manner.

Comprehensive experiments were conducted on eight benchmark cases, where both the proposed GA-based method and the ILP-based reference method were evaluated under identical experimental conditions. Specifically, the same randomly generated initial node configurations were used for both methods, and fifty independent runs were performed for each benchmark. The reported results represent the average performance and corresponding standard deviations, ensuring a fair and unbiased comparison.

The experimental results demonstrate that the proposed GA-based approach consistently outperforms the ILP-based method across all benchmark cases. In every case, the proposed method achieves shorter total routing lengths while also requiring less computational time. The most significant improvement is observed in Case 7, where the total wire length is reduced by approximately 17.6% compared to the ILP-based approach. These results clearly indicate that the performance gains of the proposed method are inherent to the optimization strategy rather than dependent on favorable initialization.

Moreover, the successful routing of large-scale and high-density benchmarks, including the 50 × 50 grid with 130 nets, confirms the robustness and scalability of the proposed framework. As problem size and routing complexity increase, the GA-based approach maintains a stable execution time and effective optimization capability, whereas the ILP-based method exhibits a higher computational cost and reduced efficiency. This demonstrates the suitability of the proposed approach for complex and large-scale PCB escape routing scenarios.

Overall, this work shows that genetic algorithms, when carefully tailored with constraint-aware representations and validation mechanisms, can simultaneously improve routing quality and computational efficiency for ordered escape routing problems. The proposed framework provides an effective and scalable optimization engine for modern high-density PCB design. Future work will focus on extending the proposed approach to multi-layer escape routing, parallel evolutionary optimization, and the integration of additional electrical and manufacturing constraints.