Two-Winding Coupled-Inductor-Based DC–DC Converter with Two Synchronous Power Switches and Ultra-High Voltage-Gain Capability

Abstract

This article describes a non-isolated boost DC–DC configuration that uses a two-winding coupled inductor (CI) together with two synchronous power switches to acquire ultra-high voltage conversion at relatively low duty cycles. The proposed structure combines a quadratic gain stage with the coupled inductor to realize a substantial output voltage boost. The overall conversion ratio can be flexibly adjusted through two independent design factors: the duty cycle of the switches and the turns ratio of the coupled inductor providing additional degrees of freedom for optimization. The main merits of the converter are its very high voltage gain (VG), reduced voltage stress (VS) on the active switches, continuous input current, common ground between input and output, soft-switching operation for diodes D₃ and D₄, and the possibility of using a synchronized gate-drive scheme. The paper thoroughly examines the operating intervals, steady-state behavior, design procedure, and efficiency performance, and also develops a dynamic model for control-oriented analysis. To highlight its strengths, the proposed topology is systematically compared with several existing high-gain converters. Finally, experimental outcomes obtained from a 400-W laboratory prototype operating at 50 kHz confirm the feasibility and effectiveness of the proposed converter in achieving high voltage gain, reduced device voltage stress, and high efficiency under practical operating conditions.

1. Introduction

Over the last ten years, priorities across the global energy sector have increasingly centered on cutting greenhouse gas emissions and expanding the contribution of renewable resources to electricity production. As illustrated schematically in Figure 1, renewables are now broadly viewed as the leading pathway for phasing out conventional, fossil-fuel-based generation. Among these options, photovoltaic (PV) technology has become especially prominent because sunlight is abundant and widely accessible, solar power is sustainable over the long term, and PV systems generally impose a relatively small environmental burden [1].

From an engineering perspective, a major challenge is that photovoltaic arrays and fuel cells naturally produce low-magnitude DC voltages, which cannot be connected to the grid without additional conditioning. To address this mismatch, a high step-up DC–DC conversion stage is typically introduced. Such converters elevate the modest DC output of the renewable source to a level suitable for subsequent power processing and eventual grid integration [2,3,4]. As a result, they are a core element of contemporary renewable-energy systems, enabling cleaner electricity production and supporting worldwide efforts to curb air pollution, reduce environmental harm, and lessen the climate impacts linked to fossil fuel dependence [5,6].

To achieve high output voltages and step up the naturally low DC levels delivered by clean sources such as photovoltaic (PV) arrays, designers have incorporated a wide range of specialized step-up strategies into boost-type DC–DC converter structures [7,8,9]. Frequently adopted solutions include switched-capacitor (SC) and switched-inductor (SL) networks, active switched-inductor (A-SL) techniques, converter topologies employing coupled inductors (CIs), voltage-lift and voltage-multiplier (VM) principles, and both interleaved and multi-stage (cascaded) architectures [10,11,12,13]. In many reported designs, two or more of these concepts are also merged into hybrid forms to further increase voltage gain and enhance overall converter performance [14,15,16,17,18].

Within the family of high step-up converters created by blending the above techniques, quadratic topologies are particularly attractive because they can produce exceptionally high voltage conversion ratios [19,20,21,22,23,24]. This advantage stems from the appearance of the (1 − D)² term in the denominator of their VG expression. In [25], a quadratic step-up circuit that integrates switched-inductor and switched-capacitor networks is proposed, achieving a relatively high step-up ratio. However, since one of the capacitors is directly linked to the input source, the configuration draws a pulsating input current, which is an undesirable characteristic for many applications. In another topology reported in [26], switched-inductor and switched-capacitor cells are again combined, but this time two series-connected capacitors are employed to control the converter’s output voltage. This arrangement succeeds in lowering the VS on the capacitors and ensures a continuous input current. However, the main switch is still exposed to a voltage stress equal to the full output voltage. Although the converters proposed in [25,26] all exhibit quadratic voltage gain characteristics, the elevated VS on the switch contributes to significant conduction and switching losses. As a result, these configurations are not appropriate for applications requiring very high output voltages.

In [27], a family of quadratic configurations is presented that combines coupled inductors with voltage multiplier stages while aiming to reduce device voltage stress. Although these configurations can acquire a high step-up ratio, they are affected by considerable input current ripple, which constrains their applicability in DC microgrid environments. In [28], another quadratic topology based on a CI with two cascaded boosting stages is introduced to obtain large voltage gain; however, this structure incurs noticeable power losses in the input diodes and is characterized by a high input current.

A different quadratic architecture with low device voltage stress is designed in [29]. Although it achieves a high voltage step-up, the series connection between the coupled-inductor primary winding and the input DC source leads to pronounced ripple in the input current, which in turn places extra stress on the source. High-gain topologies with improved input-current ripple characteristics are presented in [30,31], where two- or three-winding CIs are integrated with voltage-multiplier cells. This approach offers additional design flexibility, allowing the conversion ratio to be tuned over a broad range. However, these converters still suffer from high voltage stress on the main switch and significant current stress in the input diodes.

References [32,33,34] propose quadratic converter designs that combine coupled inductors with switched-capacitor networks in order to obtain high voltage gains. A key limitation of these structures is the large capacitor peak currents, which can increase power dissipation and worsen electromagnetic interference. In [35], a quadratic impedance-source converter augmented with a CI is presented, providing strong step-up performance with a comparatively low component count. Even so, the semiconductor devices in this topology continue to experience considerable voltage stress.

In [21], a quadratic boost converter incorporating a SEPIC-like stage is proposed and examined. The converter achieves a high conversion ratio while keeping the input-current ripple small, which helps overcome issues commonly faced in DC microgrid environments. However, the additional passive parts—most notably the coupling capacitor—add resistive and reactive losses, which ultimately reduce efficiency.

Reference [36] introduces a quadratic topology featuring soft switching, a continuous input current, and reduced voltage stress on the semiconductor devices. While this approach successfully alleviates voltage-stress concerns, it relies on a comparatively high component count, particularly in magnetic components. This increases cost and reduces power density, making practical implementation less attractive.

Driven by the strengths and limitations of current high boost configuration designs, this article describes a novel quadratic ultra-high boost DC–DC topology tailored for renewable energy systems. The proposed configuration provides two independent degrees of freedom for adjusting the VG, namely the duty cycles of the power switches and the turns ratio of the CI, which gives the designer considerable flexibility. Unlike many conventional high-gain converters, the suggested configuration can achieve a substantial step-up ratio without being restricted to severe duty-cycle values, allowing the duty cycle to vary over the entire range from 0 to 1. Furthermore, it can deliver an ultra-high output voltage even at relatively small duty cycles, which helps reduce conduction losses. Another important advantage is the low VS on the MOSFETs, enabling the employment of low-voltage-rating switches with small on-state resistance, thereby minimizing conduction losses and enhancing overall efficiency. The topology also features a continuous input current with low ripple, which is highly favorable when interfacing with vulnerable renewable sources such as PV modules. In addition, the converter operates with two active power switches driven synchronously and maintains a common ground capability, simplifying system integration and control. Finally, the proposed structure ensures soft-switching operation for diodes D₃ and D₄, effectively reducing switching losses and mitigating electromagnetic interference.

2. Proposed Configuration and Operation Modes

The proposed quadratic topology depicted in Figure 2 illustrates the layout of the new converter. It incorporates an input inductor L, two active switches S₁ and S₂, five capacitors (C₁–C₅), five diodes (D₁–D₄ and D_O) and a CI composed of two windings: a primary winding N_P and a secondary winding N_S. The turns ratio of this CI is expressed as n = N_S/N_P, and the coupling coefficient is defined as k = L_m/(L_m + L_k). The configuration functions under continuous conduction mode (CCM), and its switching period can be separated into two operating intervals, illustrated in Figure 3. The corresponding key voltage and current waveforms of the circuit elements are shown in Figure 4.

First Mode: In this mode, both switches S₁ and S₂ are in the ON state, and diode D₄ conducts, while all other diodes remain reverse-biased. At t₀ = 0, diode D₃ turns off under zero-voltage and zero-current switching (ZVCS) conditions. The magnetizing inductance L_m is energized through the loop composed of C₂, L_m, S₂, C₁, and S₁, causing the magnetizing current i_Lm to increase linearly and simultaneously discharging capacitors C₁ and C₂. Concurrently, the input inductor L is energized via the path V_in–L–S₁, resulting in a linear rise of the inductor current i_L. In parallel, capacitor C₃ is charged and C₄ is discharged through the loop formed by C₄, D₄, C₃, S₂, C₁, and S₁, while capacitor C₅ releases energy through the path including C₄, C₅, and the output voltage. Throughout this interval, the voltages and currents in the structure obey Kirchhoff’s Voltage Law (KVL) and Kirchhoff’s Current Law (KCL).

$$V_1=V_{Lm}+V_{Lk}={\displaystyle \frac{V_{Lm}}{k}}$$

(1)

$$V_{Ns}=n{V}_{Lm}$$

(2)

$$V_{in}=V_L$$

(3)

$$V_{C1}=V_1-V_{C2}$$

(4)

$$V_{C3}=V_1-V_{C2}+V_{C4}$$

(5)

$$V_O=V_{C5}+V_{C4}$$

(6)

$$V_{C5}=V_{C1}-V_{C3}+V_O$$

(7)

$$V_{C2}=V_1-V_{C3}+V_O-V_{C5}$$

(8)

$$I_{Np}=n{I}_{Ns}$$

(9)

$$I_L=I_{in}$$

(10)

$$I_{C1}=I_L-I_{S1}$$

(11)

$$I_{C2}=-I_{Lm}-I_{Np}$$

(12)

$$I_{S2}=-I_{C1}$$

(13)

$$I_{C3}=-I_{Lm}-I_{Np}+I_{S2}$$

(14)

$$I_{D4}=I_{C3}-I_{Ns}$$

(15)

$$I_{C4}=-I_{D4}-I_O$$

(16)

$$I_{C5}=-I_O$$

(17)

$$I_{in}=I_{C4}+I_O-I_{Lm}-I_{Np}+I_{S1}$$

(18)

$$I_{S1}=I_{D4}-I_{C2}+I_{in}$$

(19)

Second Mode: In this operating interval, both power switches are in the OFF state, which causes diodes D₁, D₂, D₃, and D_O to conduct, while diode D₄ is turned off under ZVCS conditions. The magnetizing inductance L_m and the input inductor L release their stored energy through the path V_in → L → D₁ → L_m → C₃ → N_S → D_O → C₅ → C₄. As a result, the currents in L_m and L decrease gradually, capacitor C₃ is discharged, and capacitors C₄ and C₅ are charged along this route. Meanwhile, capacitor C₁ is replenished via the loop V_in → L → C₁ → D₂, and capacitor C₂ is energized along the path V_in → L → D₁ → C₂. The mathematical relations governing this interval can be written as follows.

$$V_{C1}=V_{in}-V_L$$

(20)

$$V_{C3}=-V_{C2}+V_{Ns}+V_1+V_O$$

(21)

$$V_{C2}=V_1+V_{C4}$$

(22)

$$V_{C3}=V_{Ns}+V_{C5}$$

(23)

$$I_{C1}=I_L-I_{D2}$$

(24)

$$I_{C2}=-I_{Lm}-I_{Np}+I_{D1}$$

(25)

$$I_{D2}=I_{C1}$$

(26)

$$I_{C3}=-I_{Lm}-I_{Np}+I_{D3}$$

(27)

$$I_{C3}=I_{Ns}$$

(28)

$$I_{C4}=I_{D3}+I_{Do}-I_O$$

(29)

$$I_{C5}=I_{Do}-I_O$$

(30)

$$I_{in}=I_{C4}+I_O-I_{Lm}-I_{Np}+I_{D1}+I_{D2}$$

(31)

$$I_{D2}=-I_{D3}-I_{Do}-I_{C2}+I_{in}$$

(32)

The volt–second equilibrium condition for inductor L and CI can be formulated as follows:

$${〈V_L〉}_{Ts}=0$$

(33)

$${〈V_{Lm}〉}_{Ts}=0$$

(34)

$${〈V_1〉}_{Ts}=0$$

(35)

The steady-state voltages of the capacitors and the output voltage are derived by applying the volt–second balance principle to the input inductor and the coupled inductor under continuous conduction mode. In steady state, the voltages of capacitors C₁ and C₂ are equal, and their value is obtained from the average voltage of the input inductor L using the inductor voltage expressions defined in Equations (3) and (20). By enforcing the zero average voltage condition over one switching period, the voltage of C₁ (and consequently C₂) is determined. The voltage of capacitor C₄ is then derived by applying volt–second balance to the magnetizing inductance L_m using the primary–side voltage relations given in Equations (4) and (22), while noting that the primary voltage V₁ is directly related to the magnetizing inductance voltage according to Equation (1). Based on the obtained values of C₁, C₂, and C₄, the voltage of capacitor C₃ is determined from the circuit relations in the first switching interval using Equations (5) and (22). The voltage of capacitor C₅ is obtained from the circuit relations in the second switching interval using Equations (5) and (23), which include the contribution of the coupled-inductor secondary voltage.

$$V_{C1}=V_{C2}={\displaystyle \frac{V_{in}}{1-D}}$$

(36)

$$V_{C3}={\displaystyle \frac{2V_{in}}{{(1-D)}^2}}$$

(37)

$$V_{C4}={\displaystyle \frac{V_{in}(1+D)}{{(1-D)}^2}}$$

(38)

$$V_{C5}={\displaystyle \frac{2V_{in}(Dkn+1)}{{(1-D)}^2}}$$

(39)

Finally, once the voltages of capacitors C₄ and C₅ are known, the output voltage is obtained from their series combination according to Equation (6).

$$V_O={\displaystyle \frac{V_{in}(2Dkn+3+D)}{{(1-D)}^2}}$$

(40)

Ignoring the influence of the coupling coefficient of CI (especially for k = 1), the VG can be written as:

$$G={\displaystyle \frac{V_O}{V_{in}}}={\displaystyle \frac{2Dn+3+D}{{(1-D)}^2}}$$

(41)

A three-dimensional surface of the configuration gain is displayed in Figure 5. This plot shows that, for appropriate selections of D and n, the proposed structure can deliver very large step-up ratios, with the voltage gain varying in a quadratic manner.

The VS imposed on the semiconductors in the proposed configuration are determined as follows:

$$V_{S1}={\displaystyle \frac{V_{in}}{1-D}}$$

(42)

$$V_{S2}={\displaystyle \frac{V_{in}(1+D)}{{(1-D)}^2}}$$

(43)

$$V_{D1}=V_{D2}={\displaystyle \frac{V_{in}}{1-D}}$$

(44)

$$V_{D3}=V_{D4}={\displaystyle \frac{2V_{in}}{{(1-D)}^2}}$$

(45)

$$V_{Do}={\displaystyle \frac{2V_{in}(kn+1)}{{(1-D)}^2}}$$

(46)

The semiconductor device currents in each switching interval can be described by the following expressions:

$$I_{S1-Mode1}={\displaystyle \frac{I_O(3D+Dkn+D^{2}kn+1)}{D{(1-D)}^2}}$$

(47)

$$I_{S2-Mode1}={\displaystyle \frac{I_O(D+Dkn+1)}{D(1-D)}}$$

(48)

$$I_{D1-Mode2}={\displaystyle \frac{I_O(Dkn+2)}{{(1-D)}^2}}$$

(49)

$$I_{D2-Mode2}={\displaystyle \frac{I_O(D+Dkn+1)}{{(1-D)}^2}}$$

(50)

$$I_{D3-Mode2}=I_{Do-Mode2}={\displaystyle \frac{I_O}{1-D}}$$

(51)

$$I_{D4-Mode1}={\displaystyle \frac{I_O}{D}}$$

(52)

The analytical expressions used to evaluate the currents flowing through the input inductor L, the magnetizing inductance L_m, and the primary and secondary windings of the CI are presented below:

$$I_L=I_{in}={\displaystyle \frac{I_O(D+2Dkn+3)}{{(1-D)}^2}}$$

(53)

$$I_{Lm}={\displaystyle \frac{I_O(kn+2)}{1-D}}$$

(54)

$$I_{Np-Mode2}=-{\displaystyle \frac{I_{O}kn}{1-D}}$$

(55)

$$I_{Ns-Mode2}=-{\displaystyle \frac{I_O}{1-D}}$$

(56)

Using the equivalent circuits for each functioning mode and enforcing the ampere–second balance condition, the capacitor current relationships are obtained as follows:

$$I_{C1-Mode1}=-{\displaystyle \frac{I_O(D+Dkn+1)}{D(1-D)}}$$

(57)

$$I_{C1-Mode2}={\displaystyle \frac{I_O(D+Dkn+1)}{{(1-D)}^2}}$$

(58)

$$I_{C2-Mode1}=-{\displaystyle \frac{I_O(kn+2)}{(1-D)}}$$

(59)

$$I_{C2-Mode2}={\displaystyle \frac{D{I}_O(kn+2)}{{(1-D)}^2}}$$

(60)

$$I_{C3-Mode1}={\displaystyle \frac{I_O}{D}}$$

(61)

$$I_{C3-Mode2}=-{\displaystyle \frac{I_O}{1-D}}$$

(62)

$$I_{C4-Mode1}=-{\displaystyle \frac{I_O(1+D)}{D}}$$

(63)

$$I_{C4-Mode2}={\displaystyle \frac{I_O(1+D)}{(1-D)}}$$

(64)

$$I_{C5-Mode1}=-I_O$$

(65)

$$I_{C5-Mode2}={\displaystyle \frac{D{I}_O}{1-D}}$$

(66)

The mean current loading of the switches and the diodes is determined by the following expressions:

$$I_{S1,avg}={\displaystyle \frac{I_O(3D+Dkn+D^{2}kn+1)}{{(1-D)}^2}}$$

(67)

$$I_{S2,avg}={\displaystyle \frac{I_O(D+Dkn+1)}{(1-D)}}$$

(68)

$$I_{D1,avg}={\displaystyle \frac{I_O(Dkn+2)}{(1-D)}}$$

(69)

$$I_{D2,avg}={\displaystyle \frac{I_O(D+Dkn+1)}{(1-D)}}$$

(70)

$$I_{D3,avg}=I_{D4,avg}=I_{Do,avg}=I_O$$

(71)

To precisely evaluate power dissipation in the converter, it is crucial to estimate the root-mean-square (RMS) current of every device. The step-by-step derivation of the RMS currents for each element is given in (61)–(68) below.

$$I_{S1,RMS}={\displaystyle \frac{I_O(3D+Dkn+D^{2}kn+1)}{{(1-D)}^2\sqrt{D}}}$$

(72)

$$I_{S2,RMS}={\displaystyle \frac{I_O(D+Dkn+1)}{\sqrt{D}(1-D)}}$$

(73)

$$I_{D1,RMS}={\displaystyle \frac{I_O(Dkn+2)}{\sqrt{{(1-D)}^3}}}$$

(74)

$$I_{D2,RMS}={\displaystyle \frac{I_O(D+Dkn+1)}{\sqrt{{(1-D)}^3}}}$$

(75)

$$\left\{\begin{array}{l}{I}_{D3,RMS}=I_{Do,RMS}={\displaystyle \frac{I_O}{\sqrt{(1-D)}}}\\ I_{D4,RMS}={\displaystyle \frac{I_O}{\sqrt{D}}}\end{array}\right.$$

(76)

$$I_{C1,RMS}={\displaystyle \frac{I_O(D+Dkn+1)}{(1-D)\sqrt{D}}}+{\displaystyle \frac{I_O(D+Dkn+1)}{\sqrt{{(1-D)}^3}}}$$

(77)

$$I_{C2,RMS}={\displaystyle \frac{I_O(kn+2)\sqrt{D}}{(1-D)}}+{\displaystyle \frac{D{I}_O(kn+2)}{\sqrt{{(1-D)}^3}}}$$

(78)

$$I_{C3,RMS}={\displaystyle \frac{I_O}{\sqrt{D}}}+{\displaystyle \frac{I_O}{\sqrt{(1-D)}}}$$

(79)

$$I_{C4,RMS}={\displaystyle \frac{I_O(1+D)}{\sqrt{D}}}+{\displaystyle \frac{I_O(1+D)}{\sqrt{(1-D)}}}$$

(80)

$$I_{C5,RMS}=I_O\sqrt{D}+{\displaystyle \frac{D{I}_O}{\sqrt{(1-D)}}}$$

(81)

For the proposed topology to function in continuous conduction mode, the inductor current i_L must not fall to zero at any time. Accordingly, the minimum values of the inductor current i_L and the current ripple Δ_iL can be written as:

$$\mathsf{\Delta }{I}_L={\displaystyle \frac{V_{in}D}{L{f}_S}}$$

(82)

$$\left\{\begin{array}{l}{I}_{L,\min }=I_L-{\displaystyle \frac{\mathsf{\Delta }{I}_L}{2}}\\ I_{L,\max }=I_L+{\displaystyle \frac{\mathsf{\Delta }{I}_L}{2}}\end{array}\right.$$

(83)

The smallest inductance of L necessary to ensure operation in CCM can be represented as:

$$L\ge {\displaystyle \frac{D{(1-D)}^4{R}_O}{2{(2Dkn+D+3)}^2{f}_s}}$$

(84)

To guarantee correct operation, the instantaneous current flowing through the CI must not reach zero. Accordingly, the minimum current through CI and the ripple component Δ_iLm can be expressed as:

$$\mathsf{\Delta }{I}_{Lm}={\displaystyle \frac{2V_{in}Dk}{(1-D)L_m{f}_S}}$$

(85)

$$\left\{\begin{array}{l}{I}_{Lm,\min }=I_{Lm}-{\displaystyle \frac{\mathsf{\Delta }{I}_{Lm}}{2}}\\ I_{Lm,\max }=I_{Lm}+{\displaystyle \frac{\mathsf{\Delta }{I}_{Lm}}{2}}\end{array}\right.$$

(86)

The lowest inductance value of L_m that guarantees continuous conduction mode can be obtained using:

$$L_m\ge {\displaystyle \frac{kD{R}_O{(1-D)}^2}{2(kn+2)(2Dkn+D+3)f_s}}$$

(87)

As shown in Figure 6, the L_min(D) characteristic of the magnetizing inductor L_m lies above that of the input inductor L. This reveals that, under the same input voltage, switching frequency, and load conditions, the magnetizing branch requires a larger inductance value to remain in CCM. Consequently, for the parameter set adopted in this study, L_m transitions into discontinuous conduction mode (DCM) before L, which can be clearly observed in Figure 6. In addition to being continuous, the input current of the proposed converter exhibits a very low ripple at the rated operating point. For an average input current of approximately 22 A, the peak-to-peak ripple is about 0.5 A, which corresponds to an input current ripple ratio of nearly 2.27%. Such a low ripple level confirms the source-friendly nature of the proposed topology and makes it particularly suitable for PV and fuel-cell applications, where minimizing input current pulsation is essential to reduce source stress, improve operating-point stability, and enhance overall system reliability.

3. Efficiency Calculation

In this section, the study examines the conduction- and switching-related power losses of the proposed system in order to improve its overall performance. The evaluation accounts for the primary elements that contribute to energy dissipation, including the internal resistances of diodes (r_D), semiconductor switches (r_S), magnetic components such as inductors (r_Lm), and capacitors (r_C). The analysis also incorporates the forward voltage drops of both the diodes (V_FD) and the switching devices (V_FS) when determining the total loss profile. With these factors considered, the expressions for conduction losses in the switches and diodes are formulated as:

$$P_{Cond,S_1}={\displaystyle \frac{D{r}_{S_1}{{\mathrm{I}}_O}^2{\left(3D+Dn+D^{2}n+1\right)}^2}{{\left(1-D\right)}^4}}+{\displaystyle \frac{D{\mathrm{V}}_{{\mathrm{FS}}_1}{\mathrm{I}}_O\left(3D+Dn+D^{2}n+1\right)}{{\left(1-D\right)}^2}}$$

(88)

$$P_{Cond,S_2}={\displaystyle \frac{r_{S_2}{{\mathrm{I}}_O}^2{\left(D+Dn+1\right)}^2}{D{\left(1-D\right)}^2}}+{\displaystyle \frac{{\mathrm{V}}_{{\mathrm{FS}}_2}{\mathrm{I}}_O\left(D+Dn+1\right)}{1-D}}$$

(89)

$$\left\{\begin{array}{l}{P}_{Cond,D_1}={\displaystyle \frac{r_{D_1}{{\mathrm{I}}_O}^2{\left(D+Dn+1\right)}^2}{D}}\\ +{\displaystyle \frac{{\mathrm{V}}_{{\mathrm{FD}}_1}{\mathrm{I}}_O(D+Dn+1)}{1-D}}\end{array}\right.$$

(90)

$$\left\{\begin{array}{l}{P}_{Cond,D_2}={\displaystyle \frac{D^2{r}_{D_2}{{\mathrm{I}}_O}^2{\left(Dn+2\right)}^2}{{(1-D)}^3}}\\ +{\displaystyle \frac{{\mathrm{V}}_{{\mathrm{FD}}_2}{\mathrm{I}}_O(Dn+2)}{1-D}}\end{array}\right.$$

(91)

$$P_{Cond,D_3}={\mathrm{V}}_{{\mathrm{FD}}_3}{\mathrm{I}}_O+{\displaystyle \frac{{{\mathrm{I}}_O}^2{\mathrm{r}}_{{\mathrm{D}}_3}}{1-D}}$$

(92)

$$P_{Cond,D_4}={\mathrm{V}}_{{\mathrm{FD}}_4}{\mathrm{I}}_O+{\displaystyle \frac{{{\mathrm{I}}_O}^2{\mathrm{r}}_{{\mathrm{D}}_4}}{D}}$$

(93)

$$P_{Cond,D_O}={\mathrm{V}}_{{\mathrm{FD}}_O}{\mathrm{I}}_O+{\displaystyle \frac{{{\mathrm{I}}_O}^2{\mathrm{r}}_{{\mathrm{D}}_O}}{1-D}}$$

(94)

The switching energy dissipation of the power components, namely the semiconductor switches and diodes, is evaluated by applying the following assessment method:

$$P_{SW,S_1}={\displaystyle \frac{{\mathrm{I}}_O\times {\mathrm{V}}_{\mathrm{in}}\times f_s\times (t_{off}+t_{on})\times (3D+Dn+D^{2}n+1)}{6D\times {(1-D)}^3}}$$

(95)

$$P_{SW,S_2}={\displaystyle \frac{{\mathrm{I}}_O\times {\mathrm{V}}_{\mathrm{in}}\times f_s\times (t_{off}+t_{on})\times (1+D)\times (D+Dn+1)}{6D\times {(1-D)}^3}}$$

(96)

$$P_{SW,D_1}={\displaystyle \frac{I_{rr}\times V_{in}\times f_s\times t_b}{6\times (1-D)}}$$

(97)

$$P_{SW,D_2}={\displaystyle \frac{I_{rr}\times V_{in}\times f_s\times t_b}{6\times (1-D)}}$$

(98)

$$P_{SW,D_O}={\displaystyle \frac{I_{rr}\times V_{in}\times f_s\times t_b}{{(1-D)}^2}}$$

(99)

A comprehensive expression for the total power loss in both switches and diodes, incorporating contributions from conduction and switching mechanisms, can be written as:

$$P_{S,Tot}=P_{Cond,S_1}+P_{SW,S_1}+P_{Cond,S_2}+P_{SW,S_2}$$

(100)

$$P_{D,Tot}=P_{Cond,D_{1,2,O}}+P_{SW,D_{1,2,O}}$$

(101)

The conduction-related power dissipation for capacitors C₁ through C₅ is evaluated using the following expressions:

$$P_{Cond,C_1}=r_{C_1}{\left({\displaystyle \frac{{\mathrm{I}}_O(D+Dn+1)}{(1-D)\sqrt{D}}}+{\displaystyle \frac{{\mathrm{I}}_O(D+Dn+1)}{\sqrt{{(1-D)}^3}}}\right)}^2$$

(102)

$$P_{Cond,C_2}=r_{C_2}{\left({\displaystyle \frac{{\mathrm{I}}_O(kn+2)\sqrt{D}}{(1-D)}}+{\displaystyle \frac{{\mathrm{DI}}_O(kn+2)}{\sqrt{{(1-D)}^3}}}\right)}^2$$

(103)

$$P_{Cond,C_3}=r_{C_3}{\left({\displaystyle \frac{{\mathrm{I}}_O}{\sqrt{1-D}}}+{\displaystyle \frac{{\mathrm{I}}_O}{\sqrt{D}}}\right)}^2$$

(104)

$$P_{Cond,C_4}=r_{C_4}{\left({\displaystyle \frac{{\mathrm{I}}_O(1+D)}{\sqrt{1-D}}}+{\displaystyle \frac{{\mathrm{I}}_O(1+D)}{\sqrt{D}}}\right)}^2$$

(105)

$$P_{Cond,C_5}=r_{C_5}{\left(\sqrt{D}{\mathrm{I}}_O+{\displaystyle \frac{{\mathrm{DI}}_O}{\sqrt{1-D}}}\right)}^2$$

(106)

The overall power loss attributed to the capacitors is expressed through the following formulation:

$$P_{C,Tot}=P_{Cond,C_1}+P_{Cond,C_2}+P_{Cond,C_3}+P_{Cond,C_4}+P_{Cond,C_5}$$

(107)

The formulas employed to quantify the conduction losses of the magnetizing inductance L_m and the filter inductor L are presented below:

$$P_{Cond,Lm}=r_{Lm}{I}_{Lm}^2={\displaystyle \frac{{\mathrm{Io}}^2{r}_{Lm}{(n+2)}^2}{{(1-D)}^2}}$$

(108)

$$P_{Cond,L}=r_L{I}_L^2={\displaystyle \frac{{\mathrm{Io}}^2{r}_L{(D+2Dkn+3)}^2}{{(1-D)}^4}}$$

(109)

The power dissipation associated with the inductive components is characterized by the following expressions:

$$P_C=k{f}_s^{\alpha }{B}_m^{\beta }$$

(110)

The inductor core loss, represented as PC, is typically provided in units of W/kg. The coefficients α, β, and k, known as the Steinmetz parameters, are usually designated by core fabricators for different magnetic materials. For ferrite cores, the value of α commonly lies between 1 and 2 (1 ≤ α ≤ 2). Using Faraday’s law, the corresponding loss expression can be written as:

$$V_L=N{\displaystyle \frac{d\phi (t)}{dt}}=N{A}_c{\displaystyle \frac{dB(t)}{dt}}$$

(111)

Core manufacturers generally supply the cross-sectional area Ac for their magnetic components. With this parameter available, the peak flux variation ΔB in the inductors can be specified using the following relationship:

$$\mathsf{\Delta }B={\displaystyle \frac{1}{N{A}_c}}{\displaystyle \underset{0}{\overset{D{T}_s}{\int }}{V}_{in}dt}$$

(112)

The core-related losses of the inductors are expressed as P_Core = P × M, where M is the mass of the magnetic core material. Since the peak flux density is given by B_m = ΔB/2, the resulting core loss can be calculated using the following equation:

$$P_{Core}=k{f}_s^{\alpha }{\left({\displaystyle \frac{\mathsf{\Delta }B}{2}}\right)}^{\beta }M$$

(113)

An ETD 49/25/16 magnetic core is chosen for the inductors, with the associated Steinmetz coefficients given as k = 4.124 × 10⁻⁵, α = 1.72, and β = 2.76. Using these parameters, the total power loss for the high boost structure can be determined from the following expression:

$$P_{Loss}=P_{S,Tot}+P_{D,Tot}+P_{Cond,Lm}+P_{Cond,L}+P_{Cores}+P_{C,Tot}$$

(114)

The efficiency of the suggested topology, denoted by η, is specified according to the following expression:

$$\eta ={\displaystyle \frac{P_{Out}}{P_{Out}+P_{Loss}}}$$

(115)

Using the formulations provided in Equations (88)–(115), the analytical efficiency of the suggested design is derived. Figure 7 compares the predicted efficiency with the experimentally measured values across varying output power levels. A detailed distribution of individual component losses is shown in Figure 8, where it is evident that switch S₁ incurs the greatest portion of the losses, while capacitor C₅ contributes the least. Figure 9 further presents the calculated loss distribution among the two switches, five diodes, five capacitors, and two inductors, revealing that the semiconductor elements (switches and diodes) are responsible for the majority of the total dissipation, approximately 82.44%, with the passive components playing a substantially smaller role. In Figure 10, losses are categorized into conduction losses of switches, diodes, capacitors, and inductors; switching losses of switches and diodes; and magnetic core losses. The analysis indicates that switching losses are relatively minor compared with conduction and core losses.

4. Key Parameter Design Guidance

The capacitor values are computed by analyzing the average currents flowing through each capacitor across all switching intervals, while also incorporating the corresponding capacitor voltages, duty ratio, admissible voltage ripple x_C%, and the selected switching frequency of 50 kHz. According to these criteria, the minimum capacitance requirements for C₁ through C₅ can be derived as follows:

$$C_1\ge {\displaystyle \frac{I_O\times (D+Dkn+1)}{f_s\times V_{in}\times x_{C1}\%}}$$

(116)

$$C_2\ge {\displaystyle \frac{D\times I_O\times (kn+2)}{f_s\times V_{in}\times x_{C2}\%}}$$

(117)

$$C_3\ge {\displaystyle \frac{I_O\times {(1-D)}^2}{f_s\times 2V_{in}\times x_{C3}\%}}$$

(118)

$$C_4\ge {\displaystyle \frac{I_O\times {(1-D)}^2}{f_s\times V_{in}\times x_{C4}\%}}$$

(119)

$$C_5\ge {\displaystyle \frac{D\times I_O\times {(1-D)}^2}{f_s\times 2V_{in}\times (Dkn+1)\times x_{C5}\%}}$$

(120)

The design of inductor L and the magnetizing inductance L_m is governed by multiple considerations, such as their respective average currents, the voltage stresses experienced throughout all modes, the duty cycle, the permissible current ripple levels x_L% and x_Lm%, and the chosen switching frequency. Using these factors, the minimum inductance values essential for L and L_m can be expressed as follows:

$$L\ge {\displaystyle \frac{V_{in}\times D\times {(1-D)}^2}{f_s\times \mathrm{Io}\times \left(D+2Dkn+3\right)\times x_L\%}}$$

(121)

$$L_m\ge {\displaystyle \frac{2V_{in}\times k\times D}{f_s\times \mathrm{Io}\times \left(kn+2\right)\times x_{Lm}\%}}$$

(122)

5. Small Signal Modeling

In this section, the evaluation is executed under the presumption that all semiconductor devices, inductors, and capacitors operate ideally. To correctly isolate the state variables for each switching mode, non-idealities are incorporated by representing the inductors with series resistances r_L and the capacitors with series resistances r_C. The state-space averaging technique is then utilized to derive both the averaged and small-signal models. This procedure requires formulating the system dynamics for each mode and computing their weighted average over one switching cycle, derived from each interval. For the two switching submodes, the corresponding system equations are obtained using Equation (123), with Z = 1 and Z = 2.

$$\left[\begin{array}{c}{\displaystyle \frac{d{i}_L}{dt}}\\ {\displaystyle \frac{d{i}_{Lm}}{dt}}\\ {\displaystyle \frac{d{v}_{C_1}}{dt}}\\ {\displaystyle \frac{d{v}_{C_2}}{dt}}\\ {\displaystyle \frac{d{v}_{C_3}}{dt}}\\ {\displaystyle \frac{d{v}_{C_4}}{dt}}\\ {\displaystyle \frac{d{v}_{C_5}}{dt}}\end{array}\right]=[A_Z]\left[\begin{array}{c}{i}_L\\ i_{Lm}\\ v_{C_1}\\ v_{C_2}\\ v_{C_3}\\ v_{C_4}\\ v_{C_5}\end{array}\right]+[B_Z]v_{in}$$

(123)

The control method employed for the proposed configuration utilizes a pole-placement approach, relying on the small-signal model obtained from the state-space averaged representation. In this framework, each state variable and control input is separated into two components: a steady-state term $\overline{X},\overline{D}$ and a disturbance or dynamic term $\tilde{x},\tilde{d}$.

$$\left\{\begin{array}{l}X=\overline{X}+\tilde{x}\\ D=\overline{D}+\tilde{d}\end{array}\right.$$

(124)

Following this procedure to arrive at the state-space averaged representation while ignoring second-order perturbation terms produces the small-signal model corresponding to the proposed structure.

$$\left\{\begin{array}{l}\dot{\tilde{x}}=A\tilde{x}+B\tilde{u}\\ y=C\tilde{x}+D\tilde{u}\end{array}\right.$$

(125)

The state variables $\tilde{x}$, control inputs $\tilde{u}$, and output quantities y are defined as follows:

$${\tilde{x}}^T=\left[\begin{array}{ccccccc}{\tilde{i}}_L& {\tilde{i}}_{Lm}& {\tilde{v}}_{C1}& {\tilde{v}}_{C2}& {\tilde{v}}_{C3}& {\tilde{v}}_{C4}& {\tilde{v}}_{C5}\end{array}\right]$$

(126)

$$\tilde{u}=\left[\tilde{d}\right]$$

(127)

$$y^T=\left[I_{Lm}\right]$$

(128)

Using the pole-placement technique, the closed-loop poles can be situated at any desired locations, as long as the system retains full state control capability. The control capability matrix for the proposed circuit is given by:

$${\mathsf{\Phi }}_C=\left[B⋮AB⋮A^{2}B⋮\cdots ⋮A^{n-1}B\right]$$

(129)

If the controllability matrix ${\mathsf{\Phi }}_C$ has a rank of 7, which corresponds to the count of state variables $\tilde{x}$, the system is considered fully regulatable. In this scenario, two extra integral states are introduced as follows:

$$\dot{q}(t)=r(t)-y(t)=r(t)-{\tilde{i}}_{Lm}(t)$$

(130)

With the integral states included, the state-space representation and the corresponding output formulas are reformulated as follows:

$$\begin{array}{l}\left[\begin{array}{c}\dot{\tilde{x}}(t)\\ \cdots \\ \dot{q}(t)\end{array}\right]=\left[\begin{array}{ccc}A& ⋮& 0\\ \cdots & ⋮& \cdots \\ -C& ⋮& 0\end{array}\right]\left[\begin{array}{c}\tilde{x}(t)\\ \cdots \\ q(t)\end{array}\right]+\left[\begin{array}{c}B\\ \cdots \\ 0\end{array}\right]\tilde{u}(t)+\left[\begin{array}{c}0\\ \cdots \\ I\end{array}\right]r(t)\\ y(t)=\left[\begin{array}{ccc}C& ⋮& 0\end{array}\right]\left[\begin{array}{c}\tilde{x}(t)\\ \cdots \\ q(t)\end{array}\right]\end{array}$$

(131)

In this representation, r(t) denotes the reference input vector, which is defined as follows:

$$r(t)={\left[I_{Lm,ref}\right]}^T$$

(132)

Based on Equation (131), the updated forms of matrices $\overline{A}$ and $\overline{B}$ are expressed as follows:

$$\overline{A}=\left[\begin{array}{ccc}A& ⋮& 0\\ \cdots & ⋮& \cdots \\ -C& ⋮& 0\end{array}\right],\overline{B}=\left[\begin{array}{c}B\\ \cdots \\ 0\end{array}\right]$$

(133)

For the system described in Equation (131), the corresponding controllability matrix is given by:

$${\overline{\mathsf{\Phi }}}_C=\left[\begin{array}{ccc}B& ⋮& A{\mathsf{\Phi }}_C\\ \cdots & ⋮& \cdots \\ 0& ⋮& -C{\mathsf{\Phi }}_C\end{array}\right]=\underset{M}{\underbrace{\left[\begin{array}{ccc}B& ⋮& A\\ \cdots & ⋮& \cdots \\ 0& ⋮& -C\end{array}\right]}}\left[\begin{array}{ccc}I& ⋮& 0\\ \cdots & ⋮& \cdots \\ 0& ⋮& {\mathsf{\Phi }}_C\end{array}\right]$$

(134)

When ${\mathsf{\Phi }}_C$ is full rank, the system in Equation (131) is entirely regulatable provided that the controllability matrix M has rank n + m, where n designates the count of state variables $\tilde{x}$ and m represents the count of outputs y. Under these conditions, the gain matrix K is obtained using:

$$\tilde{u}(t)=-K\left[\begin{array}{c}\tilde{x}(t)\\ \cdots \\ q(t)\end{array}\right]=-\left[\begin{array}{ccc}{K}_x& ⋮& K_q\end{array}\right]\left[\begin{array}{c}\tilde{x}(t)\\ \cdots \\ q(t)\end{array}\right]$$

(135)

The feedback gain matrices K_x and K_q are expressed as follows:

$$\begin{array}{l}{K}_x=\left[\begin{array}{ccccccc}{K}_{11}& K_{12}& K_{13}& K_{14}& K_{15}& K_{16}& K_{17}\end{array}\right]\\ K_q=\left[K_{12}^{\prime }\right]\end{array}$$

(136)

By merging Equation (135) with Equation (131), the emerging equation becomes:

$$\begin{array}{l}\left[\begin{array}{c}\dot{\tilde{x}}(t)\\ \cdots \\ \dot{q}(t)\end{array}\right]=\left[\begin{array}{ccc}A-B{K}_x& ⋮& -B{K}_q\\ \cdots & ⋮& \cdots \\ -C& ⋮& 0\end{array}\right]\left[\begin{array}{c}\tilde{x}(t)\\ \cdots \\ q(t)\end{array}\right]+\left[\begin{array}{c}0\\ \cdots \\ I\end{array}\right]r(t)\\ y(t)=\left[\begin{array}{ccc}C& ⋮& 0\end{array}\right]\left[\begin{array}{c}\tilde{x}(t)\\ \cdots \\ q(t)\end{array}\right]\end{array}$$

(137)

Now we are faced with the problem of finding the controlling signal $\tilde{u}(t)$ via state feedback gain matrix K so that the closed-loop system eigenvalues are placed at the desired locations. There are several methods to determine the system controller matrix K = [K_x, K_q]. The control systems toolbox of the MATLAB software provides a useful pole-placement function, which inputs the system (137) and the desired eigenvalues locations to find the state feedback gain matrixes.

To stabilize the system, the values of K_x and K_q are determined as follows:

$$\begin{array}{l}{K}_x=\left[\begin{array}{ccccccc}0.319& 0.563& 0.0237& 0.0860& 0.284& 0.0193& 0.329\end{array}\right]\\ K_q=\left[-34.491\right]\end{array}$$

(138)

By using MATLAB software, the pole and zero placements for $G_1(s)={\displaystyle \frac{I_{Lm}(s)}{d(s)}}$ Equation (139) can be expressed as:

$$G_1(s)={\displaystyle \frac{2.678e08s^6+2.94e14s^5+7.91e16s^4+5.092e21s^3-2.654e25s^2-2.433e30s+8.221e33}{s^8+1.241e06s^7+2.54e12s^6+3.12e14s^5+2.51e21s^4+3.161e26s^3+9.281e28s^2+1.57e30s+2.04e33}}$$

(139)

To acquire the specified Gain Margin (GM ≥ 10) and Phase Margin (60° ≤ PM ≤ 80°), a trial-and-error approach is implemented to adjust the sites of the closed-loop poles. Using this method, the Bode plot of the control method for the proposed converter is shown in Figure 11. As seen in Figure 11, the gain margin for the inductor L_m exceeds 10 (GM(i_Lm) > 10), and the phase margin for the closed-loop path of i_Lm is 70.5892, which is within the desired range. Figure 12 and Figure 13 present the block diagram of the pole-placement control method and the current regulation loop for the CI, respectively. The output voltage is sensed and compared with the reference to generate an error signal, which is processed by the controller (compensator) to produce the duty-ratio command. This duty command is then applied to the PWM generation block to drive the switches, while the feedback path closes the loop and ensures regulation against input and load variations. The diagram therefore clarifies the signal flow from reference, error computation, and controller output to PWM actuation and measured feedback.

6. Comparison Study

A comprehensive comparison was carried out to highlight the merits of the proposed design. The review covered 16 competing designs, including 4 from 2025, 8 from 2024, and 4 from 2023.

Table 1. Comparison between the proposed configuration and other designs.

Ref/PY *	Voltage Gain	Maximum Voltage Stress on Switches	Power (W)/Efficiency	No. of Components					Total Component Count/Common Ground
				S	D	C	L	CI
PC *	${\displaystyle \frac{2Dn+D+3}{{(1-D)}^2}}$	${\displaystyle \frac{V_O(1+D)}{2Dn+D+3}}$	400/95.14%	2	5	5	1	1	14/Yes
[8] 2025	${\displaystyle \frac{1+D}{{(1-D)}^2}}$	$V_O$	500/94.3%	2	3	3	2	0	10/No
[9] 2025	${\displaystyle \frac{(1+3D-2D^2)}{{(1-D)}^2}}$	${\displaystyle \frac{V_O}{1+3D-2D^2}}$	100/96%	2	3	4	3	0	12/No
[10] 2025	${\displaystyle \frac{n+1}{{(1-D)}^2}}$	${\displaystyle \frac{V_O}{n+1}}$	360/95.2%	1	5	5	0	2	13/ Yes
[11] 2025	${\displaystyle \frac{n+1}{{(1-D)}^2}}$	${\displaystyle \frac{V_O}{n+1}}$	400/95%	1	4	4	2	1	12/ Yes
[12] 2024	${\displaystyle \frac{2+D}{{(1-D)}^2}}$	${\displaystyle \frac{V_O}{2+D}}$	50/87%	1	6	6	3	0	16/ Yes
[13] 2024	${\displaystyle \frac{2D+n-1}{{(1-D)}^2}}$	${\displaystyle \frac{(1-D)V_o}{2D+n-1}}$	210/93.4%	2	4	4	1	1	12/Yes
[14] 2024	${\displaystyle \frac{3-D}{{(1-D)}^2}}$	${\displaystyle \frac{(1+2D-D^2)V_o}{3-D}}$	300/94.5%	1	6	4	3	0	14/Yes
[15] 2024	${\displaystyle \frac{3-2D}{{(1-D)}^2}}$	${\displaystyle \frac{(1-2D{(1-D)}^2)V_o}{3-2D}}$	300/93.6%	2	3	3	2	0	10/No
[16] 2024	${\displaystyle \frac{{(2-D)}^2}{{(1-D)}^2}}$	${\displaystyle \frac{V_o}{{(2-D)}^2}}$	400/93.3%	2	4	4	2	0	12/No
[17] 2024	${\displaystyle \frac{D(2-D)}{{(1-D)}^2}}$	${\displaystyle \frac{V_O}{D(2-D)}}$	72/95%	2	2	3	3	0	10/ Yes
[18] 2024	${\displaystyle \frac{2D}{{(1-D)}^2}}$	${\displaystyle \frac{(1+D)V_O}{2D}}$	60/97%	2	3	4	3	0	12/ No
[19] 2024	${\displaystyle \frac{1+D}{{(1-D)}^2}}$	${\displaystyle \frac{V_O}{1+D}}$	100/94%	1	4	4	3	0	12/ Yes
[20] 2023	${\displaystyle \frac{1+2D-2D^2}{{(1-D)}^2}}$	${\displaystyle \frac{V_o}{1+2D-2D^2}}$	200/90%	1	5	6	4	0	16/Yes
[21] 2023	${\displaystyle \frac{n-1+nD}{{(1-D)}^2}}$	${\displaystyle \frac{(n-1)V_o}{n-1+nD}}$	100/93%	1	4	4	2	1	12/Yes
[22] 2023	${\displaystyle \frac{3-2D}{{(1-D)}^2}}$	${\displaystyle \frac{(2-D)V_o}{3-2D}}$	400/95.1%	1	5	4	1	1	12/Yes
[23] 2023	${\displaystyle \frac{2}{{(1-D)}^2}}$	${\displaystyle \frac{V_o}{2}}$	42/93.4%	1	5	4	0	2	12/Yes

PY *: Published Year; PC *: Proposed Converter.

reports a detailed comparison of features between the proposed topology and these alternatives, evaluating factors such as VG, peak switch VS, rated power, efficiency, device count, and whether a common ground is supported. The designs referenced in this comparison are taken from studies cited in [8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23].

Given that this work focuses on high step-up performance, voltage gain is the primary metric used for evaluation. Using the data from Table 1, Figure 14 plots the relationship between gain and duty cycle for all the boost structures reviewed. The results indicate that the proposed configuration provides the highest VG in contrast to the other designs listed in Table 1.

Switch voltage ratings are shown in the second column of Table 1, with their variation across duty cycles illustrated in Figure 15. For most operating points, the proposed circuit maintains excellent control over peak switch stress compared to other topologies. The only exception is found in the design from [13]: above a 50% duty cycle, its maximum switch stress is lower than that of the proposed circuit, but below 50%, the proposed configuration exhibits the lowest stress across all designs. Notably, operating at duty cycles under 50% generally improves converter behavior and reduces losses due to the smaller duty cycle. Another merit of the suggested design is that the switches experience lower voltage levels, allowing for the use of a smaller inductor.

The third column of Table 1 presents key performance metrics, such as rated power and efficiency. The suggested design is rated for a 400 W output and achieves an efficiency of 95.14%, as verified in Figure 7. In contrast, most other designs in Table 1 have ratings below 400 W. Even at the 400 W operating point, the proposed converter maintains 95.14% efficiency, surpassing the efficiency of many competing converters. Several of the compared designs operate at lower power levels but still exhibit lower efficiency than the suggested design.

The fourth column reports the component counts, with the final column summarizing the total device count and its breakdown. An ideal design minimizes the number of devices while maximizing voltage gain. To assess this trade-off, Figure 16 plots voltage gain against the total device count for all configurations. The data shows that the proposed circuit achieves the highest gain per device count, suggesting a cost advantage for similar performance levels. The last part of the comparison evaluates whether a common ground is supported between input and output, which is important as designs without a shared ground tend to be more susceptible to electromagnetic interference, potentially degrading performance. Unlike the designs in [8,9,15,16,18], the suggested design supports a common ground.

In conclusion, the comparative analysis highlights the strengths of the proposed converter, including its higher voltage gain, lower switch voltage stress, better gain per device count across duty cycles, and high efficiency at the 400 W level.

7. Experimental Results

To demonstrate the design’s performance and precision, a laboratory prototype rated at 400 W was constructed and implemented for a 19 V input and a 400 V output. Figure 17 shows images of the experimental prototype. The complete specifications of the prototype are listed in

Table 2. Hardware Component Parameters in the Prototype.

Parameters	Values
Rated power (Po)	400 W
Input voltage	19 V
Output voltage	400 V
Switching Frequency (fs)	50 kHz
Turns Ratio n (NS/NP)	2
Magnetizing Inductor (Lm)	300 µH
Leakage Inductor (Lk)	3 µH
Power Switch (S1)	IRF2807PbF
Power Switch (S2)	IRFP260N
Diodes (D1, D2, D3, D4)	MBR30300CT
Diode (DO)	Mur1560G
Cores type	ETD 49/25/16
Capacitors (C1, C2)	68 µF/100 V
Capacitors (C3, C4)	68 µF/200 V
Capacitor (C5)	100 µF/450 V

. A high-frequency current probe (MICSIG CP2100A, 800 kHz) and a voltage probe were used to capture and analyze the current and voltage waveforms across key components. Figure 18a shows an output of 400 V at 1 A. According to Equation (41), the predicted output is 418 V, which is in close agreement with the measured 400 V. Similarly, Equations (36) and (37) estimate 38 V across capacitors C₁ and C₂, and 152 V across C₃. The experimental results show 36 V across C₁ and C₂, and 148 V across C₃, as depicted in Figure 18b, confirming a strong match with theoretical predictions.

Equations (38) and (39) predict 114 V across C₄ and 304 V across C₅, while the experiments yield 109 V across C₄ and 298 V across C₅, as shown in Figure 18c, further supporting agreement with theory. In Figure 19a, the waveforms for switch S₁ reveal that, during the first mode, it only experiences a small fraction of the output voltage, around 9%, which aids in minimizing switching losses. The first switching subinterval for the power path through switch S₂ is demonstrated in Figure 19b. The experimental data from Figure 19a,b closely match the theoretical results derived from Equations (36), (37), (41), and (42), indicating a strong correlation between the model and experimental findings. Figure 19c and Figure 20a illustrate the voltage and current of diodes D₁ and D₂, with observed values aligning closely with the predictions from Equations (44), (49), and (50).

Additionally, the behaviors of diodes D₃ and D₄, depicted in Figure 20b,c, where ZVCS occurs during their turn-off, are consistent with theoretical predictions from Equations (45), (51), and (52), confirming a solid agreement between calculated and measured data. The behavior of diode D_O, shown in Figure 20d, also matches the theoretical expectations from Equations (46) and (51), reinforcing the consistency between the predicted and measured results.

8. Conclusions

This study presents a quadratic boost converter architecture designed specifically for renewable energy systems, with an emphasis on minimizing input current ripple. The proposed converter is compared to 16 other recent topologies (published between 2023 and 2025). At a 50% duty cycle and a turns ratio of 2, it demonstrates superior VG compared to all the designs in the comparison. Moreover, the converter ensures low device stress, with the maximum switch voltage limited to just 27.27% of the output voltage. The architecture provides two independent control parameters: the duty cycle and the turns ratio of the CI to regulate the VG. This design allows for ultra-high output voltages even at relatively low duty cycles, which helps reduce switch conduction losses and improve efficiency. Furthermore, the ZVCS (Zero-Voltage-Current Switching) turn-off behavior in diodes D₃ and D₄ helps lower losses. The prototype, rated at 400 W, achieves a remarkable efficiency of 95.14% at full load, surpassing most of its counterparts in the benchmark. The combination of high voltage gain, minimal switch stress, and dual-parameter control makes this converter an excellent choice for applications requiring significant voltage step-up in renewable energy systems.