Inter-Arm State-of-Charge Balancing Control Based on Arm Valley Voltage Adjustment in MMDTC-BESS

Abstract

This paper addresses a critical challenge in Modular Multilevel DC-link based T-type Converter (MMDTC) battery energy storage systems: the inherent power symmetry between upper and lower arms that prevents natural state-of-charge (SOC) balancing. A novel inter-arm SOC balancing control strategy is proposed that precisely modulates arm valley voltage characteristics—both amplitude and duration—to create controlled power differentials between arms. The theoretical analysis establishes a quantitative relationship between arm valley voltage width and inter-arm power difference, demonstrating that SOC balancing time is inversely proportional to arm valley voltage width. A key advantage of the proposed approach is its adaptive regulation capability: during steady-state operation, closed-loop feedback maintains arm valley voltage width within a narrow range through real-time SOC differential assessment, ensuring dynamic SOC equilibrium while minimizing impact on output power quality. The strategy works effectively in both charging and discharging modes, with comprehensive control logic for various operational scenarios. Finally, simulation and experimental results confirmed the effectiveness of the proposed control strategy.

1. Introduction

The global energy landscape is undergoing a profound transformation toward sustainability, with renewable energy installations experiencing unprecedented growth. In 2024, renewable sources accounted for over 80% of newly added global power generation capacity [1,2]. However, the inherent variability and intermittency of renewable energy sources present significant challenges to grid stability, manifesting as frequency fluctuations and voltage deviations [3,4]. Battery energy storage systems (BESS) have emerged as a pivotal solution to address these challenges, offering rapid power regulation, bidirectional energy flow, and high conversion efficiency [5,6]. Among various energy storage technologies, BESS stands out as particularly promising due to its mature technology, declining costs, and superior dynamic response characteristics [7,8].

The power conversion system (PCS) serves as the critical interface between battery arrays and the power grid, with its topology directly determining system performance, efficiency, and reliability [9]. As the BESS industry matures, there has been a notable evolution from conventional two- and three-level converter topologies toward advanced multilevel configurations.

Conventional two- and three-level converters face fundamental limitations in high-power applications. The voltage stress on semiconductor devices and constraints in battery pack configurations typically restrict single-unit capacity to approximately 500 kW. Furthermore, integration with medium- and high-voltage grids necessitates bulky line-frequency transformers, significantly increasing system cost and footprint [10,11]. In contrast, multilevel topologies such as Cascaded H-Bridge (CHB) and Modular Multilevel Converter (MMC), as shown in Figure 1a,b, offer transformative advantages through their modular architecture. These topologies enable direct grid connection at medium and high voltages without step-up transformers, while their distributed structure facilitates the segmentation of large battery arrays into independently manageable units—a critical requirement for safety and reliability in utility-scale BESS [12,13,14].

The Modular Multilevel DC-link based T-type Converter (MMDTC) represents an innovative topology that synergistically combines the advantages of both CHB and MMC [15,16]. As shown in Figure 1c, this topology features a unique configuration where a T-type converter interfaces with a modular multilevel DC-link, achieving superior performance with reduced semiconductor count and enhanced efficiency. Despite these advantages, the MMDTC faces a critical operational challenge common to all multilevel BESS: state-of-charge (SOC) balancing control. SOC imbalances not only accelerate battery degradation and reduce system efficiency but also compromise power quality and operational reliability. Research indicates that effective SOC management can extend battery lifetime by up to 30% while maintaining optimal system performance [17,18].

The SOC imbalance phenomenon in multilevel BESS exhibits hierarchical complexity, as illustrated in Figure 2. At the fundamental level, battery cell-to-cell variations arise from manufacturing tolerances, working condition, and control condition [19,20]. These microscopic imbalances propagate through the system hierarchy, manifesting as phase-level, arm-level, and submodule-level disparities. The specific imbalance patterns are topology-dependent: CHB systems primarily experience inter-phase and inter-submodule imbalances; MMC systems exhibit three-dimensional imbalances across phases, arms, and submodules; while MMDTC, due to its three-phase common DC-link configuration, predominantly faces inter-arm and inter-submodule imbalances.

Existing literature provides well-established solutions for submodule-level SOC balancing through modulation refinement and sorting algorithms, successfully demonstrated in both CHB and MMC applications [21,22,23,24]. These methods remain theoretically applicable to MMDTC systems. However, inter-arm SOC balancing presents unique challenges that existing solutions cannot adequately address.

In MMC systems, inter-arm balance is typically achieved through circulating current injection, DC bias adjustment, or power redistribution strategies [25,26,27]. However, these approaches fundamentally rely on multi-phase circulating current paths that are absent in the MMDTC’s single arm-pair configuration. Similarly, CHB systems employ zero-sequence voltage or negative-sequence current injection for inter-phase balancing [28,29,30], but the MMDTC’s line voltage output configuration inherently suppresses zero-sequence components, rendering these methods ineffective.

This fundamental incompatibility between existing balancing strategies and the MMDTC topology creates a critical research gap. The unique structural characteristics of MMDTC—combining a three-phase common DC-link with a T-type output stage—necessitate the development of novel control strategies specifically tailored to its architecture. Therefore, this paper addresses this gap by proposing an innovative inter-arm SOC balancing strategy based on arm valley voltage adjustment, providing both theoretical foundation and practical implementation for MMDTC-BESS applications.

The remainder of this paper is organized as follows: Section 2 presents a detailed description of the MMDTC-BESS topology and operating principles, analyzing the inherent power balance characteristics between arms and their impact on SOC balancing. Section 3 proposes the inter-arm SOC balancing control strategy based on arm valley voltage adjustment, establishes the quantitative relationship model between arm valley voltage width and inter-arm power difference, and analyzes the impact of this strategy on output waveform quality. Section 4 presents the simulation and experimental results. Finally, Section 5 summarizes the main contributions and conclusions of this research.

2. MMDTC-BESS Topology and Operating Principles

Figure 3 illustrates the topology of the MMDTC-BESS, which consists of a modular multilevel DC-link and a T-type structure. The DC-link comprises both upper and lower arms, with each arm constructed by cascading N half-bridge submodules and integrating battery units within these submodules. The T-type structure employs four high voltage switches per phase, formed by series-connected IGBTs or IGCTs. The DC side of the T-type structure is connected to the modular multilevel DC-link, collectively forming the complete MMDTC-BESS.

The output phase voltages of the MMDTC-BESS are defined as follows:

$$\left\{\begin{array}{l}{u}_{\mathrm{ao}}=V\sin (\mathsf{\omega }t+{\displaystyle \frac{\mathsf{\pi }}{6}})\\ u_{\mathrm{bo}}=V\sin (\mathsf{\omega }t-{\displaystyle \frac{\mathsf{\pi }}{2}})\\ u_{\mathrm{co}}=V\sin (\mathsf{\omega }t+{\displaystyle \frac{5\mathsf{\pi }}{6}})\end{array}\right.$$

(1)

where V and ω are the amplitude of the phase voltage and the angular frequency, respectively.

Moreover, the expression for the output line voltages of the MMDTC-BESS can be derived as follows:

$$\left\{\begin{array}{l}{u}_{\mathrm{ab}}=\sqrt{3}V\sin (\mathsf{\omega }t+{\displaystyle \frac{\mathsf{\pi }}{3}})\\ u_{\mathrm{bc}}=\sqrt{3}V\sin (\mathsf{\omega }t-{\displaystyle \frac{\mathsf{\pi }}{3}})\\ u_{\mathrm{ca}}=\sqrt{3}V\sin (\mathsf{\omega }t+\mathsf{\pi })\end{array}\right.$$

(2)

The relationship between the upper and lower arm voltages and the line voltages is depicted in Figure 4. Each phase of the T-type structure contains three switches: S_ku, S_kn, and S_kl (where k = a, b, c). At any given moment for each phase, only one switch is in the ON state while the other two remain in the OFF state. Taking phase A as an example, the switching state S_a is a function of {S_au, S_an, S_al}: when {S_au, S_an, S_al} = {1, 0, 0}, S_a = 1; when {S_au, S_an, S_al} = {0, 1, 0}, S_a = 0; when {S_au, S_an, S_al} = {0, 0, 1}, S_a = −1. Furthermore, {S_a, S_b, S_c} represents the switching states of the three phases in the T-type structure. Based on these switching states, mathematical expressions for the arm voltages can be derived as follows:

$$u_{\mathrm{UN}}=\left\{\begin{array}{l}\sqrt{3}V\sin \left(\theta \right),\theta \in [0,{\displaystyle \frac{\mathsf{\pi }}{3}})\\ \sqrt{3}V\sin (\theta +{\displaystyle \frac{\pi }{3}}),\theta \in [{\displaystyle \frac{\mathsf{\pi }}{3}},{\displaystyle \frac{2\mathsf{\pi }}{3}}]\end{array}\right.$$

(3)

$$u_{\mathrm{NL}}=\left\{\begin{array}{l}-\sqrt{3}V\sin (\theta -{\displaystyle \frac{\mathsf{\pi }}{3}}), \theta \in [0,{\displaystyle \frac{\mathsf{\pi }}{3}})\\ \sqrt{3}V\sin (\theta -{\displaystyle \frac{\mathsf{\pi }}{3}}),\theta \in [{\displaystyle \frac{\mathsf{\pi }}{3}},{\displaystyle \frac{2\mathsf{\pi }}{3}}]\end{array}\right.$$

(4)

where $\theta =\mathsf{\omega }t-{\displaystyle \frac{2\mathsf{\pi }}{3}}floor\left(\mathsf{\omega }t/\left({\displaystyle \frac{2\mathsf{\pi }}{3}}\right)\right)$, floor (x) represents the floor function.

The three-phase currents of the MMDTC-BESS are defined as follows:

$$\left\{\begin{array}{l}{i}_{\mathrm{a}}=I\sin (\mathsf{\omega }t+{\displaystyle \frac{\mathsf{\pi }}{6}})\\ i_{\mathrm{b}}=I\sin (\mathsf{\omega }t-{\displaystyle \frac{\mathsf{\pi }}{2}})\\ i_{\mathrm{c}}=I\sin (\mathsf{\omega }t+{\displaystyle \frac{5\mathsf{\pi }}{6}})\end{array}\right.$$

(5)

where I and $\phi$ represent the current amplitude and the power factor angle, respectively.

Based on the switching state combinations of the T-type structure depicted in Figure 4, the arm current expressions can be derived as follows:

$$i_{\mathrm{U}}=-I\sin (\theta +{\displaystyle \frac{\mathsf{\pi }}{6}}+\phi ), \theta \in [0,{\displaystyle \frac{2\mathsf{\pi }}{3}}]$$

(6)

$$i_{\mathrm{L}}=\left\{\begin{array}{l}I\sin (\theta -{\displaystyle \frac{\mathsf{\pi }}{2}}+\phi ),\theta \in [0,{\displaystyle \frac{\mathsf{\pi }}{3}})\\ I\sin (\theta +{\displaystyle \frac{5\mathsf{\pi }}{6}}+\phi ),\theta \in [{\displaystyle \frac{\mathsf{\pi }}{3}},{\displaystyle \frac{2\mathsf{\pi }}{3}}]\end{array}\right.$$

(7)

The arm instantaneous power can be calculated based on Equations (3), (4), (6) and (7), as expressed below:

$$p_{\mathrm{UN}}=\left\{\begin{array}{l}-\sqrt{3}VI\sin \left(\theta \right)\sin (\theta -{\displaystyle \frac{\mathsf{\pi }}{6}}+\phi ),\theta \in [0,{\displaystyle \frac{\mathsf{\pi }}{3}})\\ \sqrt{3}VI\sin (\theta +{\displaystyle \frac{\mathsf{\pi }}{3}})\sin (\theta -{\displaystyle \frac{\mathsf{\pi }}{6}}+\phi ),\theta \in [{\displaystyle \frac{\mathsf{\pi }}{3}},{\displaystyle \frac{2\mathsf{\pi }}{3}}]\end{array}\right.$$

(8)

$$p_{\mathrm{NL}}=\left\{\begin{array}{l}-\sqrt{3}VI\sin (\theta -{\displaystyle \frac{\mathsf{\pi }}{3}})\sin (\theta -{\displaystyle \frac{\mathsf{\pi }}{2}}+\phi ),\theta \in [0,{\displaystyle \frac{\mathsf{\pi }}{3}})\\ \sqrt{3}VI\sin (\theta -{\displaystyle \frac{\mathsf{\pi }}{3}})\sin (\theta +{\displaystyle \frac{5\mathsf{\pi }}{6}}+\phi ),\theta \in [{\displaystyle \frac{\mathsf{\pi }}{3}},{\displaystyle \frac{2\mathsf{\pi }}{3}}]\end{array}\right.$$

(9)

Furthermore, the arm average power can be calculated using the following expressions:

$$\left\{\begin{array}{l}{\stackrel{-}{p}}_{\mathrm{UN}}={\displaystyle \frac{3}{2\mathsf{\pi }}}{\displaystyle \underset{0}{\overset{2\mathsf{\pi }/3}{\int }}{u}_{\mathrm{UN}}{i}_{\mathrm{U}}}d(\mathsf{\omega }t)=-{\displaystyle \frac{3}{4}}VI\cos (\phi ) \\ {\stackrel{-}{p}}_{\mathrm{UN}}={\displaystyle \frac{3}{2\mathsf{\pi }}}{\displaystyle \underset{0}{\overset{2\mathsf{\pi }/3}{\int }}{u}_{\mathrm{NL}}{i}_{\mathrm{L}}}d(\mathsf{\omega }t)=-{\displaystyle \frac{3}{4}}VI\cos (\phi )\end{array}\right.$$

(10)

As indicated by Equation (10), under normal operating conditions, the upper and lower arms maintain identical average power, resulting in an inherent power balance that prevents natural SOC equalization. Since SOC regulation fundamentally depends on controlling the average power flow through each arm, this intrinsic power symmetry poses a critical challenge: when SOC imbalances develop between arms, the system lacks an inherent mechanism to restore equilibrium. The equal power distribution, while ensuring stable operation, paradoxically prevents the differential power flow necessary for SOC correction. To address this fundamental limitation, this paper proposes a dedicated inter-arm SOC balancing control strategy that deliberately breaks the power symmetry by introducing controlled power differentials between arms, thereby enabling active SOC equalization while maintaining system stability.

3. Proposed Inter-Arm SOC Balance Control Strategy

3.1. The Adjustment of Arm Valley Voltage

According to Equation (10), inter-arm power differential can theoretically be achieved through either voltage or current modulation. However, current-based regulation presents significant practical challenges. As illustrated in Figure 4, modulating inter-arm current distribution requires dynamic alteration of the T-type converter’s switching state combinations {Sa, Sb, Sc}, which introduces two fundamental limitations. First, the high-voltage switching devices commonly used in T-type converters typically operate at low switching frequencies; frequent switching transitions may degrade system reliability and efficiency. Second, changes in switching states directly influence the converter’s output voltage, resulting in variations in the output current. This strong voltage-current coupling significantly complicates the control system design and hinders precise power regulation.

Given these constraints, a more sophisticated approach involves modulating the arm voltage directly. The modular architecture of MMDTC, comprising multiple series-connected submodules per arm, provides exceptional flexibility for voltage waveform shaping. A distinctive characteristic of the arm voltage waveform, highlighted in Figure 5a, is the presence of valley regions that correspond to zero-voltage intervals. By precisely controlling both the amplitude and duration of these valley voltages, the arm’s time-averaged voltage—and consequently its power flow—can be effectively regulated without disrupting the fundamental T-type switching pattern.

Two complementary adjustment strategies have been developed:

(1) Duration Extension of Arm Valley Voltage (Figure 5b): The arm average voltage is reduced by extending the zero-voltage interval from its nominal value to a controlled duration β. This technique effectively increases the proportion of time during which the arm operates at zero voltage, thereby decreasing the time-averaged voltage through duty cycle modification.

(2) Both Amplitude and Duration Increase in Arm Valley Voltage (Figure 5c): The arm average voltage is increased through a dual-parameter approach that simultaneously elevates the arm valley voltage amplitude from zero to a predetermined positive value while extending its duration. This combined adjustment mechanism provides enhanced control flexibility, enabling fine-grained power regulation with improved dynamic response characteristics.

The proposed arm valley voltage adjustment strategy fully exploits the inherent structural advantages of modular multilevel converters, enabling precise power control through targeted modulation of local voltage waveform characteristics. By leveraging the flexibility afforded by the modular architecture, differential power distribution between arms can be achieved without compromising system stability or efficiency.

The fundamental objective of arm voltage adjustment is to establish precise control over inter-arm power flow. To address diverse operational requirements, four comprehensive power regulation strategies have been systematically developed, each tailored to specific battery charging-discharging states and SOC balancing requirements:

(1) Solution 1—Charging Power Reduction: As illustrated in Figure 6a, charging power is effectively reduced by extending the zero-voltage interval duration. This extension increases the duty cycle of the low-voltage state, thereby limiting energy absorption during the charging process while maintaining stable operation.

(2) Solution 2—Charging Power Enhancement: Figure 6b demonstrates power augmentation through simultaneous elevation of arm valley voltage amplitude and extension of its duration. This dual-parameter approach optimizes the voltage waveform to maximize energy absorption capacity during charging operations.

(3) Solution 3—Discharging Power Reduction: Power output is moderated by prolonging the zero-voltage duration, as shown in Figure 6c. The increased low-level duty cycle effectively constrains the energy release rate, enabling controlled discharging when power limitation is required.

(4) Solution 4—Discharging Power Enhancement: Figure 6d illustrates power amplification through combined arm valley voltage elevation and duration extension. This approach maximizes power delivery capability by optimizing the voltage waveform characteristics during discharging operations.

The practical implementation of inter-arm SOC balancing requires coordinated deployment of these four solutions based on real-time SOC differential assessment.

Table 1. Arm valley voltage adjustment scheme determined based on battery charging/discharging state and SOC difference across arms.

	Charging State		Discharging State
	${\mathbf{SOC}}_{\mathbf{UN}}{\mathbf{>}\mathbf{SOC}}_{\mathbf{NL}}$	${\mathbf{SOC}}_{\mathbf{UN}}{\mathbf{<}\mathbf{SOC}}_{\mathbf{NL}}$	${\mathbf{SOC}}_{\mathbf{UN}}{\mathbf{<}\mathbf{SOC}}_{\mathbf{NL}}$	${\mathbf{SOC}}_{\mathbf{UN}}{\mathbf{>}\mathbf{SOC}}_{\mathbf{NL}}$
Upper-arm	Solution 1	Solution 2	Solution 3	Solution 4
Lower-arm	Solution 2	Solution 1	Solution 4	Solution 3

presents the comprehensive control logic for various operational scenarios:

(1) During Charging Operations:

When SOC_UN > SOC_NL: Solution 1 is applied to the upper arm to restrict its charging rate, while Solution 2 is simultaneously implemented on the lower arm to accelerate its charging. This “suppress-high, enhance-low” approach effectively equalizes the SOC levels by differentially controlling the charging rates.

When SOC_UN < SOC_NL: The control logic is reversed—Solution 2 enhances upper arm charging while Solution 1 limits lower arm charging, thereby achieving complementary SOC adjustment.

(2) During Discharging Operations:

The same differential control philosophy is applied using Solution 3 and 4. The high-SOC arm undergoes accelerated discharging through Solution 4, while the low-SOC arm experiences moderated discharging via Solution 3, progressively converging the SOC levels toward equilibrium.

This systematic approach ensures robust SOC balancing across all operational modes while maintaining optimal power flow control.

When during the charging operation and SOC_UN > SOC_NL, the refined arm voltage is derived by implementing the control strategy outlined in Table 1:

$$u_{\mathrm{UN}\_\mathrm{ad}}=\left\{\begin{array}{l}\sqrt{3}V\sin \left(\theta \right),\theta \in [\beta ,{\displaystyle \frac{\mathsf{\pi }}{3}})\\ \sqrt{3}V\sin (\theta +{\displaystyle \frac{\mathsf{\pi }}{3}}),\theta \in ({\displaystyle \frac{\mathsf{\pi }}{3}},{\displaystyle \frac{2\mathsf{\pi }}{3}}-\beta ]\\ 0,\theta \in [0,\beta )\cap ({\displaystyle \frac{2\mathsf{\pi }}{3}}-\beta ,{\displaystyle \frac{2\mathsf{\pi }}{3}}]\end{array}\right.$$

(11)

$$u_{\mathrm{NL}\_\mathrm{ad}}=\left\{\begin{array}{l}-\sqrt{3}V\sin (\theta -{\displaystyle \frac{\mathsf{\pi }}{3}}),\theta \in [0,{\displaystyle \frac{\mathsf{\pi }}{3}}-\beta )\\ \sqrt{3}V\sin (\beta ),\theta \in [{\displaystyle \frac{\mathsf{\pi }}{3}}-\beta ,{\displaystyle \frac{\mathsf{\pi }}{3}}+\beta ]\\ \sqrt{3}V\sin (\theta -{\displaystyle \frac{\mathsf{\pi }}{3}}), \theta \in ({\displaystyle \frac{\mathsf{\pi }}{3}}+\beta ,{\displaystyle \frac{2\mathsf{\pi }}{3}}]\end{array}\right.$$

(12)

Assuming that the arm current remains constant during the process of voltage fine-tuning, the arm instantaneous power expressions can be derived from Equations (6), (7), (11) and (12) as follows:

$$p_{\mathrm{UN}\_\mathrm{ad}}=\left\{\begin{array}{l}-\sqrt{3}VI\sin \left(\theta \right)\sin (\theta -{\displaystyle \frac{\mathsf{\pi }}{6}}+\phi ),\theta \in [\beta ,{\displaystyle \frac{\mathsf{\pi }}{3}})\\ \sqrt{3}VI\sin (\theta +{\displaystyle \frac{\mathsf{\pi }}{3}})\sin (\theta -{\displaystyle \frac{\mathsf{\pi }}{6}}+\phi ),\theta \in ({\displaystyle \frac{\mathsf{\pi }}{3}},{\displaystyle \frac{2\mathsf{\pi }}{3}}-\beta ]\\ 0,\theta \in [0,\beta )\cap ({\displaystyle \frac{2\mathsf{\pi }}{3}}-\beta ,{\displaystyle \frac{2\mathsf{\pi }}{3}}]\end{array}\right.$$

(13)

$$p_{\mathrm{NL}\_\mathrm{ad}}=\left\{\begin{array}{l}-\sqrt{3}VI\sin (\theta -{\displaystyle \frac{\mathsf{\pi }}{3}})\sin (\theta -{\displaystyle \frac{\mathsf{\pi }}{2}}+\phi ),\theta \in [0,{\displaystyle \frac{\mathsf{\pi }}{3}}-\beta )\\ -\sqrt{3}VI\sin (\beta )\sin (\theta -{\displaystyle \frac{\mathsf{\pi }}{2}}+\phi ),\theta \in [{\displaystyle \frac{\mathsf{\pi }}{3}}-\beta ,{\displaystyle \frac{\mathsf{\pi }}{3}})\\ \sqrt{3}VI\sin (\beta )\sin (\theta +{\displaystyle \frac{5\mathsf{\pi }}{6}}+\phi ),\theta \in [{\displaystyle \frac{\mathsf{\pi }}{3}},{\displaystyle \frac{\mathsf{\pi }}{3}}+\beta )\\ \sqrt{3}VI\sin (\theta -{\displaystyle \frac{\mathsf{\pi }}{3}})\sin (\theta +{\displaystyle \frac{5\mathsf{\pi }}{6}}+\phi ),\theta \in ({\displaystyle \frac{\mathsf{\pi }}{3}}+\beta ,{\displaystyle \frac{2\mathsf{\pi }}{3}}]\end{array}\right.$$

(14)

Furthermore, the expressions for arm average power can be derived as follows:

$${\overline{p}}_{\mathrm{UN}\_\mathrm{ad}}=-{\displaystyle \frac{3VI\left[-6\beta +3\sin \left(2\beta \right)+\sqrt{3}\cos \left(2\beta \right)-\sqrt{3}+2\mathsf{\pi }\right]}{8\mathsf{\pi }}}\cos \left(\phi \right)$$

(15)

$${\stackrel{—}{p}}_{\mathrm{NL}\_\mathrm{ad}}=-{\displaystyle \frac{3VI\left[-6\beta +12\sin \left(\beta \right)-3\sin \left(2\beta \right)-\sqrt{3}\cos \left(2\beta \right)+\sqrt{3}+2\mathsf{\pi }\right]}{8\mathsf{\pi }}}\cos \left(\phi \right)$$

(16)

Based on Equations (15) and (16), the inter-arm power difference can be derived as follows:

$$|\Delta p|=|{\overline{p}}_{\mathrm{UN}\_\mathrm{ad}}-{\overline{p}}_{\mathrm{NL}\_\mathrm{ad}}|={\displaystyle \frac{3VI\sin \left(\beta \right)\left[\sqrt{3}\sin \left(\beta \right)-3\cos \left(\beta \right)+3\right]}{2\mathsf{\pi }}}\cos \left(\phi \right)$$

(17)

Similarly, the inter-arm power difference under the other three operating conditions listed in Table 1 can be derived, as demonstrated by Equation (17).

The inter-arm average power difference $|∆p|$, along with its ratio to the arm average power, can be determined using Equations (17) and (10):

$$\mu =\left|{\displaystyle \frac{∆p}{{\overline{p}}_{\mathrm{UN}}}}\right|={\displaystyle \frac{2\sin \left(\beta \right)\left[\sqrt{3}\sin \left(\beta \right)-3\cos \left(\beta \right)+3\right]}{\mathsf{\pi }}}$$

(18)

As illustrated in Equation (18), the ratio $\mu$ is expressed as a function of $\beta$, with the corresponding functional curve depicted in Figure 7. $\mu$ exhibits a positive correlation with $\beta$, and a maximum power regulation capability of approximately 4% can be achieved when condition $\beta <\mathsf{\pi }/18$ is met.

For the purpose of analysis, the distinctions between submodules within the arm are considered negligible, with each submodule assumed to possess equal charging and discharging power. Based on the principle of power conservation, the following equation is derived:

$$N{U}_{\mathrm{b}}{i}_{\mathrm{dc}}={\overline{p}}_{\mathrm{arm}}$$

(19)

where $U_{\mathrm{b}}$ and i_dc signifies the battery voltage and average current entering the battery, respectively.

The submodule SOC is derived using the ampere-hour integration method, as outlined below:

$${\mathrm{SOC}}_{\mathrm{SM}}={\mathrm{SOC}}_{\mathrm{SM}}(t_0)+{\displaystyle \frac{1}{{\mathrm{C}}_{\mathrm{rate}}}}{\displaystyle {\int }_{t_0}^t{i}_{\mathrm{dc}}}d(t)$$

(20)

where ${\mathrm{C}}_{rate}$ represents the rated capacity of the submodule battery.

From Equations (19) and (20), it can be concluded that:

$$N{\mathrm{SOC}}_{\mathrm{SM}}=N{\mathrm{SOC}}_{\mathrm{SM}}(t_0)+{\displaystyle \frac{{\stackrel{\_}{p}}_{\mathrm{arm}}}{U_{\mathrm{b}}{\mathrm{C}}_{\mathrm{rate}}}}(t-t_0)$$

(21)

Definition ${\mathrm{SOC}}_{\mathrm{arm}}=N{\mathrm{SOC}}_{\mathrm{SM}}$, the aforementioned equation can be rewritten as:

$${\mathrm{SOC}}_{\mathrm{arm}}={\mathrm{SOC}}_{\mathrm{arm}}(t_0)+{\displaystyle \frac{{\stackrel{\_}{p}}_{\mathrm{arm}}}{U_{\mathrm{b}}{\mathrm{C}}_{\mathrm{rate}}}}(t-t_0)$$

(22)

According to Equation (22), the inter-arm SOC difference can be derived as follows:

$$∆\mathrm{SOC}={\mathrm{SOC}}_{\mathrm{UN}}-{\mathrm{SOC}}_{\mathrm{NL}}=\left[{\mathrm{SOC}}_{\mathrm{UN}}(t_0)-{\mathrm{SOC}}_{\mathrm{NL}}(t_0)\right]+{\displaystyle \frac{\left({\overline{p}}_{\mathrm{UN}\_\mathrm{ad}}-{\overline{p}}_{\mathrm{NL}\_\mathrm{ad}}\right)}{U_{\mathrm{b}}{\mathrm{C}}_{\mathrm{rate}}}}(t-t_0)$$

(23)

The time required for the inter-arm SOC to attain an equilibrium state ($∆\mathrm{SOC}=0$) can be determined as $∆t$ by integrating Equations (17) and (23):

$$∆t=t-t_0={\displaystyle \frac{2\mathsf{\pi }{U}_{\mathrm{b}}{\mathrm{C}}_{\mathrm{rate}}\left|∆\mathrm{SOC}(t_0)\right|}{3VI\sin \left(\beta \right)\left(\sqrt{3}\sin \left(\beta \right)-3\cos \left(\beta \right)+3\right)}}$$

(24)

where $\left|∆\mathrm{SOC}(t_0)\right|$ represents the inter-arm initial SOC difference.

In a similar manner, the same relational expression can be derived by examining the other three cases.

Equation (24) establishes a precise mathematical relationship among Δt, β, and ΔSOC. In practical implementations, the balance time Δt can be flexibly configured according to specific system requirements and operational constraints. Once Δt is predetermined and ΔSOC is measured, the required β value can be directly calculated using Equation (24), enabling real-time adaptive control.

Based on this mathematical framework, a comprehensive inter-arm SOC balancing control algorithm has been developed, as illustrated in Figure 8. The implementation follows a systematic five-step procedure:

Step 1: The desired SOC equilibrium time Δt is determined based on operational requirements, battery characteristics, and system performance specifications. This parameter defines the convergence rate of the SOC balancing process.

Step 2: The battery management system continuously monitors and calculates the ΔSOC, providing real-time feedback for the control algorithm.

Step 3: The measured ΔSOC is substituted into Equation (24) to compute the corresponding β.

Step 4: Based on the battery’s operational mode (charging/discharging) and the polarity of ΔSOC, the appropriate arm voltage adjustment strategy is selected from the predefined control matrix presented in Table 1. This ensures optimal power flow direction for SOC convergence.

Step 5: The algorithm continuously evaluates whether |ΔSOC(t)| has fallen below the predetermined threshold ε. If |ΔSOC(t)| > ε, the SOC balancing control continues. Once |ΔSOC(t)| ≤ ε is satisfied, indicating successful SOC equilibrium, the modulation parameter is reset (β = 0) and normal operation resumes.

Figure 9a illustrates the comprehensive control architecture of the MMDTC-BESS system. The β parameter, calculated using Equation (24), serves as a key control variable and is seamlessly integrated into the existing control framework. The modulation wave is generated by the internal power control loop of the system. Based on the structure shown in Figure 4, the control signals for the T-type structure and the modulation waves for the upper and lower arms of the DC link can be further derived. Finally, carrier phase-shifted pulse width modulation (CPS-PWM) is adopted as the core modulation strategy for the converter, while incorporating mature technologies such as power control with Proportional-Integral (PI) controllers and submodule-level SOC balancing control with P controllers as shown in Figure 9b,c, respectively. Given that these conventional control methods have been thoroughly elaborated in the existing literature, this paper does not discuss their specific implementation details in depth.

3.2. The Impact of Arm Voltage Valley Adjustment on Output Waveform Quality

This section provides a comprehensive analysis of how arm valley voltage adjustment affects the output voltage waveform quality in MMDTC. Under normal operation, the MMDTC synthesizes high-quality sinusoidal output voltages through precise superposition of upper and lower arm voltages. However, the implementation of inter-arm SOC balancing control necessitates deliberate modifications to the conventional voltage synthesis pattern, which inevitably influences the harmonic performance of the three-phase output. Figure 10 illustrates these effects through comparative waveform analysis, clearly demonstrating the spectral changes induced by arm valley voltage modulation.

Figure 11 presents a detailed quantitative assessment of the relationship between the β and output voltage total harmonic distortion (THD). As evident from Figure 11a, the THD exhibits a monotonically increasing relationship with β, indicating progressive waveform degradation as the β increases.

The spectral decomposition presented in Figure 11b reveals the underlying mechanism: the THD elevation is predominantly caused by the emergence of even-order harmonics, particularly the 2nd and 4th components. This phenomenon directly results from the asymmetrical voltage modulation introduced between the upper and lower arms, which disrupts the natural harmonic cancelation inherent in balanced MMDTC operation.

These findings reveal a fundamental trade-off in the proposed control strategy: while larger β values accelerate inter-arm SOC convergence, they simultaneously compromise output power quality. This necessitates a holistic optimization approach that balances SOC equilibrium requirements against THD.

A particularly advantageous feature of the proposed strategy is its inherent adaptive regulation capability. As demonstrated in Figure 6, continuous application of the control algorithm drives ΔSOC toward zero, where it stabilizes with only minor fluctuations within the predetermined threshold ε. This convergence behavior has significant practical implications: as ΔSOC approaches zero, the required β value diminishes correspondingly, automatically reducing the harmonic impact on output waveforms.

4. Simulation and Experimental Verification

4.1. Simulation Verification

To verify the effectiveness of the proposed inter-arm SOC balance control strategy, a 10 kV/2 MW MMDTC-BESS simulation model was established on the MATLAB/Simulink platform. The specific simulation parameters are presented in

Table 2. Main parameters list of simulation.

Variable	Symbol	Value
Rated grid line voltage	$V_{\mathrm{line}}$	10 kV
Rated active power	P	2 MW
Rated reactive power	Q	0
Grid-side filtering inductance	L	5 mH
Number of submodules per arm	N	20
Battery pack voltage	$U_{\mathrm{b}}$	800 V
Rated capacity of Battery	${\mathrm{C}}_{\mathrm{rate}}$	200 Ah
Submodule capacitance	${\mathrm{C}}_{\mathrm{sm}}$	0.47 mF
Switching frequency	fs	1.5 kHz
$\mathrm{Threshold} \mathrm{value} \mathrm{of} ∆\mathrm{SOC}$	$\epsilon$	$1\times {10}^{-5}$

.

To examine how the arm valley voltage width β affects inter-arm SOC balance speed, comparative simulations were conducted under two typical conditions: β = π/18 and β = π/25.

Case 1 (β = π/18): As illustrated in Figure 12, the initial ΔSOC is set at 0.2%, with the SOC balance control strategy being initiated at time t₀. The simulation demonstrates that under discharging mode, SOC equilibrium between arms is achieved within Δt = 62.2 s (Figure 12a), while the charging mode requires Δt = 64.8 s to reach balance (Figure 12b). According to the system parameters provided in Table 2, the theoretical balancing time derived from Equation (24) is calculated as Δt = 60 s. The relative error between simulated and theoretical values remains below 8%, confirming the validity of the theoretical analysis. Figure 12c illustrates a transition from discharge to charge: initially, the battery is in discharge mode, and after 62.2 s, the SOC of arms reaches a balanced state; subsequently, at t = 100 s, the system switches from discharge to charge mode. The results show that despite the change in operating mode, the SOC among arms maintains good balance.

Case 2 (β = π/25): As illustrated in Figure 13, the balancing control is initiated at time t₀ while maintaining an identical initial SOC difference (ΔSOC = 0.2%). Simulation results demonstrate that the balancing duration extends to Δt = 124.6 s in discharging mode and Δt = 128.8 s in charging mode. The corresponding theoretical value is calculated as 120 s based on Equation (24), with the relative error between simulation and theoretical results remaining minimal. Similarly, Figure 13c also indicates that the SOC among arms remains balanced during transition between discharge and charge mode.

The comparison of two cases reveals that when the β value is reduced, the SOC balancing time increases. This observation aligns closely with the inverse relationship indicated in Equation (24). The results not only validate the effectiveness of the proposed theoretical model but also provide significant reference for the rational selection of β values in practical applications.

It is particularly noteworthy that the proposed inter-arm SOC balance control strategy features a self-adaptive regulation capability. As illustrated in the control flow of Figure 8, the system dynamically adjusts the arm valley voltage width β in response to real-time deviations in SOC. This characteristic provides significant operational advantages: during stable operation, closed-loop feedback control effectively maintains the ΔSOC within narrow fluctuations around predefined thresholds. With reduced balancing requirements, the corresponding β value decreases proportionally, thereby minimizing degradation in output power quality. Such an adaptive mechanism optimally balances SOC performance and power quality maintenance dynamically.

During both discharging and charging modes, the absence of a SOC balance strategy results in a significant inter-arm SOC divergence, with no tendency for convergence. This indicates an SOC imbalance despite the maintenance of power equilibrium across the arms. However, upon implementing the inter-arm SOC balance strategy, this disparity in SOC progressively diminishes; concurrently, deviations in arm power emerge, thereby confirming the efficacy of the proposed strategy. Under discharging conditions (see Figure 14c–f), the balancing strategy modifies the output characteristics of MMDTC-BESS: specifically, the THD of output voltage increases from 4.57% to 7.18%, while there is also an increase in output current THD from 0.76% to 1.04%. Similarly, during charging operations (refer to Figure 15c–f), the balancing strategy affects MMDTC-BESS’s output performance: here too, we observe an escalation in output voltage THD from 5.16% to 8.13%, alongside a rise in output current THD from 0.43% to 0.67%. Figure 14 and Figure 15 illustrate that while maintaining excellent balancing performance throughout both charging and discharging mode, this proposed strategy simultaneously impacts power quality metrics. Therefore, it is imperative that any practical implementations verify that waveform distortion rates remain within acceptable thresholds prior to applying SOC balance control.

4.2. Experimental Verification

To assess the effectiveness of the proposed control strategy, an MMDTC experimental platform has been constructed, as illustrated in Figure 16, with detailed experimental parameters provided in

Table 3. The main experimental parameters.

Variable	Symbol	Value
Grid voltage	$V_{\mathrm{g}}$	110 V
Rated amplitude of phase current	$I_{\mathrm{O}}$	5 A
Grid-side filtering inductance	L	4 mH
Number of submodules per arm	N	5
DC voltage of submodule	$U_{\mathrm{b}}$	50 V
Submodule capacitance	${\mathrm{C}}_{\mathrm{sm}}$	0.2 mF
Switching frequency	fs	5 kHz

. The main circuit is established using self-designed half-bridge submodules, while the control system is implemented on the RT-LAB real-time simulator. It is important to note that current laboratory conditions, adhering to safety regulations, do not permit the storage and maintenance of large-scale energy storage batteries in our laboratory. As a result, multiple programmable DC power supplies are utilized to replace the energy storage units, as depicted in Figure 16. This simplification does not compromise the validity of the experiment; prior theoretical analysis confirms that the core mechanism for inter-arm SOC balancing involves regulating average power distribution between the upper and lower arms.

To verify the bidirectional power regulation capability of the proposed control strategy between arms, two complementary experimental schemes were designed:

• Case 1: Assuming a discharging condition with low SOC in the upper arm.

Solutions 3 and 4 are implemented on the upper arm and lower arm, respectively (see Figure 6), thereby replicating a typical discharging scenario where the SOC in the upper arm is lower than that in the lower arm (refer to Table 1). The experimental data is presented in Figure 17.

• Case 2: Assuming a discharging condition with high SOC in the upper arm.

In this configuration, Solutions 4 and 3 are reversed, placing Solution 4 on the upper arm and Solution 3 on the lower arm. This creates a comparative scenario wherein the SOC in the upper arm exceeds that in the lower arm during discharging. The results are documented in Figure 18.

Subfigures (a)–(c) within both Figure 17 and Figure 18 illustrate output line voltage, current waveforms, as well as characteristics related to voltage/current/power for each respective arm. Key findings from these experiments include:

(1) Power quality influence

The THD of the output line voltage and current, as illustrated in subplots (a)–(b) of Figure 17 and Figure 18, is observed to increase monotonically as β rises from 0 to π/18. This observation confirms the inverse relationship between β and power quality, aligning with both theoretical predictions and simulation results.

(2) Power differential adjustment capability

Case 1 (Figure 17c) exhibits a distinct linear control characteristic, with the average power difference across the upper and lower arms measuring −1.4 W, −6.1 W, and −22.1 W at β values of 0, π/25, and π/18, respectively. Conversely, Case 2 (Figure 18c) demonstrates reversed polarity while maintaining an identical trend; it shows power differences of −1.4 W, +4.3 W, and +21.2 W, corresponding to the respective β values.

The experimental results from both schemes clearly illustrate that precise bidirectional regulation of power between the arms can be achieved by adjusting the arm valley voltage width β; furthermore, this regulation intensity exhibits a positive correlation with increasing β values.

5. Conclusions

The control strategy for inter-arm SOC balancing based on the arm valley voltage adjustment proposed in this paper successfully addresses the issue of imbalance between arms in MMDTC-BESS. By adjusting the arm valley voltage width, it disrupts the inherent power balance between the upper and lower arms. A comprehensive mathematical model has been established through theoretical analysis, deriving a quantitative relationship where the inter-arm power difference is directly proportional to the arm valley voltage width β, while SOC balancing time is inversely proportional to β. Simulation and experimental results validate both the effectiveness and practicality of this strategy; specifically, at β = π/18, approximately 4% power regulation capability can be achieved, with a high degree of correlation between theoretical predictions and measured outcomes. It is particularly noteworthy that this proposed strategy exhibits adaptive control characteristics: during steady-state operation, closed-loop feedback maintains β within a narrow range, thereby ensuring dynamic SOC equilibrium while minimizing adverse impacts on power quality. This research fills a technical gap in inter-arm SOC balancing control and lays a theoretical foundation for engineering applications of this novel topology in battery energy storage fields.