Control Applications with FPGA: Case of Approaching FPGAs for Students in an Intelligent Control Class
Abstract
1. Introduction
2. Materials and Methods
2.1. Teaching Set 1: Levitation of a Lightweight Ball
2.1.1. Understanding the Underlying Physics and Mathematical Model
2.1.2. Hardware
2.2. Teaching Set 2: Applying the Fuzzy Logic for 1-DOF Spring Mechanism
2.2.1. Understanding the Underlying Physics and Pertaining Mathematical Model
2.2.2. Fuzzy Logic Controller Implementation on the FPGA
| Algorithm 1 Fuzzy Logic Control System |
|
- If velocity error strong negative then accelerate heavily ;
- If velocity error negative N then accelerate A;
- If velocity error minor negative then accelerate slightly ;
- If velocity error slightly positive then decelerate slightly ;
- If velocity error positive P then decelerate D;
- If velocity error strong positive then decelerate heavily .
2.2.3. Practical Implementation of the Fuzzy Logic on the FPGA
3. Experiments and Results
3.1. Experimental Setup
3.2. Evaluation Criteria
3.3. Results
3.3.1. Results on Ball Levitation
3.3.2. Results on Spring Mechanism
3.3.3. Discussion
4. Conclusions
Author Contributions
Funding
Institutional Review Board Statement
Informed Consent Statement
Data Availability Statement
Conflicts of Interest
Abbreviations
| DAC | Digital-to-analog converter |
| ED | Embedded Device |
| EI | Embedded Intelligence |
| FPGA | Field Programmable Gate Array |
| FLC | Fuzzy logic controller |
| HDL | Hardware abstraction layer |
| PCB | Printed circuit board |
| PID | Proportional, integral, derivative controller |
| PLL | Phase locked loop |
| PWM | Pulse width modulation |
| RPM | Revolution per minute |
| RTL | Register transfer level |
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| Signal | Bit Width | Visualization |
|---|---|---|
| 1 bit | 1’b x | |
| 1 bit | 1’b x | |
| 1 bit | 1’b x | |
| 8 bit | 8’b xxxx.xxxx | |
| 8 bit | 8’b xxxx.xxxx | |
| 1 bit | 1’b x | |
| 1 bit | 1’b x | |
| 1 bit | 1’b x | |
| 1 bit | 1’b x | |
| 1 bit | 1’b x | |
| 12 bit | 12’b xxxx.xxxx.xxxx | |
| 16 bit | 16’b s1xxx.xxxx.xxxx.xxxx | |
| u | 9 bit | 9’b sxxxx.xxxx |
| 1 bit | 1’b x | |
| 7 bit | 7’b xxx.xxxx | |
| 7 bit | 7’b xxx.xxxx |
| Input Triangular Membership Functions | Output Singletons | |||
|---|---|---|---|---|
| Function Name | Min | Max | Singleton | Value |
| N | ||||
| 16 | ||||
| 56 | 0 | |||
| P | 32 | 512 | 10 | |
| 512 | 2096 | 55 | ||
| 75 | ||||
| Mean Error | Stdev of Oscillations | |||
|---|---|---|---|---|
| Run | PI | FLC | PI | FLC |
| 1 | 3829.18 | 4203.14 | 61.89 | 64.85 |
| 2 | 3652.21 | 4063.60 | 60.45 | 63.76 |
| 3 | 3706.62 | 4106.59 | 60.89 | 64.10 |
| 4 | 3870.04 | 4215.86 | 62.22 | 64.94 |
| 5 | 3918.14 | 4184.71 | 62.61 | 64.70 |
| 6 | 3855.74 | 4367.55 | 62.11 | 66.10 |
| 7 | 3864.81 | 4143.20 | 62.18 | 64.38 |
| 8 | 3864.20 | 4077.71 | 62.18 | 63.87 |
| 9 | 3865.01 | 4114.42 | 62.18 | 64.16 |
| 10 | 3870.59 | 4258.95 | 62.35 | 62.58 |
| mean | 3829.65 | 4173.57 | 61.91 | 64.34 |
| std | 83.08 | 93.03 | 0.68 | 0.92 |
| min | 3652.21 | 4063.60 | 60.45 | 62.58 |
| max | 3918.14 | 4367.55 | 62.61 | 66.10 |
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Share and Cite
Fister, D.; Jakopič, A.; Truntič, M. Control Applications with FPGA: Case of Approaching FPGAs for Students in an Intelligent Control Class. Appl. Sci. 2025, 15, 12884. https://doi.org/10.3390/app152412884
Fister D, Jakopič A, Truntič M. Control Applications with FPGA: Case of Approaching FPGAs for Students in an Intelligent Control Class. Applied Sciences. 2025; 15(24):12884. https://doi.org/10.3390/app152412884
Chicago/Turabian StyleFister, Dušan, Alen Jakopič, and Mitja Truntič. 2025. "Control Applications with FPGA: Case of Approaching FPGAs for Students in an Intelligent Control Class" Applied Sciences 15, no. 24: 12884. https://doi.org/10.3390/app152412884
APA StyleFister, D., Jakopič, A., & Truntič, M. (2025). Control Applications with FPGA: Case of Approaching FPGAs for Students in an Intelligent Control Class. Applied Sciences, 15(24), 12884. https://doi.org/10.3390/app152412884

