Low-Noise Chopper-Stabilized Multi-Path Operational Amplifier with Nested Miller Compensation for High-Precision Sensors

Abstract

This paper presents a low-noise multi-path operational amplifier for high-precision sensors. A chopper stabilization technique is applied to the amplifier to remove offset and flicker noise. A ripple reduction loop (RRL) is designed to remove the ripple generated in the process of up-modulating the flicker noise and offset. To cancel the notch in the overall transfer function due to the RRL operation, a multi-path architecture using both a low-frequency path (LFP) and high-frequency path (HFP) is implemented. The low frequency path amplifier is implemented using the chopper technique and the RRL. In the high-frequency path amplifier, a class-AB output stage is implemented to improve the power efficiency. The transfer functions of the LFP and HFP induce a first-order frequency response in the system through nested Miller compensation. The low-noise multi-path amplifier was fabricated using a 0.18 µm 1P6M complementary metal-oxide-semiconductor (CMOS) process. The power consumption of the proposed low-noise operational amplifier is 0.174 mW with a 1.8 V supply and an active area of 1.18 mm². The proposed low-noise amplifier has a unit gain bandwidth (UGBW) of 3.16 MHz, an input referred noise of 11.8 nV/√Hz, and a noise efficiency factor (NEF) of 4.46.

1. Introduction

With the development of smart devices for Internet of Things (IoT), various sensor applications are becoming increasingly necessary. Among them, micro-electro-mechanical system (MEMS) sensors are receiving particular attention due to their small size, high signal-to-noise ratio (SNR), and low cost [1,2,3,4]. Sensing diminutive signals with a small output current and small output voltage amplitude using MEMS sensors requires large amplification. Therefore, high gain, high input impedance, and low-noise operational amplification are essential for various sensor interfaces [5,6,7]. To reduce output noise, chopper stabilization or auto-zeroing techniques are typically used [8]. The auto-zeroing technique typically operates using two phases. The first phase stores flicker noise and offset in the auto-zero capacitor, and the next phase subtracts the stored flicker noise and offset from the input signal. Because of these two phases, the auto-zeroing technique performs discrete-time operation. In addition, auto-zeroing techniques cause switching noise as well as noise folding of high-frequency components due to sampling operations, thus chopper-stabilized architecture is preferred for low-power and low-noise continuous-time applications [9]. Chopper stabilization techniques modulate the offset and flicker noise with a chopper frequency (f_chop), leaving only thermal noise in the base band. However, the offset and the flicker noise are up-modulated, and these up-modulated noise signals are referred to as ripple. To attenuate this ripple, the ripple reduction loop (RRL) was proposed [10]. RRL integrates the generated ripple voltage at the output node and feeds back the integrated ripple to the input stage negatively. However, there is a limit in bandwidth because the transfer function of the amplifier produces a notch at the chopper frequency.

The bandwidth is increased by using a multi-path structure—a combination of a low-frequency path (LFP) and a high-frequency path (HFP). The transfer functions of the LFP and HFP induce a first-order frequency response in the system (a first-order system) by applying nested Miller compensation [11]. In the HFP, a class-AB output stage is implemented to improve the power efficiency. The proposed low-noise multi-path operational amplifier was fabricated using a 0.18-µm 1P6M complementary metal-oxide-semiconductor (CMOS) process. The average current consumption is 96.7 µA and the active area is 1.18 mm². The proposed low-noise multi-path amplifier has a unit gain bandwidth (UGBW) of 3.16 MHz, an input referred noise of 11.8 nV/√Hz, and a noise efficiency factor (NEF) of 4.46.

2. Circuit Implementation of the Proposed Operational Amplifier

2.1. Architecture of the Proposed Multi-Path Operational Amplifier

The basic schematic is shown in Figure 1. The proposed circuit consists of two main paths, the HFP and LFP. In Figure 1, the red line represents the HFP and the blue line represents the LFP. The LFP consists of four stages, and the HFP consists of two stages. The LFP applies chopper stabilization to decrease the offset and flicker noise, while ripple is suppressed by the RRL. Connect the output of A₆ in the current adder opposite to the output of A₂ to suppress the ripple. The HFP has a first-order frequency response with one dominant pole caused by C_m1 and the LFP has a second-order frequency response with two dominant poles caused by C_m1 and C_i1. Nested Miller compensation is applied to smoothly combine the two frequency responses.

2.2. Low-Frequency Path Design

The LFP is shown in Figure 2. Because the LFP amplifies in four stages and the HFP in two stages, the LFP predominantly determines the offset and flicker noise of the overall amplifier. Using the chopper, the offset and flicker noise are up-modulated to the chopper frequency to reduce the offset and flicker noise in the baseband. The schematic of the input stage is shown in Figure 3. The common mode feedback (CMFB) of the current adder is implemented with an amplifier structure. The V_cmfb is set to 1/2 VDD so that the common mode voltage of the output V_op and V_on are set to 1/2 VDD.

The signal is converted to a current through A₂ and the ripple is converted to a current through A₆. The two-signal current and the ripple current are subtracted through the current adder to suppress ripple. The output current of the current adder is converted to V_x through the A₃ integrator. V_x is converted to a current through A₄ and is merged with the HFP current through the current adder before A₅.

2.3. Ripple Reduction Loop Design

The offset of A₂ is shown in V_x as the ripple due to the demodulation chopper and integrator A₃. When the transconductance of A₂ is G_m2 and the frequency of the chopper is f_ch, the ripple at the output of A₃ can be expressed as

$${\mathrm{V}}_{\mathrm{r}\mathrm{i}\mathrm{p}\mathrm{p}\mathrm{l}\mathrm{e}1}\approx \frac{{\mathrm{V}}_{\mathrm{o}\mathrm{s}2}{\mathrm{G}}_{\mathrm{m}2}}{2{\mathrm{C}}_{\mathrm{i}1}{\mathrm{f}}_{\mathrm{c}\mathrm{h}}}.$$

(1)

When the transconductance of A₄ is G_m4, this ripple is integrated again by integrator A₅ so the ripple of the operational amplifier output can be expressed as

$${\mathrm{V}}_{\mathrm{r}\mathrm{i}\mathrm{p}\mathrm{p}\mathrm{l}\mathrm{e}2}\approx \frac{{\mathrm{V}}_{\mathrm{r}\mathrm{i}\mathrm{p}\mathrm{p}\mathrm{l}\mathrm{e}1}{\mathrm{G}}_{\mathrm{m}4}}{8{\mathrm{C}}_{\mathrm{m}1}{\mathrm{f}}_{\mathrm{c}\mathrm{h}}}.$$

(2)

To reduce this ripple, the ripple reduction loop is used. The AC component V_ripple1 is converted to the current I_r by the AC coupling capacitor C_r and is input into the current buffer (CB).

$$\left|{\mathrm{I}}_{\mathrm{r}}\right|\approx 2{\mathrm{C}}_{\mathrm{r}}{\mathrm{f}}_{\mathrm{c}\mathrm{h}}\left|{\mathrm{V}}_{\mathrm{r}\mathrm{i}\mathrm{p}\mathrm{p}\mathrm{l}\mathrm{e}1}\right|$$

(3)

The CB is shown in Figure 4. If the output impedance of current source M₁, M₂, M₇, and M₈ is large enough, the output voltage and DC output impedance of the CB are given in Equations (4) and (5). The A_CB is the DC voltage gain of the NMOS cascode in the CB. The output of the CB through A₆ is combined to estimate the amount of ripple suppressed by the current adder, as given by Equation (6).

$${\mathrm{V}}_{\mathrm{C}\mathrm{B}}=\left|{\mathrm{I}}_{\mathrm{r}}\right|\cdot {\mathrm{R}}_{\mathrm{C}\mathrm{B}}$$

(4)

$$\mathrm{w}\mathrm{h}\mathrm{e}\mathrm{r}\mathrm{e},{\mathrm{R}}_{\mathrm{C}\mathrm{B}}=\frac{{\mathrm{A}}_{\mathrm{C}\mathrm{B}}}{2{\mathrm{C}}_{\mathrm{r}}{\mathrm{f}}_{\mathrm{c}\mathrm{h}}}$$

(5)

$${\mathrm{I}}_{\mathrm{r}\mathrm{i}\mathrm{p}\mathrm{p}\mathrm{l}\mathrm{e}\_\mathrm{c}\mathrm{a}\mathrm{n}}\approx \frac{{\mathrm{A}}_{\mathrm{C}\mathrm{B}}{\mathrm{G}}_{\mathrm{m}2}{\mathrm{G}}_{\mathrm{m}6}{\mathrm{V}}_{\mathrm{o}\mathrm{s}2}}{2{\mathrm{C}}_{\mathrm{i}1}{\mathrm{f}}_{\mathrm{c}\mathrm{h}}}$$

(6)

The simulation results of the ripple for V_x when a 10-mV offset exists are shown in Figure 5. The red line is the output waveform of V_x in Figure 2 when RRL is not working, and the blue line is the output waveform of V_x when RRL is operating. The ripple voltage was reduced by approximately 88%, from 68 mV to 8 mV by the RRL.

Finally, the ripple suppression factor F can be expressed as

$$\mathrm{F}=\frac{{\mathrm{I}}_{\mathrm{r}\mathrm{i}\mathrm{p}\mathrm{p}\mathrm{l}\mathrm{e}\_\mathrm{c}\mathrm{a}\mathrm{n}}}{{\mathrm{I}}_{\mathrm{o}\mathrm{s}2}}=\frac{{\mathrm{A}}_{\mathrm{C}\mathrm{B}}{\mathrm{G}}_{\mathrm{m}6}}{2{\mathrm{C}}_{\mathrm{i}1}{\mathrm{f}}_{\mathrm{c}\mathrm{h}}},{\mathrm{I}}_{\mathrm{o}\mathrm{s}2}={\mathrm{V}}_{\mathrm{o}\mathrm{s}2}{\mathrm{G}}_{\mathrm{m}2}.$$

(7)

2.4. High-Frequency Path Design

The HFP of the proposed operational amplifier is shown in Figure 6. The HFP consists of a folded cascode and a Monticelli-class AB output circuit [12] to increase power efficiency. The HFP becomes active when the loop gain of the HFP exceeds the loop gain of the LFP.

2.5. Frequency Response

The LFP and HFP signals are combined by the current adder in Figure 6. The LFP has a second-order frequency response caused by A₃ and A₅ and the HFP has a first-order frequency response caused by A₅. To smoothly merge the transfer functions of the two paths, the frequency response of the LFP must be made similar to that of a first-order system. To accomplish this, the poles were split by applying the nested Miller compensation to C_m1, C_m2, and C_m3. In the case of C_m2, as there is positive feedback, there is a risk that the operation of the entire amplifier will become unstable by inducing the pole to appear in the right half of the complex-s plane [13]. Therefore, C_m2 is connected to a negative terminal and its signal is implemented in the form of negative feedback.

The simulation results of the complete transfer function of the proposed operational amplifier are shown in Figure 7. The red line represents the HFP, the blue line represents the LFP, and the black line represents the overall transfer function of the multi-path operational amplifier. The frequency where the loop gain of the LFP and the loop gain of the HFP are equal is called the cross-over frequency and is determined by C_i1 and A₄ in Figure 1. The overall transfer function follows the LFP function at low frequencies and the HFP function at high frequencies, and thus is not affected by the notch of the chopper frequency in the RRL. When the transconductance of A₂ is G_m1, the frequency response of the proposed multi-path operational amplifier is seen as the first-order frequency response, so unit gain bandwidth (UGBW) can be expressed as Equation (8). The simulation results show that the UGBW of the proposed multi-path operational amplifier is 2.2 MHz.

$$\mathrm{U}\mathrm{G}\mathrm{B}\mathrm{W}=\frac{{\mathrm{G}}_{\mathrm{m}}{}_1}{2\mathsf{\pi }{\mathrm{C}}_{\mathrm{m}1}}$$

(8)

2.6. Residual Input Offset

In the case of LFP, the offset and 1/f noise were suppressed using the chopper and RRL. Depending on the ripple suppression factor F, the residual ripple can ideally be removed completely. In the case of HFP, since there is no chopper that suppresses the offset, the input offset is shown as the residual input offset. In terms of residual input offset, the offset V_os1 of A₁ can be expressed as Equation (9) when the gain of HFP is A_HFP and the gain of LFP is A_LFP [14].

$${\mathrm{V}}_{\mathrm{r}\mathrm{e}\mathrm{s}\mathrm{i}\mathrm{d}\mathrm{u}\mathrm{a}\mathrm{l}\_\mathrm{i}\mathrm{n}\mathrm{p}\mathrm{u}\mathrm{t}\_\mathrm{o}\mathrm{f}\mathrm{f}\mathrm{s}\mathrm{e}\mathrm{t}1}\approx \frac{{\mathrm{A}}_{\mathrm{H}\mathrm{F}\mathrm{P}}}{{\mathrm{A}}_{\mathrm{L}\mathrm{F}\mathrm{P}}}{\mathrm{V}}_{\mathrm{o}\mathrm{s}1}$$

(9)

The offset V_os3 of A₃ also affects the residual input offset. V_os3 is represented by a square wave by chopper ch2 and parasitic capacitor C_{p3_1-3}. The current to charge and discharge C_{p3_1-3} requires an input AC voltage of A₂ [14]. This AC voltage becomes the DC voltage via chopper ch1 and appears as the residual input offset, which can be expressed as

$${\mathrm{V}}_{\mathrm{r}\mathrm{e}\mathrm{s}\mathrm{i}\mathrm{d}\mathrm{u}\mathrm{a}\mathrm{l}\_\mathrm{i}\mathrm{n}\mathrm{p}\mathrm{u}\mathrm{t}\_\mathrm{o}\mathrm{f}\mathrm{f}\mathrm{s}\mathrm{e}\mathrm{t}2}\approx \frac{4{\mathrm{V}}_{\mathrm{o}\mathrm{s}3}{\mathrm{f}}_{\mathrm{c}\mathrm{h}}{\mathrm{C}}_{\mathrm{p}3}}{{\mathrm{G}}_{\mathrm{m}2}}$$

(10)

$$\mathrm{w}\mathrm{h}\mathrm{e}\mathrm{r}\mathrm{e},{\mathrm{C}}_{\mathrm{p}3}={\mathrm{C}}_{\mathrm{p}3\_2}+\frac{{\mathrm{C}}_{\mathrm{p}3\_1}+{\mathrm{C}}_{\mathrm{p}3\_3}}{2}$$

(11)

Chopper ch2 consists of 4 CMOS switches, as shown in Figure 8. Switching errors occur due to clock feedthrough caused by a mismatch of parasitic capacitors C_{p_ch21} and C_{p_ch23} in chopper ch2, which is seen as input offset [14]. C_{p_ch21} and the C_{p_ch23} are parasitic capacitors generated between the input of chopper ch2 and the switch gate. V_clk is the voltage of the clock signal. The residual input offset can be expressed as

$${\mathrm{V}}_{\mathrm{r}\mathrm{e}\mathrm{s}\mathrm{i}\mathrm{d}\mathrm{u}\mathrm{a}\mathrm{l}\_\mathrm{i}\mathrm{n}\mathrm{p}\mathrm{u}\mathrm{t}\_\mathrm{o}\mathrm{f}\mathrm{f}\mathrm{s}\mathrm{e}\mathrm{t}3}\approx \frac{2\Delta {\mathrm{C}}_{\mathrm{p}\_\mathrm{c}\mathrm{h}2}{\mathrm{V}}_{\mathrm{c}\mathrm{l}\mathrm{k}}{\mathrm{f}}_{\mathrm{c}\mathrm{h}}}{{\mathrm{G}}_{\mathrm{m}2}}$$

(12)

$$\mathrm{w}\mathrm{h}\mathrm{e}\mathrm{r}\mathrm{e},\Delta {\mathrm{C}}_{\mathrm{p}\_\mathrm{c}\mathrm{h}2}={\mathrm{C}}_{\mathrm{p}\_\mathrm{c}\mathrm{h}21}-{\mathrm{C}}_{\mathrm{p}\_\mathrm{c}\mathrm{h}23}$$

(13)

3. Measurement Results

3.1. Chip Die and Measurement Environment

The proposed multi-path operational amplifier was fabricated using a standard 0.18-µm CMOS process. Figure 9 shows the die photograph and measurement environment of the proposed operational amplifier. The power consumption of the proposed low-noise operational amplifier is 0.174 mW with a 1.8-V supply and an active area of 1.18 mm². The fabricated chip was connected to a printed circuit board for circuit performance measurements. A waveform generator provided clock and other input signals, and signal acquisition and data analysis were performed using a digital oscilloscope. A dynamic signal analyzer was used to analyze the spectrum.

3.2. Measurement Results

The sine wave input and output and pulse wave input and output results for the buffer operation of the proposed multi-path operational amplifier are shown in Figure 10. The x-axis of (a) is 400-µs scale, the y-axis is 200-mV scale, and the x-axis of (b) is 2-µs scale, the y-axis is 50-mV scale. The red wave is the input and the blue wave is the output of the amplifier. Sinusoidal and pulse waves with an amplitude of 100 mV were applied using a 50-pF capacitive load. For the pulse response, the rise time was 1.15 µs.

The slew rate measurement results are shown in Figure 11. The red wave is the input and the blue wave is the output of the amplifier. The proposed multi-path operational amplifier exhibits a slew rate of 0.86 V/µs when a 1 V amplitude pulse wave is applied.

$$\mathrm{S}\mathrm{l}\mathrm{e}\mathrm{w}\_\mathrm{R}\mathrm{a}\mathrm{t}\mathrm{e}=\frac{\mathrm{d}{\mathrm{V}}_{\mathrm{o}}}{\mathrm{d}\mathrm{t}}=\frac{1\mathrm{V}}{1.15\mathsf{\mu }\mathrm{s}}=0.86\mathrm{V}/\mathsf{\mu }\mathrm{s}$$

(14)

Figure 12 shows the open loop gain measurement result of the proposed multi-path operational amplifier. The proposed operational amplifier has a gain of 135 dB at 1 Hz and exhibits a first-order frequency response. The proposed operational amplifier has a gain of 50 dB at 10 kHz and a unit gain bandwidth (UGBW) of 3.16 MHz. Compared with the simulation results in Figure 7, similar values are measured.

Figure 13 shows the common mode rejection ratio (CMRR) and power supply rejection ratio (PSRR) measurements of the proposed multi-path operational amplifier. The proposed operational amplifier has a CMRR of 125 dB at 1 Hz and a PSRR of 100 dB at 1 Hz. The minimum values of the CMRR and PSRR are 69.8 dB and 71.7 dB.

Figure 14 shows the results of the input referred offset measurement of the proposed multi-path amplifier. The input referred offset measurement shows that the average input offset is 1.99 µV and peak-to-peak offset is 3.73 µV.

The noise measurement results of the proposed multi-path operational amplifier for a bandwidth of 0.5–200 Hz are shown in Figure 15. Figure 15a shows the input referred noise of the proposed operational amplifier. The measured input referred noise is 47.8 nV/√Hz at 1 Hz and 10.8 nV/√Hz at 200 Hz. Figure 15b shows a noise histogram at 200 Hz for 10 samples. The average value of the input referred noise at 200 Hz for the 10 samples is 11.8 nV/√Hz.

4. Discussion

A performance comparison with previous low-noise amplifier studies is shown in

Table 1. Performance comparison: summary of measured parameters.

	This Work	[5]	[10]	[16]	[17]	[18]	[19]	[20]	[21]
Technology (µm)	0.18	0.18–0.5	0.7	0.7	0.3–0.6	0.35	0.18	0.18	0.32
Multi-path	Y	N	N	Y	N	Y	N	N	N
Power (µW)	174	25.9	1150	715	27	3675	74	3.24	561
DC gain	>137	168	-	100	>130	150	100	-	201.2
UGBW *	3.16M	260k	800k	1.8M	350k	4M	2k	-	40k
CMRR (dB)	>125	124	>120	137	-	-	>120	100	>120
PSRR (dB)	>100	120	>120	120	-	-	-	>70	115
Input referred offset (µV)	1.99	2	5	1	3	0.78	1.78	-	2
Input referred noise (nV/√Hz)	11.8	37	15	10.5	55	5.9	1.8	45.9	18
Chip Area (mm2)	1.18	1.14	4.8	1.8	0.7	1.26	0.12	0.2	0.57
NEF **	4.4	5.5	8.8	4.8	8.1	8.4	17	2.37	10.6

UGBW * = unit gain bandwidth, NEF ** = V_ni√(2∙I_tot/π∙U_T∙4kT∙BW).

. When V_ni is the input referred noise and I_tot is the total consumption current of the operational amplifier, the NEF of the performance comparison can be obtained from Equation (15) [15]. The proposed low-noise chopper-stabilized multi-path operational amplifier achieves a current consumption of 96.7 µA with a 1.8 V power supply, UGBW of 3.16 MHz, and input referred noise of 11.8 nV/√Hz, resulting in a NEF of 4.46.

$$\mathrm{N}\mathrm{E}\mathrm{F}={\mathrm{V}}_{\mathrm{n}\mathrm{i}}\cdot \sqrt{\frac{2{\mathrm{I}}_{\mathrm{t}\mathrm{o}\mathrm{t}}}{\mathsf{\pi }\cdot {\mathrm{U}}_{\mathrm{T}}\cdot 4\mathrm{k}\mathrm{T}\cdot \mathrm{B}\mathrm{W}}}$$

(15)

Because of the multi-path architecture, the proposed multi-path operational amplifier is relatively large in size and power consumption, but has a low input referred noise and wide bandwidth, so its NEF is better than previous studies.

5. Conclusions

This paper has presented a low-noise chopper-stabilized multi-path operational amplifier with nested Miller compensation for high-precision sensors. The proposed multi-path operational amplifier removes the offset, flicker noise, and ripple by applying a chopper stabilization technique and RRL, and enables wide bandwidth operation using a multi-path structure. Nested Miller compensation is applied to obtain the frequency response of a clean first-order system. The proposed multi-path operational amplifier was fabricated using a standard 0.18-µm CMOS process and an active area of 1.18 mm². The power consumption is 0.174 mW with a 1.8 V power supply. It achieves a slew rate of 0.86 V/ µs, >137 dB open loop gain, >125 dB CMRR, and >100 dB PSRR. The NEF of 4.46 was obtained based on the achieved input referred noise of 11.8 nV/√Hz and UGBW of 3.16 MHz. The proposed low-noise multi-path operational amplifier has a good NEF and is suitable for precision sensor applications.