A 90–100 GHz SiGe BiCMOS 6-Bit Digital Phase Shifter with a Coupler-Based 180° Unit for Phased Arrays

Abstract

This paper presents a 90–100 GHz wideband digital phase shifter with a fine resolution of 5.625°, implemented in a 0.13 μm SiGe BiCMOS process. A switch-type architecture with six cascaded units, including a novel 180° cell based on a broadband coupler, enables full 0–360° phase coverage while improving phase accuracy, bandwidth, and process robustness. Post-layout simulations demonstrate an insertion loss below 15.5 dB, an RMS phase error under 2.3°, and an RMS amplitude error better than 0.9 dB across the 90–100 GHz band. The total chip area, including test pads, is 0.39 mm², making the design compact and well suited for high-density phased-array applications.

1. Introduction

W-band (75−110 GHz) holds significant potential for applications in wireless communications, radar detection, and biomedical imaging due to its abundant spectral resources, large available bandwidth, and low atmospheric attenuation [1,2,3]. However, at W-band frequencies, millimeter-wave (mm-wave) circuits face several challenges, including pronounced parasitic effects, high losses, degraded noise figure, limited output power, and more. Phased array antenna technology provides an effective solution to these issues by enhancing signal-to-noise ratio through signal combining and enabling agile beamforming and scanning. Phase shifters play a critical role in phased array systems by adjusting the phase of each antenna element, thereby enabling precise beam steering in various directions. With the advancement of silicon-based processes, SiGe BiCMOS technology has emerged as a promising solution for mm-wave systems, offering CMOS logic compatibility and cost-effective mass production.

Common types of phase shifters include reflective phase shifters (RPS) [4,5,6,7], vector-sum phase shifters (VMPS) [8,9,10], and switch-type phase shifters (STPS) [11,12,13]. A RPS typically consists of a quadrature coupler and two tunable loads. The phase difference between the input and isolated ports is controlled by tuning the impedances of the through and coupled ports. However, impedance matching constraints often limit the tuning range. VMPS, which comprise I/Q signal generators, amplitude control, and logic modules, achieve phase shifts by adjusting the I/Q amplitude ratio. However, they suffer from limited linearity, temperature-sensitive phase errors, and unidirectional operation, restricting their applicability [10,14]. STPS rely on LC filter networks and switching transistors to toggle between reference and phase-shifted states [11,15]. Compared to RPS and VMPS, STPS offer high linearity, wide bandwidth, precise phase shifts, and zero static power consumption, making them well-suited for mm-wave phased arrays [15,16,17,18,19].

Among these, the 180° phase shifter unit is the most critical component in an STPS, as it has the largest phase shift and has a significant impact on phase accuracy, amplitude variation, and bandwidth. Several 180° STPS structures have been proposed, including low-pass π-type, differential inversion-type, and high/low-pass type structures. The low-pass π-type, which cascades two 90° units, is simple and wideband but incurs larger chip area and amplitude/phase errors [14,17]. The differential inversion-type structure, suitable only for differential architectures, inverts phase by controlling switching transistors, but its performance is sensitive to input impedance and parasitic effects [11]. High/low-pass structures use phase-leading and lagging networks, switched to produce a 180° phase difference. While offering high accuracy and simplicity, they suffer from limited bandwidth and reduced robustness due to parasitic effects and process variations at higher frequencies [20,21,22,23,24].

In this work, we present a W-band 6-bit switched-type phase shifter implemented in a 0.13 μm SiGe BiCMOS process. The proposed 180° unit adopts a coupler-based low-pass architecture, replacing the conventional LC high-pass network with a broadband coupler. This approach improves phase accuracy, extends bandwidth, and enhances robustness against process variations. Simulation results demonstrate that the proposed phase shifter achieves a 360° phase shift range with 5.625° resolution, an RMS phase error below 2.3°, and an RMS amplitude error below 0.9 dB across 90−100 GHz. The rest of this article is organized as follows. Section 2 describes the analysis and design of the proposed shifter unit with the proposed broadband coupler. Section 3 presents and analyzes the circuit design. The simulated results that verify the design method are discussed in Section 4. Finally, the paper is concluded in Section 5.

2. 180° Phase Shifter with a Broadband Coupler

2.1. A. Design of Broadband Coupler

A broadband coupler is employed to implement a broadband 180° phase-shifted unit instead of the high-pass network in the conventional high-low-pass type structure. The proposed coupler was designed using a 0.13 μm SiGe BiCMOS process. A schematic cross-section of this process is shown in Figure 1a, which includes five thin metal layers (M1 to M5) and two thick metal layers (LY and AM). In addition, the substrate’s height, dielectric constant, and conductivity are 82 µm, 11.9, and 7.41 S/m, respectively.

The three-dimensional physical structure model of the broadband coupler is shown in Figure 1b. It mainly consists of two vertical metal vias, which are cross connected through the top metal layer AM and the sub-top metal layer LY. On both sides, there are two pairs of coupled transmission lines composed of AM and LY. Additionally, a rectangular defective ground plane is formed using the metal layer M1. In this structure, the coupled line composed of the sub-top metal LY is connected to the defective ground plane M1 through vertical metal vias. The physical length of the coupled line is a quarter wavelength, corresponding to an operating frequency of 95 GHz. Moreover, the defective ground plane alters the electric and magnetic field distributions around the coupled line. By adjusting the dimensions of the defective plane, the distributed inductance and capacitance of the coupler can be tuned, thereby offering an additional degree of freedom in coupler design [25].

As shown in Figure 2, an equivalent circuit model of the proposed broadband coupler is developed using passive lumped elements, including resistance (R), inductance (L), and capacitance (C). This model enables effective evaluation of the coupler’s electrical performance when co-simulated with other circuit modules. Parts 1–4 consist of inductors L₁–L₄ and L₆–L₉ modeling the two coupled transmission lines AM and LY, respectively. R₁ and L₅ characterize the parasitic inductance and resistance introduced by the vertical metal via holes in Part 5. Capacitors C₁ and C₂ represent the coupling capacitances introduced by the AM and LY coupled transmission lines between Part 1 and Part 3, and between Part 2 and Part 4, respectively. K₁₂ and K₃₄ denote the coupling coefficients between Part 1 and Part 2, and between Part 3 and Part 4, respectively. C₃ and R₂ model the parasitic capacitance and resistance introduced by the vertical metal through-hole between the transmission line LY and the metal layer M1. They also account for substrate losses in Parts 3 & 4.

The simulated S-parameters and phase response of the equivalent circuit model are compared with the electromagnetic (EM) simulation results of the three-dimensional physical model, as illustrated in Figure 3. Within the frequency range of 70–120 GHz, the coupler demonstrates high-pass-like phase progression characteristics, with the transmission phase varying from 15° to 90°. The insertion loss (|S₂₁|) ranges from approximately 0.8 to 1.5 dB, while the return loss (|S₁₁|/|S₂₂|) exceeds 19 dB.

The simulated S-parameters and phase responses derived from the equivalent circuit model exhibit excellent agreement with those obtained from full-wave EM simulations of the 3D structure. This consistency verifies the accuracy of the proposed equivalent model in predicting the coupler’s performance, facilitating further optimization of broadband coupler design. The final values of the lumped elements used in the equivalent circuit model, optimized using Advanced Design System (ADS), are summarized in

Table 1. Parameter values of the components of the equivalent circuit.

L1	L2	L3	L4	L5
120 pH	115 pH	92 pH	92 pH	15 pH
L6	L7	L8	L9	R1
38 pH	39 pH	44 pH	43 pH	2.4 ohm
R2	C1	C2	C3	K12, K34
2.4 ohm	24.9 fF	2.7 fF	12.8 fF	0.77

.

2.2. B. Analysis of a Coupler-Based Low-Pass 180° Phase Shifter Unit

To improve phase accuracy and robustness in wideband applications, a coupler–low-pass configuration is adopted for the 180° phase-shifting unit. This section presents a detailed theoretical analysis comparing the proposed structure to the conventional high-/low-pass phase shifter. Figure 4a and Figure 4b illustrate the conventional high-/low-pass phase shifter structure and the proposed coupler–based low-pass configuration, respectively. The corresponding simplified equivalent circuit models for both implementations are also shown. In these models, the normalized impedances of the inductors and capacitors are denoted as X₀, X₁, and X₂, while the normalized admittances are represented by B₀, B₁, B₂, B₃, and B_m.

In the conventional high-/low-pass configuration, when the input and output ports are ideally matched to 50 Ω, the phase difference between the high-pass and low-pass networks can be expressed as

$$△{\varphi }_1 = {\tan }^{-1}\left({\displaystyle \frac{2X_0}{X_0^2 - 1}}\right) + {\tan }^{-1}\left({\displaystyle \frac{2X_1}{X_1^2 - 1}}\right)$$

(1)

Here, the impedance and admittance components are defined as

$$X_0 = \tan \left({\displaystyle \frac{{\varphi }_l}{2}}\right),X_1 = \tan \left({\displaystyle \frac{{\varphi }_h}{2}}\right), B_0 = \sin {\varphi }_l, B_1 = \sin {\varphi }_h$$

(2)

Taking the derivative of (1) with respect to angular frequency ω, the phase frequency slope becomes:

$${\displaystyle \frac{d△{\varphi }_1}{d\omega }} = {\displaystyle \frac{2X_1}{\omega \left(X_1^2 + 1\right)}} - {\displaystyle \frac{2X_0}{\omega \left(X_0^2 + 1\right)}}$$

(3)

For the proposed coupler–low-pass structure, the equivalent transmission matrix [ABCD] of the coupler is expressed as

$$\left[\begin{array}{cc}A& B\\ C& D\end{array}\right] = \left[\begin{array}{cc}{\displaystyle \frac{B_2}{B_m}}& {\displaystyle \frac{j\left(B_m^2 - B_2^2\right)}{B_m}}\\ {\displaystyle \frac{j}{B_m}}& {\displaystyle \frac{B_2}{B_m}}\end{array}\right] = \left[\begin{array}{cc}k& {\displaystyle \frac{j\left(1 - k^2\right)B_2}{k}}\\ {\displaystyle \frac{jk}{B_2}}& k\end{array}\right]\left(B_m = {\displaystyle \frac{1}{k}}{B}_2\right)$$

(4)

Assuming ideal matching, the phase difference between the low-pass and coupler paths becomes:

$$△{\varphi }_2 = {\tan }^{-1}\left({\displaystyle \frac{1}{B_2}}\right) + {\tan }^{-1}\left({\displaystyle \frac{2X_2}{X_2^2 - 1}}\right)$$

(5)

Its corresponding phase–frequency slope is

$${\displaystyle \frac{d△{\varphi }_2}{d\omega }} = {\displaystyle \frac{B_2}{\omega \left(B_2^2 + 1\right)}} - {\displaystyle \frac{2X_2}{\omega \left(X_2^2 + 1\right)}}$$

(6)

When the following condition is satisfied:

$$X_0 = X_2, B_2 = {\displaystyle \frac{1}{X_1}}$$

(7)

The slope difference between the two-phase curves is

$${\displaystyle \frac{d△{\varphi }_2}{d\omega }} - {\displaystyle \frac{d△{\varphi }_1}{d\omega }} = {\displaystyle \frac{B_2}{\omega \left(B_2^2 + 1\right)}} - {\displaystyle \frac{2X_1}{\omega \left(X_1^2 + 1\right)}} = -{\displaystyle \frac{X_1}{\omega \left(X_1^2 + 1\right)}} < 0$$

(8)

Equation (8) reveals that, under identical frequency and component conditions, the coupler–low-pass structure exhibits a lower phase–frequency slope than the conventional counterpart, resulting in a flatter phase response.

To balance insertion loss and amplitude variation, the optimized target phase shifts are set to 120° for the lagging low-pass path and approximately 60° for the leading high-pass path (including both the third-order high-pass filter and the coupler). As shown in Figure 5, the proposed 180° phase shifter achieves a variation of only 3.6° (178.3–181.9°) across 80–110 GHz, compared to 8.1° (176.6–184.7°) for the conventional structure, thus demonstrating significantly improved phase accuracy and bandwidth performance.

Moreover, process variations have an increasing impact at millimeter-wave frequencies due to smaller passive component dimensions. Figure 6 compares phase responses under ±5% and ±10% variation in component values. Simulation results show that the proposed design limits the phase error to 27°, whereas the conventional structure exhibits a maximum deviation of 37°, yielding a 27% improvement in robustness.

3. W-Band 6-Bit Digital Phase Shifter Implementation

The proposed W-band 6-bit digitally controlled phase shifter is composed of six cascaded unit cells providing discrete phase shifts of 5.625°, 11.25°, 22.5°, 45°, 90°, and 180°, respectively, as shown in Figure 7. Specifically, the 180° phase-shifting unit employs the proposed coupler–low-pass structure, the 5.625° unit uses a capacitor-loaded topology, and the remaining units adopt low-pass π-type configurations.

In general, each phase-shifting cell exhibits different input and output impedance characteristics in the reference and shifted states, and larger phase-shift units tend to introduce more severe impedance mismatches. To reduce impedance mismatch during phase-state switching, the 180° and 90° units are placed at both ends of the cascaded chain, while the smaller phase-shift units are arranged such that adjacent cells exhibit similar impedance transition profiles. Based on this design principle, the optimized cascade sequence is 180°-11.25°-22.5°-5.625°-45°-90°.

By independently toggling the six digital control signals D₀, D₁, D₂, D₃, D₄, and D₅ (corresponding to the 5.625°, 11.25°, 22.5°, 45°, 90°, and 180° bits, respectively) between 0 V and 1.2 V, the phase shifter achieves a 0–360° continuous tuning range with a least significant phase step of 5.625°. A total of 2⁶ = 64 discrete phase states are realized with this configuration.

In order to achieve more accurate performance of the proposed phase shifter, a 3-D physical model that incorporates all passive components—including couplers, inductors, capacitors, transmission lines, vias, interconnects, and other passive structures—was constructed in a full-wave electromagnetic (EM) simulator high-frequency structure simulator (HFSS), as shown in Figure 8. The passive structures were carefully optimized using the 3-D EM simulations, and then co-simulated together with the active devices to ensure precise circuit-level performance. The final design parameters of key devices, including transistor dimensions and critical passive components, are summarized in

Table 2. Key device parameter values for W-band phase shifter.

Q1,2,3,4 (W/L)	Q5,6,7,8 (W/L)	Q9 (W/L)	Q10 (W/L)	Q11 (W/L)	Q12 (W/L)
120 nm/8 µm	120 nm/1 µm	120 nm/4 µm	120 nm/17 µm	120 nm/2.5 µm	120 nm/12 µm
Q13 (W/L)	Q14 (W/L)	Q15 (W/L)	Q16 (W/L)	Q17 (W/L)	R0
120 nm/3 µm	120 nm/6 µm	120 nm/18 µm	120 nm/4 µm	120 nm/6 µm	5.7 k ohm
L0	L1	L2	L3	L4	L5
75 pH	63 pH	20 pH	65 pH	36 pH	72 pH
L6	L7	L8	L9	L10	L11
45 pH	77 pH	70 pH	85 pH	70 pH	65 pH
C0	C1,2	C3,4	C5	C6,7	C8,9
9 fF	5 fF	6 fF	5 fF	13 fF	17 fF

Note: W = emitter width of the HBT; L = emitter length of the HBT.

.

The chip implementation of the phase shifter was carried out in a 0.13 μm SiGe BiCMOS process. Figure 9 shows the layout of the W-band 6-bit phase shifter. Bond pads D₀–D₅ correspond to the control pads for the 5.625°, 11.25°, 22.5°, 45°, 90°, and 180° phase-shift units, each pad having dimensions of 100 µm × 100 µm. Ground–signal–ground (GSG) pads are used at both the input and output ends for the millimeter-wave signals. The overall die size, including all test pads, is 925 µm × 420 µm.

4. Results and Discussion

Based on this co-simulation framework, the post-layout simulation results and performance evaluation of the proposed W-band 6-bit digitally controlled phase shifter are presented below.

The phase–frequency response curves for all 64 states of the proposed 6-bit digital phase shifter are presented in Figure 10a. Across the target frequency range of 90–100 GHz, the curves exhibit no overlap, and the phase steps are uniformly distributed from 0° to 360° with a resolution of 5.625°, demonstrating precise and monotonic phase control. As illustrated in Figure 10b, the insertion loss (|S₂₁|) ranges from 12 dB to 15.5 dB across all phase states, with a peak-to-peak amplitude variation of only ±1.75 dB relative to the reference state. The phase shifter also exhibits excellent broadband impedance matching, with both input return loss (|S₁₁|) and output return loss (|S₂₂|) exceeding 11 dB for all states, as shown in Figure 11.

To provide a clearer view of the tuning capability, Figure 12 summarizes the phase steps across all states at the center frequency of 95 GHz. Each dot corresponds to the relative phase shift and amplitude variation with respect to the reference state. The results show that the proposed design achieves a complete 360° phase coverage, while the amplitude variation across all phase states is tightly constrained within 0.23 dB, demonstrating excellent phase resolution and amplitude consistency.

Thanks to the proposed coupler–low-pass structure employed in the 180° phase-shifting unit, the phase shifter achieves excellent linearity and amplitude consistency. As shown in Figure 13, the root-mean-square (RMS) phase error ranges from 1.5° to 2.3°, and the RMS amplitude error varies from 0.6 dB to 0.9 dB over the 90–100 GHz band. In contrast, conventional high-/low-pass-based 180° phase shifters exhibit significantly worse performance, with RMS phase error ranging from 1.9° to 2.7° and RMS amplitude error from 0.6 dB to 1.8 dB. Overall, the proposed W-band phase shifter achieves a 15% reduction in RMS phase error and a 50% reduction in RMS amplitude error compared to the conventional design, validating the efficacy of the coupler-assisted topology for broadband high-resolution phase control.

We further performed post-layout simulations under operating voltage and environment temperature variations to validate the robustness of the proposed design. Specifically, (1) ±10% control voltage variation and (2) a wide temperature ranges from –55 °C to 85 °C were considered. As shown in Figure 14, the RMS amplitude error remains below 1.2 dB under these conditions, indicating strong robustness against voltage and temperature variations. However, as depicted in Figure 15, the RMS phase error degrades at high temperature, reaching 6.1° at 85 °C, mainly due to the increased ON-resistance of the HBT switch, which is inherently temperature-dependent.

To mitigate this limitation, an adaptive control voltage scheme is proposed to stabilize the ON-resistance against temperature variation. This method has been validated in our prior work [26]. As shown in Figure 14, applying a 2.5 V adaptive control voltage significantly improves the high-temperature performance, reducing the RMS phase error at 85 °C to better than 2.65°.

The performance metrics of the proposed W-band phase shifter chip are summarized in

Table 3. Performance summary and comparison with state-of-the-art phase shifters.

	[14]	[11]	[12]	[16]	[15]	★ This Work
Process	90 nm CMOS	65 nm CMOS	65 nm CMOS	130 nm BiCMOS	32 nm CMOS SOI	130 nm BiCMOS
Frequency (GHz)	57~66	75~85	90~100	92~100	94~96	90~100
Insertion Loss (dB)	16~19	22~27	16~20	23~26	17~18	12~15.5
Phase Range (°)/Bits	360/4	360/4	360/6	360/5	360/5	360/6
RMS phase error (°)	<5	<11.25	<11	<5	<6	<2.3
RMS amplitude error (dB)	<0.5	<1.4	N/A	<1.8	<1	<0.9
Chip Size (mm2)	0.17	0.12	0.19	0.85	0.7	0.39

^★ post-layout simulated results.

and compared with those of recently reported silicon-based millimeter-wave phase shifters. The results demonstrate that the proposed design delivers excellent overall performance across multiple dimensions, achieving low insertion loss, high phase accuracy, and low RMS amplitude error. In particular, the incorporation of the coupler-based 180° phase-shifting unit significantly enhances both phase accuracy and process tolerance. Although Reference [6] reports the lowest RMS amplitude error among the listed works, its operating frequency lies in the V-band (50–75 GHz), which imposes fewer design challenges than the W-band. In contrast, the proposed design maintains highly competitive performance under more demanding high-frequency conditions, validating its suitability for next-generation high-resolution phased array applications.

5. Conclusions

A 90–100 GHz 6-bit digital phase shifter has been presented in this paper, implemented using a 0.13 μm SiGe BiCMOS process. A novel coupler–low-pass-based 180° phase-shifting unit is introduced to replace the conventional high-/low-pass topology, significantly reducing phase and amplitude errors while improving robustness against process variations. Post-layout simulation results demonstrate that the proposed phase shifter achieves a full 0–360° phase tuning range with a fine resolution of 5.625°, insertion loss below 15.5 dB, RMS phase error under 2.3°, and RMS amplitude error better than 0.9 dB across the entire 90–100 GHz frequency band. The total chip area, including all test pads, is only 0.39 mm², highlighting its suitability for compact, high-density phased array systems in advanced W-band applications.

To further validate the proposed architecture, chip fabrication and on-wafer measurements are planned as part of our future work. These results will provide experimental verification of the design and confirm its applicability in practical W-band phased-array systems.