Design and Simulation Analysis of a 3TnC MLC FeRAM Using a Nondestructive Readout and Offset-Canceled Sense Amplifier for High-Density Storage Applications

Hf_0.5Zr_0.5O₂-based multi-level cell (MLC) ferroelectric random-access memory (FeRAM) has great potential for high-density storage applications. However, it is usually limited by the issues of a small operation margin and a large input offset. The study of circuit design and optimization for MLC FeRAM is necessary to solve these problems. In this work, we propose and simulate a configuration for a Hf_0.5Zr_0.5O₂-based 3TnC MLC FeRAM macro circuit, which also presents a high area efficiency of 12F² for each bit. Eight polarization states can be distinguished in a single fabricated Hf_0.5Zr_0.5O₂-based memory device for potential MLC application, which is also simulated by a SPICE model for the subsequent circuit design. Therein, a nondestructive readout approach is adopted to expand the reading margin to 450 mV between adjacent storage levels, while a capacitorless offset-canceled sense amplifier (SA) is designed to reduce the offset voltage to 20 mV, which improves the readout reliability of multi-level states. Finally, a 4 Mb MLC FeRAM macro is simulated and verified using a GSMC 130 nm CMOS process. This study provides the foundation of circuit design for the practical fabrication of a Hf_0.5Zr_0.5O₂-based MLC FeRAM chip in the future, which also suggests its potential for high-density storage applications.