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Volume 11
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10.3390/mi11080741
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Correction published on 30 April 2025, see Micromachines 2025, 16(5), 537.
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Article

Single-Grain Gate-All-Around Si Nanowire FET Using Low-Thermal-Budget Processes for Monolithic Three-Dimensional Integrated Circuits

by
Tung-Ying Hsieh
1,2,
Ping-Yi Hsieh
3,
Chih-Chao Yang
3,*,
Chang-Hong Shen
3,
Jia-Min Shieh
3,
Wen-Kuan Yeh
3 and
Meng-Chyi Wu
1
1
Institute of Electronics Engineering, National Tsing Hua University, Hsinchu 30013, Taiwan
2
National Applied Research Laboratories, 3F, No. 106, Ho Ping E. Rd., Sec. 2, Taipei City 10622, Taiwan
3
Taiwan Semiconductor Research Institute, No. 26, Prosperity Road 1, Hsinchu 30013, Taiwan
*
Author to whom correspondence should be addressed.
Micromachines 2020, 11(8), 741; https://doi.org/10.3390/mi11080741
Submission received: 4 July 2020 / Revised: 28 July 2020 / Accepted: 30 July 2020 / Published: 30 July 2020 / Corrected: 30 April 2025
(This article belongs to the Special Issue Monolithic 3D Chips)
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Abstract

We introduce a single-grain gate-all-around (GAA) Si nanowire (NW) FET using the location-controlled-grain technique and several innovative low-thermal budget processes, including green nanosecond laser crystallization, far-infrared laser annealing, and hybrid laser-assisted salicidation, that keep the substrate temperature (Tsub) lower than 400 °C for monolithic three-dimensional integrated circuits (3D-ICs). The detailed process verification of a low-defect GAA nanowire and electrical characteristics were investigated in this article. The GAA Si NW FETs, which were intentionally fabricated within the controlled Si grain, exhibit a steeper subthreshold swing (S.S.) of about 65 mV/dec., higher driving currents of 327 µA/µm (n-type) and 297 µA/µm (p-type) @ Vth ± 0.8 V, and higher Ion/Ioff (>105 @|Vd| = 1 V) and have a narrower electrical property distribution. In addition, the proposed Si NW FETs with a GAA structure were found to be less sensitive to Vth roll-off and S.S. degradation compared to the omega(Ω)-gate Si FETs. It enables ultrahigh-density sequentially stackable integrated circuits with superior performance and low power consumption for future mobile and neuromorphic applications.
Keywords: monolithic 3D; gate-all-around; nanowire FET; low-thermal budget; location-controlled-grain; laser crystallization; laser activation; laser-assisted salicidation; low power consumption monolithic 3D; gate-all-around; nanowire FET; low-thermal budget; location-controlled-grain; laser crystallization; laser activation; laser-assisted salicidation; low power consumption

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MDPI and ACS Style

Hsieh, T.-Y.; Hsieh, P.-Y.; Yang, C.-C.; Shen, C.-H.; Shieh, J.-M.; Yeh, W.-K.; Wu, M.-C. Single-Grain Gate-All-Around Si Nanowire FET Using Low-Thermal-Budget Processes for Monolithic Three-Dimensional Integrated Circuits. Micromachines 2020, 11, 741. https://doi.org/10.3390/mi11080741

AMA Style

Hsieh T-Y, Hsieh P-Y, Yang C-C, Shen C-H, Shieh J-M, Yeh W-K, Wu M-C. Single-Grain Gate-All-Around Si Nanowire FET Using Low-Thermal-Budget Processes for Monolithic Three-Dimensional Integrated Circuits. Micromachines. 2020; 11(8):741. https://doi.org/10.3390/mi11080741

Chicago/Turabian Style

Hsieh, Tung-Ying, Ping-Yi Hsieh, Chih-Chao Yang, Chang-Hong Shen, Jia-Min Shieh, Wen-Kuan Yeh, and Meng-Chyi Wu. 2020. "Single-Grain Gate-All-Around Si Nanowire FET Using Low-Thermal-Budget Processes for Monolithic Three-Dimensional Integrated Circuits" Micromachines 11, no. 8: 741. https://doi.org/10.3390/mi11080741

APA Style

Hsieh, T.-Y., Hsieh, P.-Y., Yang, C.-C., Shen, C.-H., Shieh, J.-M., Yeh, W.-K., & Wu, M.-C. (2020). Single-Grain Gate-All-Around Si Nanowire FET Using Low-Thermal-Budget Processes for Monolithic Three-Dimensional Integrated Circuits. Micromachines, 11(8), 741. https://doi.org/10.3390/mi11080741

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