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Micromachines 2019, 10(11), 722; https://doi.org/10.3390/mi10110722

Article
A Smart Floating Gate Transistor with Two Control Gates for Active Noise Control
School of Electronic Science and Engineering, Nanjing University, Nanjing 210023, China
*
Author to whom correspondence should be addressed.
Received: 16 September 2019 / Accepted: 24 October 2019 / Published: 25 October 2019

Abstract

:
A smart floating gate transistor with two control gates was proposed for active noise control in bioelectrical signal measurement. The device, which is low cost and capable of large-scale integration, was implemented in a standard single-poly complementary metal–oxide–semiconductor (CMOS) process. A model of the device was developed to demonstrate the working principle. Theoretical analysis and simulation results proved the superposition of the two control gates. A series of test experiments were carried out and the results showed that the device was in accordance with the basic electrical characteristics of a floating gate transistor, including the current–voltage (I–V) characteristics and the threshold characteristics observed on the two control gates. Based on the source follower circuit, the experimental results proved that the device can reduce interference by more than 29 dB, which demonstrates the feasibility of the proposed device for active noise control.
Keywords:
floating gate transistor; control gate; CMOS device; active noise control

1. Introduction

There is growing interest in detecting chemical or bioelectrical signals with solid-state sensors in a complementary metal–oxide–semiconductor (CMOS) process [1,2]. One of the major classes of solid-state sensors is based on the field-effect transistor (FET) [3,4,5]. The multiparametric nature and intrinsic signal amplification ability of FETs make them capable of achieving well beyond what is possible with two terminal devices. The ion-sensitive field-effect transistor (ISFET) [6,7] is an important branch of FET and has attracted great research interest regarding chemical signal detection due to its small size, capability of mass fabrication, and fast response time. The organic thin-film transistor (OTFT) [8,9,10] is another meaningful branch and has been extensively studied for bioelectrical signal detection. For example, a sensing platform based on floating gate OTFTs is used for bioelectrical signal sensing [11,12,13,14]. The working principle of a floating gate organic charge-modulated field-effect transistor (OCMFET) is shown in Figure 1a, where the sensing area is part of the floating gate exposed to the surrounding bioelectrochemical environment to detect signals, and the control gate is used to set the working point with the control capacitor, as shown in Figure 1b. Ionic or cell charge variations occurring in close proximity to the sensing area cause a charge separation in the floating gate, which leads to a modulation of the charge carrier density inside the channel of the transistor, as shown in Figure 1c [15]. The OCMFET device can detect signals in the frequency range of cell electrical activity (10–1000 Hz) and can work without any external reference electrode. However, the floating gate and sensing area are integrated as a whole and can only detect charge signals, which is not suitable for detecting voltage signals because the voltage signal on the floating gate fixes the working point of the device. In addition, it is difficult for the device to suppress interference, which is important for small signal detection.
In order to detect voltage signals, some modifications must be made, such as separating the sensing area and the floating gate. Moreover, the detected signal is accompanied by some interference and the interference can also modulate the channel charge. To suppress the interference actively, the active noise control (ANC) concept has been introduced, which cancels the unwanted primary interference by using a secondary source for signal superposition [16,17,18]. Generally, two input ports are required to achieve active noise control, where one input port is used for primary source detection and another for secondary source input [19]. Therefore, we have proposed a smart floating gate transistor with two control gates (called an ANC device), which is characterized by active noise control and a low-cost standard CMOS process.
Firstly, the physical model of the proposed device was developed to demonstrate the working principle, and the layout of the device was implemented in a standard single-poly CMOS process. Secondly, simulation results are illustrated to show the ANC performance based on the proposed device. Finally, the experimental electrical characterizations of the fabricated device are provided, which demonstrate the feasibility of the device for active noise control applications.

2. ANC Device

2.1. Device Structure

The proposed ANC device is based on an evolution of a single-poly metal–oxide–semiconductor field-effect transistor (MOSFET) and the cross section of the proposed ANC device is shown in Figure 2, including a source region (S), a drain region (D), a bulk region (B), a floating gate (FG), and two control gates ( CG 1 and CG 2 ). Two heavily doped N+ regions are generated on a P-type bulk to serve as the source and the drain, and two N- or P-type physically isolated wells are generated beside the bulk to serve as the two control gates CG 1 and CG 2 , respectively. The floating gate is generated by a single-poly layer, which is isolated from the bulk and the two control gates by a dielectric layer. The floating gate overlaps the bulk and the two control gates, which leads to the coupling capacitors. The channel current of the proposed device is controlled with two control gates by the coupling capacitors with the floating gate. In application, control gates CG 1 and CG 2 are connected to two standard PADs to receive voltage signals. The source, drain, and bulk are connected to three standard PADs for the normal working condition setting.

2.2. Device Model

The equivalent schematic diagram of the proposed ANC device is shown in Figure 3a, where C FC 1 , C FC 2 , C S , C D ,   and   C B   are the capacitors between the floating gate and the control gate CG 1 , the control gate CG 2 , the source, the drain, and the bulk region, respectively. Considering that the charge Q of the floating gate should be equal to 0, the simple model of the proposed device is expressed in Equation (1) [20]:
Q = 0 = C F C 1 ( V F G V C G 1 ) + C F C 2 ( V F G V C G 2 ) + C S ( V F G V S ) + C D ( V F G V D ) + C B ( V F G V B )
where V FG is the potential on the floating gate; V CG 1 is the potential on the control gate CG 1 ; V CG 2 is the potential on the control gate CG 2 ; and V S , V D , and V B   are the potentials on the source, the drain, and the bulk, respectively. Defining the total capacitors C T as the sum of the capacitors of C FC 1 , C FC 2 , C S , C D , and C B , the potential on the floating gate due to capacitive coupling can be expressed as
V F G = C F C 1 C T V C G 1 + C F C 2 C T V C G 2 + C S C T V S + C D C T V D + C B C T V B .
For C S and C D being far less than C T , and the bulk being grounded, Equation (2) can be simplified as
V F G = C F C 1 C T V C G 1 + C F C 2 C T V C G 2 .
Generally, CG 1 and CG 2 are equivalent in terms of electrical characteristics and one of them is always set to zero for measurement of the threshold voltage, so the threshold voltages and conductivity factors of the floating gate and control gates CG 1 and CG 2 satisfy the following relationships:
V T F G = C F C 1 C T V T C G 1 = C F C 2 C T V T C G 2
β F G = C T C F C 1 β C G 1 = C T C F C 2 β C G 2
where V T FG is the threshold for the floating gate, V T CG 1 is the threshold for control gate CG 1 , V T CG 2 is the threshold for control gate CG 2 , β FG is the conductivity factor for the floating gate, β CG 1 is the conductivity factor for control gate CG 1 , and β CG 2 is the conductivity factor for control gate CG 2 .
Accordingly, the transformed current–voltage (I–V) equations of the proposed ANC device in the triode region (TR) and the saturation region (SR) can be expressed by
TR   | V D S | < C F C 1 C T | V C G 1 + C FC 2 C F C 1 V C G 2 C T C F C 1 V S V T C G 1 | I D = β C G 1 [ ( V C G 1 + C F C 2 C F C 1 V C G 2 C T C F C 1 V S V T C G ) V D S 1 2 C T C F C 1 V D S 2 ]
SR   | V D S | C F C 1 C T | V C G 1 + C FC 2 C F C 1 V C G 2 C T C F C 1 V S V T C G 1 | I D = β C G 1 2 ( C F C 1 C T ) ( V C G 1 + C F C 2 C F C 1 V C G 2 C T C F C 1 V S V T C G 1 ) 2
which show the relationship between I D and V CG 1 , V CG 2 , V S , and V D . In Equation (7), I D in the saturation region is not affected by V DS , which is greatly convenient for reading the output signal of the ANC device. Assuming I D to be a constant value and the source voltage V S to be the output signal, the signal of the control gate is easily obtained by measuring the output voltage V S . This readout method is called the source follower method, where the voltage of source V S can be expressed by the voltage of two control gates as
V S = C F C 1 C T V C G 1 + C F C 2 C T V C G 2 2 I D β C G 1 ( C F C 1 C T ) C F C 1 C T V T C G 1 .
Normally, one control gate is used to set the DC operation point of the device and works as the secondary source input, and the other control gate is used to detect the effective signal with background interference. The subsequent circuits extract the interference from the output signal V S and actively generate an inverse interference for secondary input. Thus, the secondary interference on one control gate and the primary interference on the other control gate work together to cancel each other and, finally, output the effective signal in V S , with the interference being as small as possible.
According to the equivalent schematic diagram of the proposed ANC device shown in Figure 3a and the standard symbols for MOS transistors, the symbols for the proposed ANC device are shown in Figure 3b, which has five terminals of drain (D), source (S), bulk (B), control gate ( CG 1 ), and control gate ( CG 2 ).

2.3. Device Layout

The proposed ANC device was implemented in a standard 0.18 μm single-poly CMOS process. Figure 4 shows the layout and cross section of the proposed ANC device, where AA is the active area, SN is the N+ implantation for source and drain, SP is the P+ implantation, GT is the polysilicon gate, NW is the N-type well, DNW is the deep N-type well, CT is the contact area, and M1 is the metal one. As shown in Figure 4, two control gates were formed in two N-type wells without special isolation from the P-type bulk. CG 1 is an N-MOSC, while CG 2 is a P-MOSFET with a common source, drain, and substrate. The two different structures both modulated the charges in the floating gate by the coupling capacitors. The coupling capacitor was determined by the overlap area between the floating gate and the control gate. The design parameters of the ANC device are listed in Table 1, where L is the abbreviation for the length and W is the abbreviation for the width of the areas shown in Figure 4a.

3. Simulation Results

A simulation schematic based on the proposed ANC device is shown in Figure 5. The device is equivalent to a standard MOSFET M 0 and two capacitors C 0 and C 1 , where capacitors C 0 and C 1 can be seen as the coupling capacitors C FC 1 and C FC 2 , and MOSFET M 0 is equivalent to the combination of the floating gate, the source, the drain, and the p-bulk. Inputs IN 1 and IN 2 are equivalent to the control gates CG 1 and CG 2 . Two resistors R 1 and R 2 were used to provide the bias potential for the gate. The device was operated in the source follower mode under the saturation state. The values of two capacitors C 0 and C 1 were set to 24 fF according to the parameters of CG 1 and CG 2 , as shown in Table 1, calculated as Equation (9). The saturation current based on the standard MOSFET M 0 was calculated as Equation (10), where V GS is the potential difference between the gate and the source, and V T is the threshold for the MOSFET device. Signals IN 1 and IN 2 are two sinusoidal wave signals with inverse phase and the same frequency and amplitude. The voltages of nodes G, D, and S were measured and the results are shown in Figure 6. From 0 to 3.5 ms, signal IN 2 was a DC signal, only signal IN 1 modulated the gate voltage with a certain attenuation, and the source voltage followed the gate voltage. After 3.5 ms, signals IN 1 and IN 2 both modulated the gate voltage. When the primary interference was detected by input end IN 1 , the source follower structure output the similar primary interference, and subsequent circuits actively generated an inverse secondary interference for input end IN 2 , which led to an effective signal without the primary interference at the source output by the superposition of two input signals. As a result, the source voltage was a DC voltage without the input sinusoidal signal, which showed the good performance of active noise control.
C = W L C o x = W L ε r ( ox ) ε 0 t o x = 1.35 × 10 4 c m × 2 × 10 4 c m × 3.9 × ( 8.85 × 10 14 F / c m ) 4 × 10 7 c m = 23.3 f F
I D = W μ C o x 2 L ( V G S V T ) 2 = 2 × 10 4 c m × 500 cm 2 / V s 2 × 0.67 × 10 4 c m × 3.9 × ( 8.85 × 10 14 F / c m ) 4 × 10 7 c m × ( 1.8 V 0.5 V 0.7 V ) 2 = 232 μ A

4. Experimental Results

4.1. I–V Characteristics

The proposed ANC device was fabricated in a 0.18 μm single-poly CMOS process and the performance was measured with the Keithley 4200 Semiconductor Characterization System. To test the capability of each control gate to modulate the charge carrier density of the device channel, one of the two control gates was set to zero voltage and the other was input with a scanning voltage, while the source and the bulk were grounded and the drain was set to 0.5 V. Figure 7a shows the ID–VG characteristics of the device, where the blue line is for control gate CG 1 and the red line is for control gate CG 2 , which shows that each control gate was able to modulate the device and the threshold voltages were within a reasonable range.
Figure 7b and c show the ID–VD curves for control gates CG 1 and CG 2 , respectively. When the control gate voltage was not large enough, a high drain voltage caused a secondary increase of the drain current. For comparison, the ID–VD curve for a standard MOSFET with the same gate size as that of the ANC device is shown in Figure 7d. It can be seen that when the gate voltage of the standard MOSFET is less than 0.2 V, the current I D increases again after saturation, which is a characteristic similar to that of the proposed device. This may be caused by reverse breakdown of the pn junction between the drain and the substrate because most of the increasing current comes from the substrate end, which can easily happen when the gate voltage is far below the threshold voltage. When the gate voltage becomes higher, a deeper depletion region is generated below the channel, which connects to the depletion region below the drain region and protects the pn junction from breakdown. Fortunately, in active noise control detection applications, the device is always turned on in the saturation state, which will not cause serious secondary increase.

4.2. Device Threshold Characteristic

The basic structure of the proposed ANC device was a 1.8 V MOSFET with a channel length of 0.67 μm and a channel width of 2.03 μm. The designed overlap area between control gate CG 1 and the floating gate was slightly bigger than that between control gate CG 2 and the floating gate. In the measurement, one of the control gates was grounded and the other was for threshold scanning. The threshold voltage for each control gate is illustrated clearly in Figure 8. The average threshold voltage for CG 1 was 0.95 V and that for CG 2 was 1.3 V.
As discussed in the section on the device model, the threshold relationships satisfy Equation (4). According to the parameters in Table 1, the estimated threshold voltages of the two control gates should almost be the same value, but the measurement result was inconsistent. However, it can be seen from the layout that the real capacitor of CG 1 was larger than that of CG 2 , which explains why the threshold voltage of control gate CG 1 was smaller than that of control gate CG 2 .

4.3. ANC Experimental Verification

The circuit with source follower mode is shown in Figure 9, where a current mirror, composed of two transistors T 1 and T 2 and a resistor R , was used to provide a constant saturation current I C , and V D was set to 2 V to ensure that the device was in the saturation state.
To characterize the background noise of the proposed ANC device in the circuit system, control gate C G 2 was grounded and control gate C G 1 was applied with a standard sinusoidal signal (with a 3.3 V DC bias), shown as the black line in Figure 10. The output signal V S was sampled and analyzed as the blue line, shown in Figure 10. The output signal curve was fitted by a sinusoidal function. The mean square of the residual expressed in Equation (11) represents the background noise of the device in the circuit system, where V bn is the background noise, N is the number of sampled points, y real is the sampled output signal, and y fit is the fitted signal as mentioned above. The absolute value of the background noise was less than 0.33 mV for N being 1000, which shows the feasibility of the device in detecting small biosignals. It should be noted that the background noise can be reduced further by integrating all circuits in the same CMOS process.
V bn = i = 1 N ( y real , i   -   y fit , i ) 2 N .
In Figure 11, the pink line is the signal on control gate C G 1 , the red line is the signal on control gate C G 2 (both corresponding to the left axis), and the blue line is the output signal V S , corresponding to the right axis. V C G 2 is an input sinusoidal wave signal, considered as the primary interference. V C G 1 is the secondary interference relevant to the primary interference from V C G 2 . The measured signal V S as function of time is shown in Figure 11, which was in good agreement with expectations. As shown in Figure 11a, the output signal V S followed the superposition of signals V C G 2 and V C G 1 , as calculated in Equation (8). When the active noise control system was turned on, the ANC signal on C G 1 was adjusted by the subsequent feedback circuits to a signal with an inverse phase from the primary interference on C G 2 . The amplitude of the ANC signal was modified by adjusting the gain of the subsequent circuits manually until the output signal V S became as small as possible. Feedback system design is a large subject area and there are many kinds of specific circuit forms for feedback system implementation. One kind of feedback circuit for an ANC system consists of a bandpass filter and an inverting amplifier. The bandpass filter extracts the interference from the output signal and the inverting amplifier generates an inverse interference for secondary input. Figure 11b shows the result of the ANC system, where the input interference amplitude was 0.255 V and the output interference amplitude after ANC was 0.009 V. Therefore, the circuits can attenuate the interference by greater than 29 dB. The device has proved to be feasible and reliable for active noise control application. Moreover, the device works at ultra-low voltages and without any external reference electrode, and it also provides the capability of large-scale integration at a low cost for fabrication in a standard single-poly CMOS process.

5. Conclusions

A smart floating gate transistor with two control gates was proposed for active noise control in bioelectrical signal measurement. A model of the device was developed and analyzed to demonstrate the working principle of the electrical behavior. Theoretical analysis and simulation results proved that the superposition of the two control gates can be reflected at the source end. To verify the feasibility of the proposed ANC device, a device with a novel structure was designed and fabricated in a standard 0.18 μm single-poly CMOS process. A series of test experiments were carried out and the results showed that the devices were in accordance with the basic electrical characteristics of floating gate transistors, including the I–V characteristics and the threshold characteristics observed on two control gates. Based on the source follower circuit, the experimental results proved that the device can reduce interference by more than 29 dB, and that is possesses the outstanding characteristic of low-cost, large-scale integration for fabrication in a standard single-poly CMOS process.
Future work will be directed toward fabricating the readout circuit of the proposed device and the subsequent circuit for secondary input in a standard single-poly CMOS process to enhance the large-scale integration ability and reduce the background noise further.

Author Contributions

All authors conceived of and designed the device and experiments; C.M. and C.Y. performed the experiments; H.M. analyzed the data; L.Z. and F.Y. contributed materials and analysis tools; C.M. wrote the paper; L.Z. revised the paper.

Funding

This research was funded by the National Key R & D Program of China, grant number 2016YFA0202100 and 2016YFA0202102, and the National Nature Science Foundation Program of China, grant number 11304152 and61571376. The APC was funded by 2016YFA0202100.

Conflicts of Interest

The authors declare no conflict of interest

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Figure 1. Working principle of a floating gate organic charge-modulated field-effect transistor (OCMFET). (a) Cross section of the device, where the floating gate is exposed to the surrounding bioelectrochemical environment as the sensing area. (b) The setting of the working point by applying the appropriate V G . (c) The charge sensing and modulation principle of the device, where the charge variations occurring in close proximity to the sensing area cause a charge separation in the floating gate, which leads to modulation of the charge carrier density inside the channel of the transistor and variation of the output current.
Figure 1. Working principle of a floating gate organic charge-modulated field-effect transistor (OCMFET). (a) Cross section of the device, where the floating gate is exposed to the surrounding bioelectrochemical environment as the sensing area. (b) The setting of the working point by applying the appropriate V G . (c) The charge sensing and modulation principle of the device, where the charge variations occurring in close proximity to the sensing area cause a charge separation in the floating gate, which leads to modulation of the charge carrier density inside the channel of the transistor and variation of the output current.
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Figure 2. Cross section of the proposed active noise control (ANC) device based on an evolution of a single-poly metal–oxide–semiconductor field-effect transistor (MOSFET), including a source region (S), a drain region (D), a bulk region (B), a floating gate (FG), and two control gates ( CG 1 and CG 2 ).
Figure 2. Cross section of the proposed active noise control (ANC) device based on an evolution of a single-poly metal–oxide–semiconductor field-effect transistor (MOSFET), including a source region (S), a drain region (D), a bulk region (B), a floating gate (FG), and two control gates ( CG 1 and CG 2 ).
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Figure 3. (a) The simple model of the equivalent schematic diagram of the proposed ANC device, where C FC 1 , C FC 2 , C S , C D ,   and   C B are the capacitors between the floating gate and the control gate CG 1 , the control gate CG 2 , the source, the drain, and the bulk region, respectively. (b) Symbols for the ANC device with five terminals.
Figure 3. (a) The simple model of the equivalent schematic diagram of the proposed ANC device, where C FC 1 , C FC 2 , C S , C D ,   and   C B are the capacitors between the floating gate and the control gate CG 1 , the control gate CG 2 , the source, the drain, and the bulk region, respectively. (b) Symbols for the ANC device with five terminals.
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Figure 4. (a) Layout of the proposed ANC device, where AA is the active area, SN is the N+ implantation for the source and drain, SP is the P+ implantation, GT is the polysilicon gate, NW is the N-type well, DNW is the deep N-type well, CT is the contact area, and M1 is the metal one. (b) Cross section of the layout, where CG 1 is a N-MOSC and CG 2 is a P-MOSFET with a common source, drain, and substrate.
Figure 4. (a) Layout of the proposed ANC device, where AA is the active area, SN is the N+ implantation for the source and drain, SP is the P+ implantation, GT is the polysilicon gate, NW is the N-type well, DNW is the deep N-type well, CT is the contact area, and M1 is the metal one. (b) Cross section of the layout, where CG 1 is a N-MOSC and CG 2 is a P-MOSFET with a common source, drain, and substrate.
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Figure 5. A simulation schematic based on the proposed ANC device with a standard MOSFET M 0 and two capacitors C 0 and C 1 , where capacitors C 0 and C 1 can be seen as the coupling capacitors C FC 1 and C FC 2 ; MOSFET M 0 represents the combination of the floating gate, the source, the drain, and the p-bulk; inputs IN 1 and IN 2 are equivalent to the control gates CG 1 and CG 2 ; and two resistors R 1 and R 2 are used to provide the bias potential for the gate.
Figure 5. A simulation schematic based on the proposed ANC device with a standard MOSFET M 0 and two capacitors C 0 and C 1 , where capacitors C 0 and C 1 can be seen as the coupling capacitors C FC 1 and C FC 2 ; MOSFET M 0 represents the combination of the floating gate, the source, the drain, and the p-bulk; inputs IN 1 and IN 2 are equivalent to the control gates CG 1 and CG 2 ; and two resistors R 1 and R 2 are used to provide the bias potential for the gate.
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Figure 6. Simulation result of the proposed ANC device, where signals IN 1 , IN 2 , G, S, and D are the measured voltages from the red node IN 1 , IN 2 , G, S, and D shown in Figure 5, and signals IN 1 and IN 2 are simulated as the primary interference and secondary interference, respectively. From 0 to 3.5 ms, only signal IN 1 modulates the gate voltage with a certain attenuation and the source voltage follows the gate voltage. After 3.5 ms, signals IN 1 and IN 2 both modulate the gate voltage and the source voltage becomes a DC voltage without noise.
Figure 6. Simulation result of the proposed ANC device, where signals IN 1 , IN 2 , G, S, and D are the measured voltages from the red node IN 1 , IN 2 , G, S, and D shown in Figure 5, and signals IN 1 and IN 2 are simulated as the primary interference and secondary interference, respectively. From 0 to 3.5 ms, only signal IN 1 modulates the gate voltage with a certain attenuation and the source voltage follows the gate voltage. After 3.5 ms, signals IN 1 and IN 2 both modulate the gate voltage and the source voltage becomes a DC voltage without noise.
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Figure 7. Current–voltage (I–V) characteristics of an ANC device and a standard MOSFET. (a) The ID–VG characteristics of an ANC device show that each control gate can modulate the device and the threshold voltages are within a reasonable range. (b) ID–VD characteristics for control gate CG 1 . (c) ID–VD characteristics for control gate CG 2 . (d) ID–VD characteristics of a standard MOSFET.
Figure 7. Current–voltage (I–V) characteristics of an ANC device and a standard MOSFET. (a) The ID–VG characteristics of an ANC device show that each control gate can modulate the device and the threshold voltages are within a reasonable range. (b) ID–VD characteristics for control gate CG 1 . (c) ID–VD characteristics for control gate CG 2 . (d) ID–VD characteristics of a standard MOSFET.
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Figure 8. The threshold voltages for two control gates of 10 devices, where the average threshold voltage for CG 1 is 0.95 V and that for CG 1 is 1.3 V.
Figure 8. The threshold voltages for two control gates of 10 devices, where the average threshold voltage for CG 1 is 0.95 V and that for CG 1 is 1.3 V.
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Figure 9. The circuit with source follower mode, where a current mirror, composed of two transistors T 1 and T 2 and a resistor R , is used to provide a constant saturation current I C , and V D is set to 2 V to ensure the device is in the saturation state.
Figure 9. The circuit with source follower mode, where a current mirror, composed of two transistors T 1 and T 2 and a resistor R , is used to provide a constant saturation current I C , and V D is set to 2 V to ensure the device is in the saturation state.
Micromachines 10 00722 g009
Figure 10. Characterization of device background noise in the circuit, where control gate C G 1 is applied with a standard sinusoidal signal (with a 3.3 V DC bias) as shown with the black line, and the output signal V S is shown with the blue line and fitted by a sinusoidal function as the red line with the fitting parameters given in the insets. The absolute value of the background noise is less than 0.33 mV.
Figure 10. Characterization of device background noise in the circuit, where control gate C G 1 is applied with a standard sinusoidal signal (with a 3.3 V DC bias) as shown with the black line, and the output signal V S is shown with the blue line and fitted by a sinusoidal function as the red line with the fitting parameters given in the insets. The absolute value of the background noise is less than 0.33 mV.
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Figure 11. The measured voltage as a function of time, where the pink line is the signal on control gate C G 1 , the red line is the signal on control gate C G 2 , the blue line is the output signal V S , and the input interference on control gate C G 2 and the output signal are fitted by a sinusoidal function respectively with the parameters given in the insets. (a) Without active noise control, the output signal V S follows the superposition of signals V C G 2 and V C G 1 as calculated. (b) With active noise control, the output signal V S is 9 mV and has a 29 dB attenuation for the input interference of 255 mV.
Figure 11. The measured voltage as a function of time, where the pink line is the signal on control gate C G 1 , the red line is the signal on control gate C G 2 , the blue line is the output signal V S , and the input interference on control gate C G 2 and the output signal are fitted by a sinusoidal function respectively with the parameters given in the insets. (a) Without active noise control, the output signal V S follows the superposition of signals V C G 2 and V C G 1 as calculated. (b) With active noise control, the output signal V S is 9 mV and has a 29 dB attenuation for the input interference of 255 mV.
Micromachines 10 00722 g011aMicromachines 10 00722 g011b
Table 1. The design parameters of the device.
Table 1. The design parameters of the device.
DeviceLength (μm)Width (μm)
CG11.3752.01
MOS0.672.03
CG21.352.00
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