Mathematical Modeling and Analysis of Capacitor Voltage Balancing for Power Converters with Fewer Switches
Abstract
:1. Introduction
2. Proposed Cascaded H-Bridge MLI
2.1. Modes of Operation
2.2. Capacitor States of Bottom H Bridge Inverter
- C1 and C3 total charging time = 4.18 milli seconds;
- C1 and C3 total discharging time = 4.18 milli seconds;
- C2 total charging time = 3.84 milli seconds;
- C2 total discharging time = 4.52 milli seconds.
3. Capacitor Voltage Balancing in the Proposed Inverter
4. Modeling of PWM Pulses for Proposed Cascaded Multilevel Inverter
- Step 1.
- Form a set:
- Step 2.
- Write the permutation P on
- Step 3.
- Eliminate the final column in the above permutation P1 and rework as
- Step 4.
- We can develop the switching signals for the secondary switches calculated from the above equation. The first and last columns of the matrix are responsible for establishing the switching patterns for the initial and final secondary switches, respectively. The equations for SS1 and SSn are also included.
5. Results and Discussion
6. Hardware Validation
7. Conclusions
Author Contributions
Funding
Institutional Review Board Statement
Informed Consent Statement
Data Availability Statement
Acknowledgments
Conflicts of Interest
References
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Switching Mode | PS5 | PS6 | PS7 | PS8 | SS1 | SS2 | Voltage Obtained | Reference |
---|---|---|---|---|---|---|---|---|
1 | ✓ | ✓ | ✖ | ✖ | ✖ | ✖ | 0 | Figure 2a |
✖ | ✖ | ✓ | ✓ | ✖ | ✖ | 0 | Figure 2b | |
2 | ✖ | ✖ | ✖ | ✓ | ✖ | ✓ | 2 Vdc0 | Figure 2c |
3 | ✖ | ✖ | ✖ | ✓ | ✓ | ✖ | 4 Vdc0 | Figure 2d |
4 | ✓ | ✖ | ✖ | ✓ | ✖ | ✖ | 6 Vdc0 | Figure 2e |
5 | ✖ | ✓ | ✖ | ✖ | ✓ | ✖ | −2 Vdc0 | Figure 2f |
6 | ✖ | ✓ | ✖ | ✖ | ✖ | ✓ | −4 Vdc0 | Figure 2g |
7 | ✖ | ✓ | ✓ | ✖ | ✖ | ✖ | −6 Vdc0 | Figure 2h |
✖—OFF|✓—ON |
Switching Mode | PS5 | PS6 | PS7 | PS8 | SS1 | SS2 | Status of Capacitors | Time Duration | ||
---|---|---|---|---|---|---|---|---|---|---|
C1 | C2 | C3 | ||||||||
1 | ✓ | ✓ | ❌ | ❌ | ❌ | ❌ | UC | UC | UC | 1.84 ms |
❌ | ❌ | ✓ | ✓ | ❌ | ❌ | UC | UC | UC | ||
2 | ❌ | ❌ | ❌ | ✓ | ❌ | ✓ | ↑ | ↑ | ↓ | 1.92 ms |
3 | ❌ | ❌ | ❌ | ✓ | ✓ | ❌ | ↑ | ↓ | ↓ | 2.26 ms |
4 | ✓ | ❌ | ❌ | ✓ | ❌ | ❌ | UC | UC | UC | 4.9 ms |
5 | ❌ | ✓ | ❌ | ❌ | ✓ | ❌ | ↓ | ↑ | ↑ | 1.92 ms |
6 | ❌ | ✓ | ❌ | ❌ | ❌ | ✓ | ↓ | ↓ | ↑ | 2.26 ms |
7 | ❌ | ✓ | ✓ | ❌ | ❌ | ❌ | UC | UC | UC | 4.9 ms |
❌—OFF|✓—ON|UC—Unchanged | 20 ms |
Top H Bridge Switches | Bottom H Bridge Switches | Mode | Output Load Voltage | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PS1 | PS2 | PS3 | PS4 | PS5 | PS6 | PS7 | PS8 | SS1 | SS2 | Vtop | Vbottom | Vtotal = Vtop + Vbottom | |
✓ | ✖ | ✖ | ✓ | ✓ | ✖ | ✖ | ✓ | ✖ | ✖ | I | 6 Vdc0 | ||
✖ | ✓ | ✓ | ✖ | ✓ | ✖ | ✖ | ✓ | ✖ | ✖ | II | 6 Vdc0 | ||
✓ | ✖ | ✖ | ✓ | ✖ | ✖ | ✖ | ✓ | ✓ | ✖ | III | |||
✖ | ✓ | ✓ | ✖ | ✖ | ✖ | ✖ | ✓ | ✓ | ✖ | IV | |||
✓ | ✖ | ✖ | ✓ | ✖ | ✖ | ✖ | ✓ | ✖ | ✓ | V | 2 Vdc0 | ||
✖ | ✓ | ✓ | ✖ | ✖ | ✖ | ✖ | ✓ | ✖ | ✓ | VI | 2 Vdc0 | ||
✓ | ✖ | ✖ | ✓ | ✓ | ✓ | ✖ | ✖ | ✖ | ✖ | VII | 0 | ||
✖ | ✓ | ✓ | ✖ | ✖ | ✖ | ✓ | ✓ | ✖ | ✖ | VIII | 0 | ||
✓ | ✖ | ✖ | ✓ | ✖ | ✓ | ✖ | ✖ | ✓ | ✖ | IX | −2 Vdc0 | ||
✖ | ✓ | ✓ | ✖ | ✖ | ✓ | ✖ | ✖ | ✓ | ✖ | X | −2 Vdc0 | ||
✓ | ✖ | ✖ | ✓ | ✖ | ✓ | ✖ | ✖ | ✖ | ✓ | XI | |||
✖ | ✓ | ✓ | ✖ | ✖ | ✓ | ✖ | ✖ | ✖ | ✓ | XII | |||
✓ | ✖ | ✖ | ✓ | ✖ | ✓ | ✓ | ✖ | ✖ | ✖ | XIII | −6 Vdc0 | ||
✖ | ✓ | ✓ | ✖ | ✖ | ✓ | ✓ | ✖ | ✖ | ✖ | XIV | −6 Vdc0 | ||
✖—OFF|✓—ON |
PARAMETERS | LEVEL 11 | LEVEL 15 |
---|---|---|
Top inverter voltage | 65 V | 47 V |
Bottom inverter voltage | 130 V | 94 V |
Load resistance = 100 Ω and load inductance = 30 mH. |
Levels | No. of Primary Switches in the Top Inverter | No. of Primary Switches in the Bottom Inverter | No. of Secondary Switches in the Bottom | Current THD in % |
---|---|---|---|---|
15 | 4 | 4 | 2 | 0.88 |
11 | 4 | 4 | 1 | 2.41 |
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Alghaythi, M.L.; Irudayaraj, G.C.R.; Ramu, S.K.; Govindaraj, P.; Vairavasundaram, I. Mathematical Modeling and Analysis of Capacitor Voltage Balancing for Power Converters with Fewer Switches. Sustainability 2023, 15, 10698. https://doi.org/10.3390/su151310698
Alghaythi ML, Irudayaraj GCR, Ramu SK, Govindaraj P, Vairavasundaram I. Mathematical Modeling and Analysis of Capacitor Voltage Balancing for Power Converters with Fewer Switches. Sustainability. 2023; 15(13):10698. https://doi.org/10.3390/su151310698
Chicago/Turabian StyleAlghaythi, Mamdouh L., Gerald Christopher Raj Irudayaraj, Senthil Kumar Ramu, Praveenraj Govindaraj, and Indragandhi Vairavasundaram. 2023. "Mathematical Modeling and Analysis of Capacitor Voltage Balancing for Power Converters with Fewer Switches" Sustainability 15, no. 13: 10698. https://doi.org/10.3390/su151310698