# Developing a Generalized Multi-Level Inverter with Reduced Number of Power Electronics Components

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## Abstract

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## 1. Introduction

- The proposed basic module has a lesser number of switches, which by generalizing the basic module, the proposed extended structure is realized.
- As the number of switches decreases, the axillary circuit number of devices, including the number of gate drivers, snubber circuits, heat sinks, etc., decreases as well, which reduces the cost and volume of the suggested inverter.
- The voltage stress of the recommended basic module switches is low.
- The maximum number of conducting switches in the current path of each voltage level is low for the proposed structure. Thus, the switches total conduction losses are reduced and the efficiency increased.

## 2. Suggested Structure

#### 2.1. The Reduced Switch Basic Module

_{1}, S

_{2}, S

_{3}, and their complementary pairs. According to Figure 1, if the switches S

_{1}, S

_{3}are turned on, the output voltage 0 is generated, and if the switch S

_{3}is turned on, the first voltage level is produced. To generate the second voltage level, the switches S

_{1}, S

_{2}, S

_{3}are turned on, and switches S

_{2}, S

_{3}are turned on to generate the third voltage level. The RSBM also generates the fourth voltage level when the switches S

_{1}, S

_{2}are turned on, and the fifth voltage level is generated when the switch S

_{2}is turned on. Table 1 demonstrates the switching pattern of the suggested basic module to produce voltage levels. In this table, 1 means on-state, and 0 means off-state for switches. Naturally, complementary switches behave inversely with the main switches.

#### 2.2. Blocking Voltage of the Proposed Reduced Switch Basic Module

#### 2.3. The Proposed Generalized Inverter Structure

_{dc}, the following relations provide the various parameters of the proposed multi-level inverter in the symmetric topology.

_{j}shows the size of the voltage sources of the jth basic module, N

_{L}shows the number of output voltage levels that can be synthesized by the topology, N

_{IGBT}, and N

_{S}show the number of IGBT and switches, respectively. Since the bidirectional switch is not utilized in the structure, the number of switches and IGBTs are equal. N

_{GD}shows the number of gate drivers, and the TBV shows the total blocking voltage by the switches of the structure.

#### 2.4. The Proposed Multi-Level Inverter Structure

_{L}) is obtained from the output voltage of the multiple basic cells:

## 3. Efficiency Calculation

#### 3.1. Conduction Losses

_{D}are the voltage drop across the switch and the anti-parallel diode in their conduction interval. The resistors R

_{S}and R

_{D}represent the equivalent resistance of the switch and its anti-parallel diode, i(t) is the current flowing through the switch and the anti-parallel diode at the conduction moments. The parameter α is a switch constant that depends on the switch specifications, which is introduced by the manufacturer in the switch datasheet. The conduction losses are calculated from the sum of the conduction losses presented in Equations (14) and (15). The amount of conduction losses of a multi-level inverter depends on the number of switches conducted at different voltage levels. Considering N

_{S}as the conducting number of switches and N

_{D}as the conducting anti-parallel diodes in a time interval, the average conduction losses of the converter in an output voltage period can be represented by (16):

#### 3.2. Switching Losses

_{ON,j}and E

_{OFF,j}are the energy dissipation of the switch j at the moments of turning on and off, ${\mathrm{t}}_{\mathrm{ON}}$ and ${\mathrm{t}}_{\mathrm{OFF}}$ are the time intervals required to turn a switch on and off, respectively. The parameters I and ${\mathrm{I}}^{\prime}$ are the current that passes through the switch before turning it off, and after turning it on. V

_{S,j}is the reverse voltage across the switch after it is turned off. The switching power losses of switches in an output voltage period can be written as follows:

_{ON,j}and N

_{OEE,j}are the number of times that switch turns on and off in a cycle, and f is the output voltage frequency. Finally, the total losses are calculated by Equation (20):

_{1}= 50 Ω, Z

_{2}= 50 + j12.56 Ω, and Z

_{3}= 50 + j25.12 Ω are simulated with output voltage steps of 50 V. Figure 4a, b show the conduction and switching power losses for all three types of the loads, respectively. Besides, the efficiency and total losses are also displayed in Figure 4c. To compare the efficiency of the proposed 11-level structure, the efficiency curve for different output power is shown in Figure 5.

## 4. Comparative Study

_{IGBT}/N

_{L}ratio is calculated and presented in Table 3 for the proposed basic module and the comparative structures. Moreover, Table 3 lists other comparative parameters, including N

_{IGBT}(number of IGBTs), N

_{GD}(number of drivers), N

_{L}(number of voltage levels synthesized by structure), N

_{DC}(number of DC voltage source), TBV (total blocking voltage), N

_{D}(number of Diodes) and N

_{IGBT, ON}(number of conducting IGBTs in each voltage level) for the proposed topology and other symmetric topologies. According to this Table, the presented basic module utilizes fewer switches for various voltage levels.

_{IGBT}/N

_{L}) is evaluated. This ratio also provides cost-effectiveness of structures. The larger this ratio, the steeper the slope of the comparison curve, and the more IGBTs are used to achieve higher output voltage levels. Furthermore, the smaller this ratio, the lower the slope of the comparison curve, and the fewer IGBTs are required.

_{GD}/N

_{L}) is presented. Figure 6 demonstrates the (N

_{IGBT}/N

_{L}) and (N

_{GD}/N

_{L}) diagrams for the proposed and other structures. As shown in Figure 6a, the proposed topology has the lowest slope for (N

_{IGBT}/N

_{L}) diagram, which means the proposed structure utilizes the lowest number of switches to generate different voltage levels. Figure 6b also shows a comparison of the number of gate drivers, in which the proposed structure does not have the lowest curve slope regarding the number of gate drivers since it has not utilized a bidirectional switch. Nevertheless, the proposed structure still has a relatively good condition regarding the number of gate drivers compared to most comparative structures.

_{L}) is used, and this graph is plotted for different topologies, as shown in Figure 7. As Figure 7 displays, the proposed structure provides a relatively good TBV compared to other structures.

## 5. Simulation and Laboratory Results of the Proposed Structure

_{0}= V

_{1}= V

_{2}= 6 V. First, the inverter results for a purely resistive load Z

_{load1}= 6.6 Ω are presented in Figure 10. The peak output voltage of the inverter with 11 levels of 6 V steps results in 66 volts. The peak load current, in this case, is 10A. The harmonic spectrum of the proposed topology is presented in Figure 10c, highlighting that the total harmonic distortion (THD) is 3.25%, with advantage in size and cost of the output filter.

_{load2}= 6.6 + j4.71 Ω. The peak load current in the case of R-L output load is 8.1 A, in which the inductance of the load filters, the current, and the load current is obtained similar to a sine wave.

_{load2}= 6.6 + j4.71 Ω to a purely resistive load Z

_{load3}= 4 Ω. The proposed structure performs well under dynamic load change conditions as well.

_{0}= V

_{1}= 2 V, V

_{2}= 12 V. The performance results of the proposed multi-level inverter with asymmetric topology for a resistive-inductive load are presented in Figure 15. The number of voltage steps increases from 11 levels in the symmetric topology to 36 levels of 2 V steps in the asymmetric topology. In this case, the peak output voltage results in 72 V. The peak load current equals 11.4 A in this condition. Figure 15b displays the zoomed staircase waveform of the output voltage. The proper performance of the proposed structure is clearly shown in this figure in the production of voltage steps. In addition, the THD value is decreased from 3.26% in the symmetric topology to 1.01% in the asymmetric topology. This THD value demonstrates that the asymmetric topology of the suggested MLI can operate properly without any output filter, which results in more reduction in overall size and cost.

## 6. Conclusions

## Author Contributions

## Funding

## Institutional Review Board Statement

## Informed Consent Statement

## Data Availability Statement

## Conflicts of Interest

## References

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**Figure 1.**(

**a**) The suggested RSBM, (

**b**) ${\mathrm{V}}_{\mathrm{out}}=0$, (

**c**) ${\mathrm{V}}_{\mathrm{out}}={\mathrm{V}}_{\mathrm{dc}}$, (

**d**) ${\mathrm{V}}_{\mathrm{out}}=2{\mathrm{V}}_{\mathrm{dc}}$, (

**e**) ${\mathrm{V}}_{\mathrm{out}}=3{\mathrm{V}}_{\mathrm{dc}}$, (

**f**) ${\mathrm{V}}_{\mathrm{out}}=4{\mathrm{V}}_{\mathrm{dc}}$, (

**g**) ${\mathrm{V}}_{\mathrm{out}}=5{\mathrm{V}}_{\mathrm{dc}}$.

**Figure 4.**(

**a**) Power losses and efficiency curves for the proposed 11-level basic cell topology at three types of loads, (

**a**) Conduction losses, (

**b**) Switching losses, (

**c**) Temperature of switches, (

**d**) Efficiency and total losses.

**Figure 5.**Efficiency comparison of the proposed 11-level basic cell with other topologies. [A] Alishah et al., 2021, [B] Jayabalan et al., 2017, [C] Ponraj et al., 2021.

**Figure 6.**Comparative diagrams including: (

**a**) N

_{IGBT}/N

_{L}, (

**b**) N

_{GD}/N

_{L}. [A] Oskuee et al., 2015, [B] Alishah et al., 2021, [C] Jayabalan et al., 2017, [D] Ponraj et al., 2021, [E] Peddapati 2020, [F] Siddique et al., 2019, [G] Samsami et al., 2017, [H] Dhanamjayulu et al., 2017, [I] Gohari et al., 2019, [J] Alishah et al., 2016, [K] Hosseinpour et al., 2020, [L] Hosseini Montazer et al., 2021, [M] Selvaraj et al., 2020, [N] Meraj et al., 2019, [O] Ponraj et al., 2021, [P] Lee et al., 2017, [Q] Siddique et al., 2019, [R] Ali 2018, [S] Seifi et al., 2020.

**Figure 7.**TBV/N

_{L}diagram for the proposed structure and other structures.* Indicates product symbol. [A] Oskuee et al., 2015, [B] Alishah et al., 2021, [C] Jayabalan et al., 2017, [D] Ponraj et al., 2021, [E] Peddapati 2020, [F] Siddique et al., 2019, [G] Samsami et al., 2017, [H] Dhanamjayulu et al., 2017, [I] Gohari et al., 2019, [J] Alishah et al., 2016, [K] Hosseinpour et al., 2020, [L] Hosseini Montazer et al., 2021, [M] Selvaraj et al., 2020, [N] Meraj et al., 2019, [O] Ponraj et al., 2021, [P] Lee et al., 2017, [Q] Siddique et al., 2019, [R] Ali 2018, [S] Seifi et al., 2020.

**Figure 8.**(

**a**) A laboratory prototype of the proposed structure, (

**b**) The power circuit of proposed structure.

**Figure 10.**The waveforms for resistive output load in symmetric topology, (

**a**) laboratory sample voltage and current, (

**b**) simulation voltage and current, (

**c**) output voltage THD.

*****Indicates product symbol.

**Figure 11.**Resistive-inductive load waveforms in symmetric topology, (

**a**) laboratory sample voltage and current, (

**b**) simulation voltage and current.

*****Indicates product symbol.

**Figure 12.**Voltage and current waveforms for changes of the modulation index: (

**a**) from 1 to 0.65 and (

**b**) from 0.65 to 0.3.

*****Indicates product symbol.

**Figure 13.**Voltage and current waveforms related to load’s dynamic change, (

**a**) laboratory result, (

**b**) simulation result.

*****Indicates product symbol.

**Figure 15.**The waveforms of Proposed MLI in asymmetric topology (

**a**) voltage and current, (

**b**) zoomed voltage, (

**c**) output voltage THD.

*****Indicates product symbol.

${\mathbf{S}}_{1}$ | $\mathbf{S}2$ | S_{3} | V_{out} |
---|---|---|---|

1 | 0 | 1 | 0 |

0 | 0 | 1 | V_{dc} |

1 | 1 | 1 | 2V_{dc} |

0 | 1 | 1 | 3V_{dc} |

1 | 1 | 0 | 4V_{dc} |

0 | 1 | 0 | 5V_{dc} |

Proposed Algorithm | Magnitude of dc Voltage Sources | N_{IGBT} | N_{L} | N_{D} |
---|---|---|---|---|

1st proposed algorithm | ${\mathrm{V}}_{0}={\mathrm{V}}_{1}=\mathrm{V},\hspace{0.17em}\hspace{0.17em}{\mathrm{V}}_{2}=\dots ={\mathrm{V}}_{\mathrm{j}}=2{\mathrm{V}}_{\mathrm{dc}}$ | $6\mathrm{j}+4$ | $20\mathrm{j}+11$ | $6\mathrm{j}+4$ |

2nd proposed algorithm | ${\mathrm{V}}_{0}={\mathrm{V}}_{1}={\mathrm{V}}_{\mathrm{dc}},\hspace{0.17em}\hspace{0.17em}{\mathrm{V}}_{2}=2{\mathrm{V}}_{\mathrm{dc}},\hspace{0.17em}\hspace{0.17em}{\mathrm{V}}_{\mathrm{j}}=2{\mathrm{V}}_{\mathrm{j}-1}$ | $6\mathrm{j}+4$ | $10{\mathrm{V}}_{\mathrm{j}}+10{\mathrm{V}}_{\mathrm{j}-1}+\dots +11{\mathrm{V}}_{1}+1$ | $6\mathrm{j}+4$ |

3rd proposed algorithm | ${\mathrm{V}}_{0}={\mathrm{V}}_{1}={\mathrm{V}}_{\mathrm{dc}},\hspace{0.17em}\hspace{0.17em}{\mathrm{V}}_{2}=3{\mathrm{V}}_{\mathrm{dc}},\hspace{0.17em}\hspace{0.17em}{\mathrm{V}}_{\mathrm{j}}=3{\mathrm{V}}_{\mathrm{j}-1}$ | $6\mathrm{j}+4$ | $10{\mathrm{V}}_{\mathrm{j}}+10{\mathrm{V}}_{\mathrm{j}-1}+\dots +11{\mathrm{V}}_{1}+1$ | $6\mathrm{j}+4$ |

4th proposed algorithm | ${\mathrm{V}}_{0}={\mathrm{V}}_{1}={\mathrm{V}}_{\mathrm{dc}},\hspace{0.17em}\hspace{0.17em}{\mathrm{V}}_{2}=6{\mathrm{V}}_{\mathrm{dc}},\hspace{0.17em}\hspace{0.17em}{\mathrm{V}}_{\mathrm{j}}=6{\mathrm{V}}_{\mathrm{j}-1}$ | $6\mathrm{j}+4$ | $10{\mathrm{V}}_{\mathrm{j}}+10{\mathrm{V}}_{\mathrm{j}-1}+\dots +11{\mathrm{V}}_{1}+1$ | $6\mathrm{j}+4$ |

N_{IGBT} | N_{GD} | N_{L} | N_{DC} | TBV(* V_{dc}) | N_{D} | N_{IGBT,ON} | N_{IGBT}/N_{L} | |
---|---|---|---|---|---|---|---|---|

[13] | 10 | 10 | 9 | 4 | 22 | 0 | 5 | 1.11 |

[14] | 12 | 10 | 9 | 4 | 24 | 0 | 7 | 1.33 |

[15] | 12 | 9 | 7 | 3 | 18 | 0 | 7 | 1.71 |

[16] | 10 | 10 | 7 | 3 | 20 | 0 | 5 | 1.42 |

[17] | 10 | 7 | 7 | 3 | 21 | 1 | 4 | 1.42 |

[18] | 8 | 7 | 7 | 3 | 14 | 0 | 4 | 1.14 |

[19] | 8 | 7 | 7 | 3 | 18 | 0 | 4 | 1.14 |

[20] | 5 | 5 | 3 | 2 | 9 | 4 | 2 | 1.66 |

[21] | 6 | 6 | 7 | 4 | 12 | 0 | 3 | 0.85 |

[22] | 12 | 10 | 9 | 4 | 24 | 0 | 7 | 1.33 |

[23] | 11 | 10 | 11 | 5 | 31 | 1 | 5 | 1 |

[24] | 11 | 10 | 11 | 5 | 31 | 2 | 4 | 1 |

[25] | 8 | 8 | 7 | 3 | 12 | 0 | 3 | 1.14 |

[26] | 10 | 8 | 9 | 4 | 20 | 0 | 4 | 1.11 |

[27] | 10 | 10 | 9 | 4 | 20 | 0 | 5 | 1.11 |

[28] | 10 | 7 | 7 | 3 | 20 | 0 | 3 | 1.42 |

[29] | 10 | 9 | 7 | 3 | 14 | 0 | 4 | 1.42 |

[30] | 10 | 9 | 9 | 4 | 18 | 0 | 4 | 1.11 |

[31] | 9 | 9 | 9 | 4 | 22 | 1 | 5 | 1 |

Proposed | 10 | 10 | 13 | 5 | 30 | 0 | 5 | 0.77 |

*****Indicates product symbol.

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## Share and Cite

**MDPI and ACS Style**

Shayeghi, H.; Seifi, A.; Hosseinpour, M.; Bizon, N.
Developing a Generalized Multi-Level Inverter with Reduced Number of Power Electronics Components. *Sustainability* **2022**, *14*, 5545.
https://doi.org/10.3390/su14095545

**AMA Style**

Shayeghi H, Seifi A, Hosseinpour M, Bizon N.
Developing a Generalized Multi-Level Inverter with Reduced Number of Power Electronics Components. *Sustainability*. 2022; 14(9):5545.
https://doi.org/10.3390/su14095545

**Chicago/Turabian Style**

Shayeghi, Hossein, Ali Seifi, Majid Hosseinpour, and Nicu Bizon.
2022. "Developing a Generalized Multi-Level Inverter with Reduced Number of Power Electronics Components" *Sustainability* 14, no. 9: 5545.
https://doi.org/10.3390/su14095545