The Choice of the Control in the Single-Phase Voltage Source Inverters for UPS Systems

Abstract

The paper presents four solutions to the voltage source inverter (VSI) control system with existing delays in the measurement channels and the middle switching frequency (25,600 Hz): Single-Input Single-Output Coefficient Diagram Method (SISO-CDM), Multi-Input Multi-Output Passivity-Based Control (MISO-PBC), Multi-Input Multi-Output One-Sample-Ahead Preview Controller (MISO-OSAP), and MISO-OSAP with Luenberger Observer (MISO-OSAP-LO). The theory, including adjustments to controller gains or to the coefficients of the characteristic equation of the closed-loop system, is presented. Simulations of the VSI operation with these control systems for the nonlinear load and the dynamic resistive load (per the requirements of the EN 62040-3 standard) are presented. The SISO-CDM and MISO-PBC are finally selected for experimental verification of the simulations. The results of the tests enable the selection of the control type for a particular VSI design based on its cost and an estimation of the advantages of the more expensive solution. The paper should help in engineering design according to the remarks in the paper.

1. Introduction

There is a variety of instantaneous control systems for the stand-alone VSI. The first difference between them is in the number of input variables of the controller. The simplest and cheapest are Single-Input Single-Output (SISO) systems, when only the output voltage is measured and controlled. In this case, the most common approach is to treat the output voltage as the independent disturbance [1,2,3,4,5,6]. For the low frequency band, below the corner frequency of the output filter, the influence of the output current on the output voltage, that is equal to the negative product of the current and the output VSI impedance for the open feedback loop, is divided by the gain of the controller, which is high in this frequency range [7]. One of the easiest to design SISO control algorithms is the Coefficient Diagram Method (CDM) [8,9,10] when the controller is designed in such a way that the coefficients of the characteristic equation of the closed loop system are equal to the coefficients of the reference characteristic equation based on the Standard Manabe Form. In the case of the VSI with a second order of the nominator and denominator of the controller, this kind of SISO controller can be treated as a PID controller with Manabe coefficients. It generally works well in accordance with the requirements of the IEC 62040-3 standard [11]. For the UPS system with the power below 3 kW, the nonlinear rectifier RC load with a Power Factor of 0.7 is basic. The dynamic load is defined as a step load change from 20% to 100% and 100% to 20% of the nominal load at the point of the maximum of the output sinusoidal voltage (Figure 1). More demanding is the step decrease because the current flowing through the filter coil is redirected to the output capacitor, causing the voltage overshoot (the feedback is always delayed at least by one switching period, T_s).

In the Multi-Input Single-Output (MISO) control systems, the VSI output voltage, current, and the inductor current are treated as the state variables, which are measured and implemented in the control law. Measuring the output current, we omit the problem with the hidden loop from the output voltage to the output current. The first considered MISO control is the Passivity-Based Control (PBC) [3,12,13,14,15,16,17,18]. The idea of PBC (similar to the Lyapunov approach [12]) is based on the statement that the energy stored in the VSI system should be lower than the energy delivered to the system. However, the system directly taking into account voltage and currents could be faster. The last, initially considered control MISO system is deadbeat control [19,20,21]. It is pure discrete, the fastest control that shifts the roots of the characteristic equation of the closed-loop system to zero in the z-plane. It is the only system where we can predict that the controlled output variable (in our case, the VSI output voltage) will reach the reference value after a countable number of switching periods. In the case of the VSI, it can be assigned to the next switching period. The One-Sample-Ahead Preview Control (OSAP) [19,20,21] is a kind of deadbeat control. A. Kawamura [19] showed that assuming v_OUT(k + 1) = v_ref(k + 1) leads to a deadbeat control law that is simply created from one of the discrete state space equations. The deadbeat control law has no assigned gains for the voltage or current. Deadbeat control is very sensitive to delays in the system. The common problem for all these controllers is a delay in the measurement channels and the PWM modulator [22]. It can be seen that one of the ways of using it in a real system with delays is by implementing the prediction of the state variables. The delay in the PWM modulator is a result of storing data in one switching period and changing pulse width according to the stored data in the next period. The modulator delay is equal to one switching period. All the measurement channels are a kind of low-pass filter. In the frequency range below the resonant frequency of the output filter, it is possible to model them as a simple delay equal to some switching periods. In our experimental VSI, we use switching frequencies f_s equal to 12,800, 25,600, or 51,200 Hz. It was shown in [22] that for the low f_s = 12,800 Hz, the delays are so serious that the necessary solution for control with a delay can be the prediction of the state variables. For f_s equal to 25,600 Hz, the delays have a small but visible influence on control, and for f_s = 51,200 Hz, they are unnoticeable. The so-called first schema of PWM was described many years ago in [23] and presented further in [24] and many others. In this scheme, the bridge transistors are switched with frequency f_s, but the magnetizing current of the filter coil has a double 2f_s frequency. So, the reasonable switching frequency, without excessive power losses in the filter coil core, was chosen as f_s = 25,600 Hz.

The goal of the paper is to show that different types of control can be useful for different requirements of the VSI designer. The CDM control is cheap (it has only one output voltage measurement channel) and quite fast. The MISO-PBC is based on energy calculation, so in the real device, it is not so good for fast load changes, but perfect for the harmonic distortions and the steady state. The MISO-OSAP is very fast, the best for fast load changes, but not so good in the steady state, and not robust to delays. After the theoretical presentations of control laws for all these controls, the simulations and the experimental verification (for the chosen controls) will be shown. We cannot forget about the other solutions—e.g., the double-loop SISO with the plug-in Repetitive Controller (RC), a kind of harmonics generator in the outer loop [24,25], perfectly dumping only harmonics distortions and steady-state error. But they implement other problems (e.g., RC remembers disturbance from the previous fundamental period even if it vanishes). The chosen four controls should clearly show differences between SISO and MISO, based on the energy calculation, and a fast pure discrete MISO control.

2. Basic Assignments and Calculations for the VSI Simulation

First, we should have the basic parameters of the simulated system. The output filter was initially calculated for the steady state. So L_FC_F was calculated to keep the output voltage maximum harmonic below 3% (1) and to keep THD below 5% (IEEE 519 [26] for low voltages) or below 8% (IEC 62040-3 [11] for UPS system). The maximum harmonic value is for the PWM duty ratio τ = 0.5.

$${{\left.{(h}_{max}\right|}_{\tau =0.5}/h_1)}_{OUT}<3\%$$

(1)

The highest harmonic is equal to or close (±50 Hz) to the double switching frequency 2f_s (2) for the first PWM scheme [24] and three-level modulation.

$$L_F{\mathrm{C}}_F={\displaystyle \frac{1}{{(2f_s)}^2}}$$

(2)

In [27], a cost function F (3) was created as the sum of the absolute values of the reactive powers in the filter inductor and capacitor, approximately only for the fundamental harmonic h₁. Having the minimum induction L_F as a function of the capacitance C_F, there is a possibility to calculate the induction value L_F for which the cost function has a minimum (4).

$$F\approx {\omega }_m(L_F{I}_{LFh1rms}^2+{\displaystyle \frac{1}{L_F{(2f_s)}^2}}{V}_{OUTh1rms}^2)$$

(3)

We assume that I_LFh1rms ≈ I_OUTh1rms and f_s >> f_m.

$${\displaystyle \frac{\partial F}{\partial L_F}}\approx {\omega }_m\left(I_{OUTh1rms}^2-{\displaystyle \frac{1}{{(L}_F{2f_s)}^2}}{V}_{OUTh1rms}^2\right)=0$$

(4)

From (2) and (4), we can obtain the particular values of L_F (5) and C_F (6).

$$L_F={\displaystyle \frac{1}{{2f}_s}}{R}_{LOAD}$$

(5)

$$C_F={\displaystyle \frac{1}{{2f}_s}}{\displaystyle \frac{1}{R_{LOAD}}}$$

(6)

For f_s = 25,600 Hz, V_OUTh1rms/I_OUTh1rms = R_LOAD = 50 Ω, L_F ≈ 1 mH, C_F ≈ 0.4 µF. However, the PWM modulator introduces a delay equal to the switching period, and the control cannot do anything during this period. We can assume that it will be a constant current forced by the filter coil during one switching period (the period T_s of bridge control, not the period T_s/2 of the filter inductor current). So, for the 5 A step load current decrease Δi_OUT = 5 A, T_s = 1/f_s = 39 µs, for assumed Δv_OUT = 5 V, C_F = T_sΔi_OUT/Δv_OUT, C_F = 39 µF. Finally, L_F = 2 mH and C_F = 51 µF were used in the simulation and the experimental model (C_F—Metallized Polypropylene capacitor WIMA MKP 4). The other parameter is the serial equivalent resistance R_L, the sum of all the serial resistances, the coil winding resistance, the equivalent resistance of the coil caused by the power losses in its core, and the serial resistance of two serially connected switched-on bridge transistors and all other VSI’s PCB and connectors’ resistances. This resistance is variable, depending on the load, but assuming R_L = 1 Ω was reasonable for the coil core made of the alloy-powder high-quality material MS-Sendust [28] and the used bridge transistors Vishay Siliconix (2201 Laurelwood Road, Santa Clara, CA 95054, USA) MOSFET IRFP360LC. The L_F and C_F values were assumed constant, and the serial parasitic resistance of the MKP capacitor was neglected. For the nonlinear rectifier RC load, when the rectifier begins conducting current to the load capacitor in t_RON time (it was simplified as ω_mt_RON = π/4, M is a modulation index, M ≤ 1), the maximum possible step voltage on the filter input is ∆v_FIN = V_DC(1 − Msin(ω_mt_RON)). So, we have to limit the maximum value L_Fmax of the filter inductor to the value that enables the rise in the inductor current controlled by feedback to follow the reference sinusoidal voltage in the inverter output in t_RON time. The approximated value L_Fmax was calculated in [24] (7), where for the serial resistance of the rectifier R_s = 1, the worst-case M = 1, the L_Fmax < 2.6 mH. So, our chosen L_F = 2 mH value is acceptable. The real value of M should be low enough (e.g., equal to 0.7, used further) to ensure the possibility of a rapid answer for the step load change in the maximum of the sinusoidal output waveform.

$$L_{Fmax}<{\displaystyle \frac{(R_L+R_s)\left(\frac{\sqrt{2}}{M}-1\right)}{{\omega }_m}}$$

(7)

Figure 1 presents the block diagram of the simulated and tested VSI, the single-phase inverter with the three-level, double-edge PWM scheme, where the switching on periods of the modulating signals (PWM envelope) for each transistor from Figure 1 are described by (8)–(11) [23,24]. For k = 1 … (f_s/f_m):

$$S_1:T_{ON}\left(k\right)/T_s=0.5M\mathit{sin}(2\pi k{f}_m/f_s)+0.5$$

(8)

$$S_2:NOT\left(S_1\right)$$

(9)

$$S_3:T_{ON}\left(k\right)/T_s=0.5M\mathit{sin}((2\pi k{f}_m/f_s)+\pi )+0.5$$

(10)

$$S_4:NOT\left(S_3\right)$$

(11)

The way of measuring the Bode plots of the inverter and its measuring channels was previously widely described in [29]. The measurement of Bode plots of the output voltage channel is based on measuring the ratios of the test signal V_ChOUT(nf_m) (summed with the fundamental signal) to the fundamental signal V_ChOUT(f_m) at the output of the channel and V_ChIN(nf_m) to V_ChIN(f_m) at the input of the channel (12). The idea of creating test signals is based on creating harmonics nf_m of the fundamental signal. The similar design (except for the channels input, where a differential amplifier is used in the voltage channel and transducers LA25-NP in the current channels) of all the measuring channels justifies the approximation (<1 kHz) that all channels have the same Bode plots in the low-pass frequency band.

$$K_{ChCTRL}(\mathrm{j}2\mathsf{\pi }{\mathrm{n}\mathrm{f}}_m)={\displaystyle \frac{\left|V_{ChOUT}\left(n{f}_m\right)\right|/\left|V_{ChOUT}\left(f_m\right)\right|}{\left|V_{ChIN}\left(n{f}_m\right)\right|/\left|V_{ChIN}\left(f_m\right)\right|}}\mathrm{e}\mathrm{x}\mathrm{p}(j\mathrm{a}\mathrm{r}\mathrm{g}(n{f}_m))$$

(12)

Figure 2 presents the Bode plots of the five tested experimental VSIs (Figure 3). They are compared with the simple exponential function exp(−j2πfnT_s). It can be seen that for the frequency range below the resonant frequency of the VSI output filter, f < 1 kHz, the simple delay can model the frequency-dependent characteristics of the channel quite accurately. The delay is nT_s, where n is equal to two in the particular tested VSI at f_s = 25,600 Hz. In the simulation, a Zero-Order Hold Unit simulates the analog-to-digital converter, and an additional delay of 2T_s simulates the delay of the measurement channel. But in a more developed measurement channel, there can be a higher delay [22].

The linearised discrete state-space equations are (13) and (14), where v_CTRL is the input signal to the PWM modulator (Figure 1), and x(k) = [v_OUT(k) i_LF(k) i_OUT(k)]^T. They are based on the idea of solving the continuous state space equations in one switching period and the linear approximation of the exponential function exp(AT_ONk/2), where A is a state space matrix [19,24,30]. It should be noticed that the control system has f_s switching frequency. However, the output filter input voltage at frequency 2f_s, which is a result of the coincidence of the two shifted pulses generated with the f_s switching frequency, does not influence control. The presented discrete model (13)–(26) of the VSI plant enables the creation of the control law of VSI.

$$\mathbf{x}(k+1)={\mathbf{A}}_D\mathbf{x}(k)+{\mathbf{G}}_D{T}_{ON}(k)={\mathbf{A}}_D\mathit{x}(k)+{\mathbf{G}}_D{\displaystyle \frac{T_s}{V_{DC}}}{v}_{CTRL}(k)$$

(13)

$$\mathbf{y}(k+1)={\mathbf{C}}_D\mathbf{x}\left(k\right)$$

(14)

The state, input, and output matrices are (15).

$${\mathbf{A}}_D=\mathbf{\Phi }\left(T_s\right)=\left[\begin{array}{ccc}{\varphi }_{11}& {\varphi }_{12}& {\varphi }_{13}\\ {\varphi }_{21}& {\varphi }_{22}& {\varphi }_{23}\\ {\varphi }_{31}& {\varphi }_{32}& {\varphi }_{33}\end{array}\right], {\mathbf{G}}_D=\left[\begin{array}{c}{g}_{11}\\ g_{21}\\ g_{31}\end{array}\right], {\mathbf{C}}_D=\mathbf{C}=[\begin{array}{ccc}1& 0& 0\end{array}]$$

(15)

For the three-level double-edge modulation, coefficients of the state matrix are (16)–(23):

$${\xi }_F={\displaystyle \frac{1}{2}}{R}_L\sqrt{{\displaystyle \frac{C_F}{L_F}}}, {\omega }_{F0}={\displaystyle \frac{1}{\sqrt{C_F{L}_F}}}, E_A=\mathit{exp}(-{\xi }_F{\omega }_{F0}{T}_s),{ E}_G=sqrt(-{\xi }_F{\omega }_{F0}{T}_s/2)$$

(16)

$${\phi }_{11}=[\mathit{cos}\left({\omega }_{F0}{T}_s\right)+{\xi }_F\mathit{sin}\left({\omega }_{F0}{T}_s\right)]E_A,$$

(17)

$${\phi }_{12}={\displaystyle \frac{1}{{\omega }_{F0}{C}_F}}\mathit{sin}({\omega }_{F0}{T}_s)E_A,$$

(18)

$${\phi }_{13}=-{\displaystyle \frac{1}{{\omega }_{F0}{C}_F}}\mathit{sin}({\omega }_{F0}{T}_s)E_A+R_L({\phi }_{11}-1),$$

(19)

$${\phi }_{21}=-{\displaystyle \frac{1}{{\omega }_{F0}{L}_F}}\mathit{sin}({\omega }_{F0}{T}_s)E_A,$$

(20)

$${\phi }_{22}=[\mathit{cos}({\omega }_{F0}{T}_s)-{\xi }_F\mathit{sin}({\omega }_{F0}{T}_s)]E_A,$$

(21)

$${\phi }_{23}=1-[\mathit{cos}\left({\omega }_{F0}{T}_s\right)+{\xi }_F\mathit{sin}\left({\omega }_{F0}{T}_s\right)]E_A,$$

(22)

$${\phi }_{31}=0, {\varphi }_{32}=0, {\phi }_{33}=1$$

(23)

Coefficients of the input matrix are (24)–(26):

$$g_{11}=V_{DC}{\omega }_{F0}\mathit{sin}({\omega }_{F0}{T}_s/2)E_G,$$

(24)

$$g_{21}={\displaystyle \frac{V_{DC}}{L_F}}[\mathit{cos}({\omega }_{F0}{T}_s/2)-{\xi }_F\mathit{sin}({\omega }_{F0}{T}_s/2)]E_G,$$

(25)

$$g_{31}=0$$

(26)

The control of the VSI’s output voltage for the open loop and three-level, double-edge modulation is (27). It was shown in [24] that double-edge modulation introduces additional delay because the interval between two consecutive pulses (k) and (k − 1) depends on the previous (k − 1) pulse width. The PWM modulator introduces an additional delay. G_inv in (27) is the inverter transfer function of the T_ON to V_OUT.

$$V_{OUT}\left(z\right)=z^{-1}{\displaystyle \frac{T_s}{V_{DC}}}{G}_{inv}{V}_{CTRL}\left(z\right)-Z_{OUI}\left(z\right)I_{OUT}\left(z\right)$$

(27)

The inverter transfer function of V_CTRL to V_OUT, including the delay of the PWM modulator and the delay of the double-edge algorithm, is (28), presented further as (29) with coefficients (30). What is important for further calculations, the V_DC value in Equations (28) and (29) simplifies with the V_DC value in g_i coefficients (24)–(26). So, (28) and (29) are not finally dependent on V_DC.

$$K_{VSI}={\displaystyle \frac{V_{OUT}\left(z\right)}{V_{CTRL}\left(z\right)}}=z^{-1}{\displaystyle \frac{T_s}{V_{DC}}}{G}_{inv}={\displaystyle \frac{N(z^{-1})}{D(z^{-1})}}={\displaystyle \frac{\frac{T_s}{V_{DC}}{g}_{11}{z}^{-2}+\frac{T_s}{V_{DC}}({\phi }_{12}{g}_{21}-{\phi }_{22}{g}_{11})z^{-3}}{1-({\phi }_{11}+{\phi }_{22})z^{-1}+({\phi }_{11}{\phi }_{22}-{\phi }_{12}{\phi }_{21})z^{-2}}}$$

(28)

$$K_{VSI}={\displaystyle \frac{N(z^{-1})}{D(z^{-1})}}={\displaystyle \frac{a_2{z}^{-2}+a_3{z}^{-3}}{1+b_1{z}^{-1}+b_2{z}^{-2}}}$$

(29)

where

$$a_2={\displaystyle \frac{T_s}{V_{DC}}}{g}_{11}{z}^{-2}, a_3={\displaystyle \frac{T_s}{V_{DC}}}({\phi }_{12}{g}_{21}-{\phi }_{22}{g}_{11})z^{-3}, b_1=-({\phi }_{11}+{\phi }_{22}), b_2=({\phi }_{11}{\phi }_{22}-{\phi }_{12}{\phi }_{21})$$

(30)

3. SISO CDM Control

The diagram of the SISO control is presented in Figure 4. The voltage conditioning scales the output voltage amplitude value to the scale of the amplitude of the reference voltage. It sets the output voltage amplitude for the modulation index M = 1 of the reference voltage V_REF. In the simulations with the V_DC voltage of the VSI, the voltage conditioning coefficient was V_REFamp/V_DC. However, the modulation index M should be set below unity because it would cause the saturation of the PWM modulator. In our further simulations, when the amplitude V_REFamp is equal to unity, we set M = 0.7 and check if the control signal in the PWM modulator input is inside ±1 range, and there is no modulator saturation. M = 0.7 was the highest possible modulation index without saturation in our simulation (it will be shown further).

The inverter output voltage is (31). N and D are from (29) and (30).

$$v_{OUT}(z^{-1})={\displaystyle \frac{TN}{RD+SN}}{v}_{REF}(z^{-1})-{\displaystyle \frac{Z_{OUT}RD}{RD+SN}}{I}_{OUT}(z^{-1})$$

(31)

The characteristic equation of a closed-loop system is Equation (32).

$$P(z^{-1})=R(z^{-1})D(z^{-1})+S(z^{-1})N(z^{-1})={\sum }_{i=0}^n{p}_{zi}{z}^{-i}$$

(32)

For CDM [8,9,10], a system with a disturbance (Figure 4: I_OUT), the degrees of R and S should be equal to or higher than n − 1, where n is the degree of D. For VSI with a plant described by (28), the second order of R and S was assumed (33):

$$S(z^{-1})={\sum }_{i=0}^2{s}_i{z}^{-i} , R(z^{-1})={\sum }_{i=0}^2{r}_i{z}^{-i}, r_0=1$$

(33)

We should solve the Diophantine Equation (34) for r₀ = p₀ = 1. To find the r_i and s_i coefficients, a matrix Equation (35) should be solved, where p_zi are coefficients of the Standard Manabe Form [8,9] in the discrete version. The fifth degree of the Manabe Standard Form is suitable for calculating the coefficients of second-order CDM control for the VSI (35).

$$(1+r_1{z}^{-1}+r_2{z}^{-2})(1+b_1{z}^{-1}+b_2{z}^{-2})+(s_0+s_1{z}^{-1}+s_2{z}^{-2})(a_2{z}^{-2}+a_3{z}^{-3})={\sum }_{i=0}^5{p}_{zi}{z}^{-1}$$

(34)

$$\left[\begin{array}{ccccc}1& 0& 0& 0& 0\\ b_1& 1& a_2& 0& 0\\ b_2& b_1& a_3& a_2& 0\\ 0& b_2& 0& a_3& a_2\\ 0& 0& 0& 0& a_3\end{array}\right]\left[\begin{array}{c}{r}_1\\ r_2\\ s_0\\ s_1\\ s_2\end{array}\right]=\left[\begin{array}{c}{p}_{z1}-b_1\\ p_{z2}-b_2\\ p_{z3}\\ p_{z4}\\ p_{z5}\end{array}\right]$$

(35)

The coefficients p_i of the Standard Manabe Form in a continuous system for the fifth degree of P(s) are the following:

p₀(s₀) = 1, p₁(s₁) = p₀τ, p₂(s₂) = 0.4p₀τ², p₃(s₃) = 0.08p₀τ³, p₄(s₄) = 0.008p₀τ⁴, p₅(s₅) = 0.0004p₀τ⁵

The time constant of a closed-loop system is τ. The experimentally satisfactory results of the CDM control were achieved for τ = 4T_s or τ = 5T_s (5T_s in simulations, 4T_s in the experimental model). Shorter or longer time constants caused some oscillations for the standard loads.

To find the coefficients of the Standard Manabe Form in the discrete version, the transfer function was discretized using the c2d MATLAB R2021b function with the discretization cycle T_s equal to the switching period (36).

$$K(z)=c2d({\displaystyle \frac{1}{{\sum }_{i=0}^5{p}_i(s)s^i}},T_s)={\displaystyle \frac{{\sum }_{i=0}^5{w}_i(z)z^{-i}}{{\sum }_{i=0}^5{p}_{zi}(z^{-1})z^{-i}}}$$

(36)

The result of the discretization is in

Table 1. Coefficients of the discretized Standard Manabe Form for τ = 4/25,600 s and τ = 5/25,600 s.

τ	pz0	pz1	pz2	pz3	pz4	pz5
4/fs	1	−1.327	0.6811	−0.1826	0.0381	−0.006738
5/fs	1	−1.7808	1.2885	−0.5077	0.1272	−0.0183

.

To keep v_OUT = v_REF in the steady state, the requirement (37) should be fulfilled. However, in the real VSI, the value of t₀ can require some corrections.

$$t_0={\displaystyle \frac{P(z=1)}{N(z=1)}}={\displaystyle \frac{V_{DC}}{T_s}}{\displaystyle \frac{1+p_{z1}+p_{z2}+p_{z3}+p_{z4}+p_{z5}}{{\phi }_{12}{g}_{21}+(1-{\phi }_{22})g_{11}}}$$

(37)

The results of solutions (35) and (37) are in

Table 2. Coefficients of the discretized CDM controller from Figure 4 for f_s = 25,600 Hz, τ = 4/f_s or 5/f_s.

τ	LF, CF	r0	r1	r2	s0	s1	s2	t0
4/fs	1 mH, 51 µF	1	0.5907	0.4224	30.1770	−24.7324	−0.4697	6.9871
4/fs	2 mH, 51 µF	1	0.6241	0.4464	65.6919	−53.0062	−0.9253	13.8305
5/fs	1 mH, 51 µF	1	0.1365	0.3558	16.8256	−13.2966	−1.2769	3.7438
5/fs	2 mH, 51 µF	1	0.1700	0.3737	37.9021	−29.5197	−25151	7.4106

.

The difference control law of the CDM control for the second order of controller nominator and denominator is presented in Equation (38).

$$v_{CTRL}\left(k\right)=-r_1{v}_{CTRL}(k-1)-r_2{v}_{CTRL}(k-2)+t_0{v}_{REF}-s_0{v}_{OUT}\left(k\right)-s_1{v}_{OUT}(k-1)-s_2{v}_{OUT}(k-2)$$

(38)

Figure 5 presents a simulation model diagram (MATLAB 2021b) for the CDM control for the rectifier RC load (100 Ω || 430 µF, R_s = 1 Ω, V_REFamp = 1, M = 0.7), and Figure 6 presents the dynamic step load 45/500 Ω and 500/45 Ω. Figure 7 presents the distortions of the output voltage for the open loop for (a) the rectifier RC load (100 Ω || 430 µF) and (b) the output voltage harmonics’ spectrum. Figure 8 presents the same dependences as Figure 7, but for CDM control. Figure 9 presents the distortions for the open loop for (a) the step load decrease of 45/500 Ω, and (b) for the step load increase of 500/45 Ω. Figure 10 presents the same dependences as Figure 9, but for CDM control.

The discussion of the simulation results for CDM control for the standard loads shows that for the rectifier RC load (PF ≈ 0.7), the output voltage THD is reduced from 6.78% to 1.42%. The overshoot for the step load decrease 45/500 Ω is reduced from 11.89% to 5.37%, and the settling time is reduced from 14 ms to 4 ms. The undershoot shoot for the step load increase 500/45 Ω is reduced from 10.52% to 5.48%, and the settling time is reduced from 10 ms to 3.5 ms. The output voltage follows its first harmonic in the steady state in a similar way (up to ±1.25% of error). It should be noted that the load current is forced by CDM to change its shape, thereby reducing the output voltage drop when the rectifier begins conducting. For the MISO control, the shape of the current will be more complex. The highest modulation index for which there is no modulator saturation is M = 0.7 (Figure 11). A lower modulation index than 0.7 would be advantageous in control, but unreal.

4. MISO Passivity-Based Control

The energy in the inverter system is stored in the filter inductor and capacitor. The Hamiltonian function (39) describes this energy stored in the system. The idea of the Passivity Based Control (PBC) [3,7,12,13,14,15,16,17,18] is based on the fact that the energy stored in the VSI system should be lower than the energy delivered to the inverter system. The idea of PBC is similar to the Lyapunov approach [12]. The control is realized by “injecting” virtual resistance R_i, which is a substitute for the current gain. In [3,12], the additional gain Kv for the output-voltage error was used in the control law of the improved PBC [7]. Output current is treated as the independent variable.

$$\mathbf{x}=[{\mathrm{v}}_{OUT}{\mathrm{C}}_F i_{LF}{L}_F], \mathrm{H}(\mathbf{x})={\displaystyle \frac{1}{2}}(L_F{i_{LF}}^2+C_F{v_{OUT}}^2)$$

(39)

The equilibrium of a closed-loop system is asymptotically stable [22] if the Hamiltonian function H(e) has a minimum in x = x_ref (40).

$$\mathbf{e}=\mathbf{x}-{\mathbf{x}}_{ref}, {\left.{\displaystyle \frac{\partial H(\mathit{e})}{\partial \mathit{x}}}\right|}_{\mathit{x}={\mathit{x}}_{ref}}=0, {\left.{\displaystyle \frac{{\partial }^{2}H(\mathit{e})}{\partial {\mathit{x}}^2}}\right|}_{\mathit{x}={\mathit{x}}_{ref}}>0$$

(40)

A negative value of the time derivative H(e) is a requirement of the system passivity (41).

$${\displaystyle \frac{dH\left(\mathit{e}\right)}{dt}}<0$$

(41)

The PBC law is created from Equation (42) [3] for a closed-loop system and Equation (43) for an open-loop system.

$$\dot{\mathbf{e}}=[\left[\begin{array}{cc}0& -1\\ 1& 0\end{array}\right]-(\left[\begin{array}{cc}{R}_L& 0\\ 0& 0\end{array}\right]+\left[\begin{array}{cc}{R}_i& 0\\ 0& K_v\end{array}\right])]\left[\begin{array}{cc}{\displaystyle \frac{1}{L_F}}& 0\\ 0& {\displaystyle \frac{1}{C_F}}\end{array}\right]\mathbf{e}$$

(42)

$$\dot{\mathbf{x}}=[\left[\begin{array}{cc}0& -1\\ 1& 0\end{array}\right]-\left[\begin{array}{cc}{R}_L& 0\\ 0& 0\end{array}\right]]\left[\begin{array}{cc}{\displaystyle \frac{1}{L_F}}& 0\\ 0& {\displaystyle \frac{1}{C_F}}\end{array}\right]\mathbf{x}+\left[\begin{array}{c}{V}_{DC}\\ 0\end{array}\right]m+\left[\begin{array}{c}0\\ -1\end{array}\right]i_{OUT}$$

(43)

The discretized PBC law [7,31] is (44) and (45).

$$v_{CTRL}(k)=-R_i{i}_{LF}(k)+(R_i+R_L)i_{LFref}(k)+L_F{\displaystyle \frac{i_{LFref}(k)-i_{LFref}(k-1)}{T_s}}+v_{REF}(k)$$

(44)

$$i_{LFref}(k)=K_v[v_{REF}(k)-v_{OUT}(k)]+C_F{\displaystyle \frac{v_{REF}(k)-v_{REF}(k-1)}{T_s}}+i_{OUT}(k)$$

(45)

The system with PBC is stable for R_L + R_i > 0 (R_L is always >0, and we assign that R_i > 0) and K_v > 0. In this case, the roots of the continuous characteristic equation of the closed-loop PBC system are in the left half s-plane [7]. The upper limit of the PBC gains is a result of the restriction of the output voltage control change speed. For the three-level PWM modulation used, it is V_DC/T_s (in one switching period, the output voltage cannot increase more than V_DC). This restriction follows (46) [22].

$$\left|{\displaystyle \frac{d{v}_{CTRL}\left(k{T}_s\right)}{dt}}\right|\le {\displaystyle \frac{V_{DC}}{T_s}}$$

(46)

From (44)–(46), for the worst case of control, the inverter load R_LOAD = ∞, for the system where we can neglect existing delays, the approximated restriction is (47), and the allowable areas of gains are presented in Figure 12.

$$K_v[L_F+(R_i+R_L)T_s]{\displaystyle \frac{1}{L_F{C}_F}}+{\displaystyle \frac{R_i}{L_F}}<f_s$$

(47)

The allowable areas of gains from (47) are below the red curve for L_F = 2 mH or below the black curve for L_F = 1 mH. The higher gains result in the lower output voltage error and faster convergence. The presented restriction (47) gives approximate results useful for initially setting up the PBC controller. R_L = 1 Ω has no serious influence on the allowable area because we set much higher R_i. The crosses in Figure 12 point to the values of R_i and K_v: one and 0.5, seven and 0.3, 15 and 0.15, and present the real borderline of the maximum gains for L_F = 2 mH in simulations. Above this line, the oscillations in the control system begin. The values of the gains tested in the experimental VSI are in the circle. They are also in the allowable area.

Figure 13 presents the PBC controller module that realizes the control law Equations (40) and (41). Figure 14 presents the simulation module diagram of VSI with the PBC controller from Figure 13 and the rectifier RC load (430 µF || 100 Ω). The gains were set R_i = 10 Ω and K_v = 0.2 S. The other set of allowable gains R_i and K_v are one and 0.5, seven and 0.3, 15 and 0.15. They are from the allowable region of gains from the diagram in Figure 12, when the PBC is slower than the PBC modulator speed. They mark the line above which oscillations occur for L_F = 2 mH. The simulated restrictions are harder than calculated from (43). Figure 15 presents the control voltage for the different sets of gains (oscillations begin for the higher gains). Figure 16 shows the distortions of the output voltage for the PBC (R_i = 10 Ω and K_v = 0.2 S) for the rectifier RC (100 Ω|| 430 µF) load and the output voltage harmonics spectrum. The values further adjusted in the experimental VSI (R_i = 4 Ω and K_v = 0.7 S) differ from those in simulations, but they are from the same allowable area. The distortions of the output voltage are lower (THD_VOUT = 0.83%) than in the case of SISO-CDM control (1.42%) for the same nonlinear load.

The discussion of the simulation results for PBC for the standard loads shows that for the rectifier RC load (PF ≈ 0.7), the output voltage THD is reduced from 6.78% to 0.83%—better than in the case of SISO-CDM (1.42%). Figure 17 presents the simulation module diagram of VSI with the PBC controller from Figure 13 for the step load. The overshoot for the step load decrease 45/500 Ω is reduced from 11.89% to 4.81%, and the settling time is reduced from 14 ms to 3 ms (Figure 18a). The undershoot shoot for the step load increase 500/45 Ω is reduced from 10.52% to 5.47%, and the settling time is reduced from 10 ms to 2.5 ms (Figure 18b). The overshoot and undershoot of the output voltage are similar to the results of CDM control (Figure 10a,b). The settling time is a bit shorter. The output voltage follows its first harmonic in the steady state (up to ±1.3% of error), in a similar way to CDM control. It should be noted that the load current is forced by MISO-PBC to change its shape more than in the case of MISO-CDM control. The highest modulation index for which there is no modulator saturation is M = 0.7, as in the case of CDM.

5. MISO Deadbeat Control

The deadbeat control [19,20,21] places all poles of the closed-loop transfer function at the origin of the z-plane. The deadbeat control is useful in linear systems. One of the advantages of the deadbeat control is reaching the steady state of the output in a countable number of time periods equal to the order of the system. A. Kawamura [19] described that for the second-order model of the inverter system, when the output voltage value can be equal to the reference value in the next k + 1 switching period. This statement is used in One-Sample-Ahead Preview Control (OSAP), also presented in the newer papers [20,21].

The deadbeat OSAP law of the inverter is based on the assumption v_OUT(k + 1) = v_ref(k + 1). Deadbeat control law has no assigned gains for the voltage or current. Its operation depends on the parameters of the control system and the switching period. Deadbeat control is very sensitive to the values of parameters and to delays in the plant’s open-loop transfer function. Version SISO of the deadbeat control is practically useless for VSI control. Only using all the state variables (output voltage, inductor current, and output current that are dependent on the parameters of the inverter) as inputs of the MISO-OSAP deadbeat control (Figure 19) can lead to acceptable control results for the standard loads in the system without noticeable delays.

If reasonable delays exist, the state variables should be predicted. The first equation of (13) is (48).

$$v_{OUT}\left(k+1\right)={\phi }_{11}{v}_{OUT}\left(k\right)+{\phi }_{12}{i}_{LF}\left(k\right)+{\phi }_{13}{i}_{OUT}\left(k\right)+g_{11}{\displaystyle \frac{T_s}{V_{DC}}}{v}_{CTRL}(k)$$

(48)

If we assume $v_{OUT}\left(k+1\right)=v_{ref}\left(k+1\right)$, we receive MISO-OSAP law (49).

$$v_{CTRL}\left(k\right)={\displaystyle \frac{1}{g_{11}}}{\displaystyle \frac{V_{DC}}{T_s}}[v_{ref}\left(k+1\right)-{\phi }_{11}{v}_{OUT}\left(k\right)-{\phi }_{12}{i}_{LF}\left(k\right)-{\phi }_{13}{i}_{OUT}\left(k\right)]$$

(49)

We should note that (49) does not depend on V_DC because its value simplifies to the same value as V_DC in Equation (24) of g₁₁. There are two problems with MISO-OSAP. The first is a very high amplification of the output voltage error. The result is the required reduction in the modulation index M. As shown in Figure 20, the value M = 0.7, previously used for PBC, leads to the saturation of the PWM modulator, which slightly increases the output voltage distortions (THD_VOUT = 0.85%) for the nonlinear rectifier RC load. The highest value of the modulation index for which there is no saturation of the modulator in the case of the nonlinear load is M = 0.4 (Figure 20). Such a low value of the modulation index is unacceptable in the real world; however, the output voltage distortions are very low for M = 0.4 (THD_VOUT = 0.284%). M = 0.7 will be further used in simulations. The second problem is the high sensitivity of MISO-OSAP to delays. The output overshoots (1.08%), undershoots (2.39%), and settling time (equal to 0.3 ms) are really very low because the MISO-OSAP is the fastest (Figure 21).

The system MISO-OSAP, with results of control in Figure 20 and Figure 21, has only modeled an analog-to-digital converter (ZOH) and a modulator with structural delay. It can be seen that MISO-OSAP “carves” the waveform of current for the rectifier RC load more than any other MISO control. Any additional delay in the measurement channels (it was 2T_s in previous examples of SISO-CDM and MISO-PBC) causes oscillations of the output voltage. The solution is to use the Luenberger Observer to predict state variables.

The full-order state Luenberger Observer [31,32,33] is a linear solution (e.g., a Kalman filter requires much more calculations) for the three input state variables prediction in the system with delays with MISO-OSAP deadbeat controller that is unstable even for an additional delay equal to the single switching period T_s, for the standard nonlinear load. The Luenberger Observer and other similar linear observers are frequently used in inverters’ control systems [34,35,36,37]. In the full-order state Luenberger Observer (46), all the state variables are measured to predict them in the next switching periods. Comparing the state Equations (13)–(15) with equations of the predicted state variables [${\widehat{v}}_{OUT}$, ${\widehat{i}}_{LF}$, ${\widehat{i}}_{OUT}$]^T (50) and (51), the output matrix C_L (51) is different from the C_D (15) because now all the state variables are in the outputs of the Luenberger Observer (not only the output voltage).

$$\widehat{\mathbf{x}}(k+1)={\mathbf{A}}_D\widehat{\mathbf{x}}\left(k\right)+{\mathbf{G}}_D{T}_{ON}\left(k\right)+\mathbf{L}\left[\mathbf{y}\right(k)-{\mathbf{C}}_L\widehat{\mathit{x}}(k\left)\right]$$

(50)

$$\mathbf{y}=\mathbf{x}, {\mathbf{C}}_{\mathit{L}}=\left[\begin{array}{ccc}1& 0& 0\\ 0& 1& 0\\ 0& 0& 1\end{array}\right]$$

(51)

The matrix of Luenberger Observer gains for three state variables [v_OUT, i_LF, i_OUT]^T is (52).

$$\mathit{L}=\left[\begin{array}{ccc}{l}_{\mathrm{v}\mathrm{O}\mathrm{U}\mathrm{T}}& 0& 0\\ 0& l_{\mathrm{i}\mathrm{L}\mathrm{F}}& 0\\ 0& 0& l_{\mathrm{i}\mathrm{O}\mathrm{U}\mathrm{T}}\end{array}\right]$$

(52)

We can estimate the values of the components of the matrix of the Luenberger Observer gains by analyzing the equation of the system error (53).

$$\mathbf{e}\left(k+1\right)=\mathbf{x}\left(k+1\right)-\widehat{\mathbf{x}}\left(k+1\right)=({\mathbf{A}}_D-\mathbf{L}{\mathit{C}}_L)\mathbf{e}\left(k\right)$$

(53)

The characteristic equation of the full-state Luenberger Observer is (56) derived from (54) and (55).

$$\mathit{det}(\mathbf{I}z-{\mathbf{A}}_D+\mathbf{L}{\mathbf{C}}_L)=0$$

(54)

$$\mathit{det}\left[\begin{array}{ccc}z-{\phi }_{11}+l_{\mathrm{v}\mathrm{O}\mathrm{U}\mathrm{T}}& -{\phi }_{12}& -{\phi }_{13}\\ -{\phi }_{21}& z-{\phi }_{22}+l_{\mathrm{i}\mathrm{L}\mathrm{F}}& -{\phi }_{23}\\ 0& 0& z-1+l_{\mathrm{i}\mathrm{O}\mathrm{U}\mathrm{T}}\end{array}\right]=0$$

(55)

$$\left(z-1+l_{\mathrm{i}\mathrm{O}\mathrm{U}\mathrm{T}}\right)\left[\left(z-{\phi }_{11}+l_{\mathrm{v}\mathrm{O}\mathrm{U}\mathrm{T}}\right)\left(z-{\phi }_{22}+l_{\mathrm{i}\mathrm{L}\mathrm{F}}\right)-{\phi }_{12}{\phi }_{21}\right]=0$$

(56)

The “separation theorem” [38] states that setting the three roots z₁, z_2, and z₃ of the characteristic equation of the Luenberger Observer (56) is independent of the closed-loop feedback control. The observer should provide a faster convergence to zero of the observation error than the transient process in a closed-loop system. For the discrete system, the roots of the Luenberger characteristic Equations (55) and (56) should be closer to zero on the z-plane than the roots of the characteristic equation of the closed feedback-loop system. This requirement cannot be met for the deadbeat control that has the poles of the closed-loop system equal to zero, and there is no simple algorithm for setting the Luenberger gains. Different algorithms for calculating the values of the linear observer characteristic equation roots compared to the closed-loop system characteristic equation roots were presented in [38,39,40]. In [38], the design of the Luenberger Observer ensured that its dynamics would be three times faster than the fastest pole of the plant. It is possible to use the poles placement acker() MATLAB function to get the pole position of the state observer [39] and further to obtain its gain matrix. Always, the eigenvalues of the continuous Luenberger Observer characteristic equation [40] should have real negative parts. In our case of deadbeat control, we can solve Equation (56) by setting the Luenberger gains such that the absolute value of the three roots z₁, z_2, and z₃ is lower than unity (the roots are inside the unit circle in the z-plane). The observer gains are initially assigned as positive values. The absolute value of the first root z₁ (57) is below unity if, according to (58), l_iOUT < 2.

$$z_1=1-l_{\mathrm{i}\mathrm{O}\mathrm{U}\mathrm{T}}$$

(57)

$$\left|1-l_{\mathrm{i}\mathrm{O}\mathrm{U}\mathrm{T}}\right|<1$$

(58)

The solution of Equation (56), finding z₂ and z₃, is graphically presented in Figure 22, where l_vOUT and l_iLF are parameters of the solution. The final approximated restriction for l_vOUT, l_iLF, l_iOUT > 0 is l_vOUT < 2, l_iLF < 2, l_iOUT < 2. However, the lowest values of |z₁|, |z₂|, and |z₃| (the fastest Luenberger Observer) are for l_vOUT ≈ 1, l_iLF ≈ 1, l_iOUT ≈ 1. Finally, the gains l_vOUT, l_iLF, l_iOUT of the Luenberger Observer (LO) should be adjusted starting from the unity value in the allowable area (Figure 22) by the trial method for the particular design case of the MISO-OSAP-LO.

Figure 23 shows a simulation module schema of VSI with the MISO-OSAP-LO controller and the rectifier RC load (430 µF || 100 Ω) with additional delays 2T_s in the measurement channels. Figure 24 presents the distortions of the output voltage for the MISO-OSAP-LO control for the rectifier RC (100 Ω || 430 µF). The THD_VOUT of the output voltage for the rectifier RC load is similar to the result for MISO-PBC, but the voltage overshoots and undershoots are unacceptably high. The settling time is slightly longer than for MISO-PBC. It can be seen that using the Luenberger Observer allows the system to operate with measurement channel delays but significantly degrades the closed-loop dynamic properties (Figure 25).

6. The Discussion of the Properties of Simulated Control Systems

The simulations were performed for f_s = 25,600 Hz, for the additional delays in the measurement channels equal to 2T_s for the rectifier RC load (430 µF || 100 Ω) and step load change 45/500/45 Ω, for modulation index M = 0.7 (even though it could, in some cases, lead to the saturation of the modulator e.g., Figure 20).

The best results are for the fastest MISO-OSAP (it is 10 times faster than MISO-PBC) but it can properly work only in the system without additional delays of the measurement channels (only the structural delay of the PWM modulator and analog-to-digital conversion delay exist in the simulation model, totaling one T_s delay; in the same switching period we measure variables and store them in modulator register). Modification of MISO-OSAP with the prediction of the state variables by means of the Luenberger Observer worsens the dynamic parameters of the MISO-OSAP-LO controller. So, both MISO-OSAP and MISO-OSAP-LO controllers can be useless in real applications. MISO-PBC has slightly better parameters of control than SISO-CDM, but it is more expensive. It requires three measurement channels (the output voltage, the inductor, and the output currents). Additionally, the adjustment of PBC requires careful adjustment of two gains, while the adjustment of CDM requires adjustment only of the time constant. So, it should be discussed if, in the particular case, using MISO-PBC is cost-effective. There is one more parameter that is not usually discussed—the distance of the output voltage from its first harmonic in the steady state. For the simulation of all the controls, it was not more than ±1.5%. However, the experimental data are a bit different. The further experimental verification concerns SISO-CDM and MISO-PBC controls.

The energy that is delivered to the load in one fundamental period (20 ms) is always the same for the open-loop and all kinds of control systems. The differences are in the shape of the current waveform and, consequently, the distortions of the sinusoidal output voltage waveforms. In the case of the rectifier RC load, the MISO type of control forces a faster increase in the load current when the rectifier begins to conduct. This increase in the inductor current (59) [41] is restricted by the maximum possible increase in the filter inductor current. In case of V_DC = 85 V, M = 0.7, R = 100 Ω, C = 430 µF, L_F = 0.002 H, C_F = 51 µF, the maximum possible inductor current increase when the rectifier begins to conduct is about 17,300 A/s, neglecting the serial resistances.

$${\displaystyle \frac{∆I_L}{∆t}}{\approx V}_{DC}\left[1-M\left(1-{\displaystyle \frac{1}{3\ast 50RC}}\right)\right]/L_F$$

(59)

For an open-loop system, the maximum increase (for the almost linear part of the current slope) of output current is 1452 A/s; for SISO-CDM control, the maximum increase in output current is 4218 A/s; for MISO-PBC: 7454 A/s; for MISO-OSAP: 14,296 A/s (MISO-OSAP in the system without additional delays), Figure 26. The fastest increase in the current in the output filter capacitor (C_F = 51 µF) is about 300 A/s. So, in the worst case, the increase in the inductor current (it is the sum of the output current and the filter capacitor current) will not reach the border value (59). The presented calculations demonstrate that the MISO control systems lead to a faster increase in the output current, thereby reducing the decrease in output voltage (the decrease under its first harmonic) after the rectifier begins to conduct. What is more, the MISO control systems decrease the output current waveform when the rectifier stops conducting, reducing the output voltage increase (over its first harmonic). At this moment, all the inductor current flows to the filter capacitor (Figure 26).

7. The Experimental Verification

It was presented in [42] that for experimental verification, we can use the Real-Time Interface (e.g., dSpace and MATLAB software with MicroLabBox RTI 1202 hardware) or create a software for the chosen microprocessor—in our case, STM32F407VG (39 Chemin du Champ-des-Filles, 1228 Plan-les-Ouates, Geneva, Switzerland). Using the microprocessor control in the experimental VSI is closer to the final device design, and it requires more sophisticated (as in the real device) scaling of the measured voltage and currents.

It is straightforward to implement the control law equations in the STM32F407VG microprocessor using the two channels, Channel 1 and Channel 2, of its TIMER1. If we have f_TIM = 84 MHz at the input of TIMER1, and we assign f_s = 25,600 Hz, the approximated maximum peak-to-peak amplitude of the control signal is f_TIM/f_s = 3281.25. Therefore, the amplitude of the sinusoidal control signal v_CTRL (calculated in the control law procedure) can be up to 1640, and the peak-to-peak amplitude can be up to 3280. Channel1Pulse register drives S1, Channel2Pulse register drives S3 from Figure 1.

The input controller signals are measured by the analog-to-digital converter in the range of −4095 to 4095. So, the measured amplitude of the nominal output voltage can be set to 3000 (by means of a potentiometer). The same adjustment should be done in the current measuring channels for the nominal load, R_nom. It should correspond to a value of 1640 in the PWM unit. The scaling factor of the measured output voltage is 1640/3000. The margin for dynamics is obtained by setting M < 1. If the nominal load was 50 Ω, the scaling factor of the output current should be (1640/3000)/R_nom. The scaling factor of the inductor current should take into account the filter capacitor current, and it should be (1640/3000)/(R_nom||1/(2π50C_F)). The used parameters are V_DC = 85 V, M = 0.7, L_F = 0.002 H, C_F = 51 µF, R = 100 Ω, C = 100 µF or 430 µF.

MISO-OSAP was very sensitive to the additional delays in the measurement channels. The prediction in MISO-OSAP-LO had advantages for harmonic disturbances but disadvantages for the dynamic load. So, the experimental VSI was tested with SISO-CDM and MISO-PBC controllers.

Figure 27 presents the output voltage and current waveforms (a) for the open-loop system, and (b) the output voltage harmonics spectrum for the rectifier R = 100 Ω, C = 100 µF load. Figure 28 presents compatible waveforms for the rectifier R = 100 Ω, C = 430 µF load. Figure 29 presents the distortions for the open-loop system, the step load decrease (45/2000 Ω), and the step load increase (2000/45 Ω) for M = 0.7. Figure 30, Figure 31 and Figure 32 present the same waveforms for the SISO-CDM control, and Figure 33, Figure 34 and Figure 35 for the MISO-PBC. Figure 36 presents a comparison of measured VSI output current waveforms for the rectifier RC load ((a) R = 100 Ω, C = 100 µF and (b) R = 100 Ω, C = 430 µF) for the open-loop, SISO-CDM control, and MISO-PBC. The output current slope is faster for MISO-PBC than for SISO-CDM, which results in lower output voltage distortions. However, the equivalent serial resistance in the experimental VSI was probably bigger than assigned in the simulation, and owing to this, the maximum values of measured currents are lower than in the simulation.

8. Discussion

The simulations and experimental verification of the control systems were performed for the harmonic disturbances (rectifier RC load resulting in PF = 0.7 for the open-loop system) and the dynamic resistive load. The final results can be compared in

Table 3. The comparison of the different simulated control results for the rectifier RC load and the dynamic load.

	No Feedback	SISO_CDM	MISO-PBC	MISO-OSAP	MISO-OSAP	MISO-OSAP-LO
Delay of the measurement channel	-------	d = 2Ts	d = 2Ts	d = 0	d = 2Ts	d = 2Ts
THDVOUT for RC load 100 Ω || 430 µF/ IOUT slope	6.78%/ 1452 A/s	1,42%/ 4218 A/s	0.83%/ 7454 A/s	0.85%/ 14,296 A/s	oscillations	1.07%/ 5464 A/s
Overshoot for 45/500 Ω	11.89%	5.37%	4.81%	1.08%	oscillations	6.94%
Undershoot for 500/45 Ω	−10.52%	−5.48%	−5.47%	−2.39%	oscillations	−25.77%
Settling time for 45/500 Ω	14 ms	4 ms	3 ms	0.3 ms	oscillations	5.7 ms
Settling time for 500/45 Ω	9 ms	3.5 ms	2.5 ms	0.3 ms	oscillations	5.7 ms

(simulations) and

Table 4. The comparison of the different control results of the experimental VSI for the rectifier RC load and the dynamic load.

	No Feedback	SISO-CDM	MISO-PBC
THDVOUT [%] for RC rectifier load 100 Ω || 100 µF /slope of the output current [A/s]	4.2%/1215 A/s	1.7%/2059 A/s	1.6%/4974 A/s
THDVOUT [%] for RC rectifier load 100 Ω || 430 µF /slope of the output current [A/s]	6.6%/1695 A/s	2.9%/2337 A/s	2.5%/4579 A/s
Overshoot for 45/2000 Ω	14%	5.13%	7.39%
Undershoot for 2000/45 Ω	−12.7%	−5.64%	−6.01%
Settling time for the load decrease of 45/2000 Ω	8 ms	1 ms	1.5 ms
Settling time for the load increase of 2000/45 Ω	5.7 ms	1.3 ms	1.5 ms

(experiments). The best simulated results were for MISO-OSAP, but it was very sensitive to the additional delay in measurement channels. The improvement of it with the prediction of the state variables by means of the Luenberger Observer worked properly for the harmonic disturbances, but was unsatisfactory for the dynamic load. So, OSAP was not experimentally tested. Among the two controls—the SISO-CDM and MISO-PBC—the MISO-PBC system resulted in lower THD of the output voltage for the nonlinear rectifier RC load, but had in experimental work slightly higher output voltage overshoots and undershoots, and slightly longer settling time for the dynamic load than the system with SISO-CDM. It can be explained that MISO-PBC calculates energy stored in the inverter, and SISO-CDM immediately responds to the output voltage change. The lower THD of the output voltage for the MISO-PBC is a result of the better shaping of the output current (both currents are at the inputs of the control system) than in the case of SISO-CDM—the output current (PBC) increases faster (Figure 36) to reduce the voltage drop after the rectifier begins to conduct. The energy delivered to the load in one fundamental period (20 ms) is the same with any feedback or without it, but feedback carves the output current shape, minimizing the distortions of the output voltage. The faster falling current in the case of the feedback reduces the distortions of the output voltage when the load rectifier stops conducting. The upper limit of the current slope increase is the restriction by the ratio of the voltage on the filter choke to its inductance value (for V_DC = 85 V, M = 0.7, L_F = 2 mH, equal to 17,300 A/s) when the rectifier begins conducting. Therefore, the lower the value of the modulation index M and the lower the value of the choke inductance L_F, the higher the possibility of feedback increasing the current slope. In the experimental measurements for rectifier RC load 100 Ω || 100 µF, the slope of current (averaging the instantaneous distortions and for the almost linear part of the slope) for open-loop was about 1215 A/s, for CDM was about 2059A/s, and for PBC about 4974 A/s. For the rectifier RC load 100 Ω|| 430 µF, the slope of current for open-loop was about 1695 A/s, for CDM was about 2337A/s, and for PBC over 4579 A/s. The faster the increase in the output current, the lower the distortions caused by the nonlinear load. The maximum values of output currents for CDM and PBC and their slope increase are lower in the experimental VSI than in simulations. It causes a higher THD of the output voltage. One of the possible reasons can be a higher real equivalent serial resistance than assigned. In simulations, one constant value of this resistance was assigned. In the real device, it changes with the filter inductor magnetizing current, resulting from variable power losses in the coil core.

9. Conclusions

The price of the main control unit—the microprocessor with embedded analog-to-digital converters—is the same for all the feedback systems. However, the MISO controller requires three measurement channels (for the state variables: output voltage, inductor current, and output current), and the SISO controller has only one output voltage measurement channel. So, the MISO controller is more expensive. The SISO-CDM controller in the basic version (using the Standard Manabe Form) has simply calculated the coefficients of the closed-loop characteristic equation, and the only adjustment concerns the time constant of the closed-loop system. The design practice shows that it should be four or five switching periods (for f_s = 25,600 Hz). We should adjust only one scaling factor of the output voltage measurement. In the case of MISO-PBC, we should adjust the two controller gains (voltage and current) within the allowable ranges. Additionally, we have to set three scaling factors in the voltage and both current measuring channels. The result of the reduction in the harmonic distortions for the nonlinear rectifier RC load (for Power Factor equal to 0.7) is better for MISO-PBC; for the more “trouble load”, the profit is higher, but the overshoots and undershoots for the dynamic load change are slightly higher for MISO-PBC than for SISO-CDM because the PBC idea is based on complex energy calculation, and SISO-CDM simply measures output voltage. Finally, it is hard to choose between the MISO-PBC and the SISO-CDM control—higher cost, lower distortions of the output voltage for the nonlinear load, versus a cheaper device and slightly better dynamics. The real improving parameters can be achieved by increasing switching frequency, e.g., up to 51,200 Hz [22], because it decreases the delays in the system and does not need any prediction of state variables, which can worsen the dynamic parameters of the control system (as in the case of the simulated MISO-OSAP-LO), but for the higher switching frequency the power losses increase. It would be possible to improve the control by further increasing the current slope (we have a margin to its highest possible value), but the problem could be with the stability of the system when the gains of the controller are higher.

The presented control systems of UPS fulfill the requirements of the best UPS classification class (“S”—sinusoidal mode) of IEC 62040-3:2021 [11] standard when THD of the output voltage should be below 8% for linear and nonlinear loads, and the limitation of the harmonics spectrum should be according to IEC 61000-2-2 standard [43].

The presented control systems of UPS fulfill the requirements of the first class of the transient performance [11] when over- and undershoot should be below 30% of the nominal voltage, and the settling time to 10% above or below the nominal output voltage should be below 100 ms for the defined step load changes.