Inverting Two-Stage Step-Up Converters

Abstract

Apart from combining two converters by connecting them in parallel at the input and the output sides, one can connect them in parallel at the inputs and in series at the outputs of the stages to increase the power rate and to modify the voltage transformation ratio. Four converter topologies with a limited duty-cycle range are studied for their application as stages for a converter combination, which operates as an inverting two-stage step-up converter. The operation of the converter combinations is studied in the steady state, and the dynamic models (for large and small signals) are derived. The start-up of the converters is analyzed. The stress across the components is calculated, and hints for dimensioning are given. The considerations are proved by LTSpice simulations. The advantages and the disadvantages of the four converters are included.

1. Introduction

To increase the output power of a converter, one can combine two converter stages. A common concept is to connect the converters in parallel, as is displayed in Figure 1a. The voltage transformation ratio of the complete converter is equal to that of one of the stages. The second concept is to connect the inputs of the stages in parallel and the outputs of the stages in series, including the input voltage; this is shown in Figure 1b. The pointed line between one input terminal and one output terminal of the converter stages shows that they are directly connected. In this second concept, the voltage transformation ratio is changed. The output voltage is now the sum of the two output voltages of the two stages and the input voltage

$$u_2=u_{21}+u_{22}+u_1.$$

(1)

This concept leads to a large output voltage. It can be used when a stable input voltage is available. A sudden change at the input leads directly to a sudden change at the output. If one uses a diode in series to the input source and a capacitor behind the diode at the input of the two-stage converter, the direct influence can be avoided. The additional diode also serves as reverse-polarity protection.

Small letters in this paper symbolize the time variables. For the steady state, capital letters are employed.

A third concept for combining two converters again is to connect the inputs in parallel and the outputs directly in series; this is depicted in Figure 2a. Now it is not possible to use the same converter type; instead, one must use an inverting and a noninverting converter stage. The output voltage is given by

$$u_2=u_{21}+u_{22}.$$

(2)

This concept can also be used by input voltages that are not stiff and can change quickly. The control of the converter stages has to correct the output voltage. In the method according to Figure 1b, a change in the input voltage directly influences the output voltage.

A fourth concept is shown in Figure 2b. The inputs of the converters are connected in parallel. The converter stages have no direct connection between the input and the output sides (which is shown by the pointed line in the other concepts); therefore, one has to combine the outputs in series. Here, converters with isolation between input and output can be used.

Using two inverting DC/DC converters leads to a high voltage transformation ratio. In this paper, inverting limited-duty-cycle step-up–down converters are used to produce a floating two-stage converter with a high voltage transformation ratio. They are taken from [1], where eight converters with reduced duty-cycle range, grounded to the positive input terminal, are presented. Two of them are step-down, two of them are step-up, and four of them are inverting step-up–down converters. These converters can be combined with stages, where the ground is connected to the negative input terminal.

The aim of this paper is to show four new floating two-stage converter topologies, according to Figure 1b, with a high voltage transformation ratio. Two different voltage transformation ratios are achieved. The new floating converters are studied in detail.

In the Chinese patent application [2], a converter according to Figure 1b consisting of two Boost converters is presented and the modes are described in detail. A more complicated converter with the same connection at the inputs and the outputs of the stages can be found in [3]. Each stage consists of n bidirectional Boost converters, which are connected in parallel; therefore, a large output power can be produced. Another Chinese patent application [4] shows a floating converter consisting of Boost converters with an additional capacitor, a diode, and a winding, which is magnetically coupled with the winding used in the Boost converter. Ref. [5] shows a modification of the Boost converter that is used for the stages of a converter according to the type displayed in Figure 1b. The advantage of this circuit is that, compared to the normal Boost converter, no inrush current occurs when connected to the input voltage. A publication concerning the concept according to Figure 2b is [6]. A complex converter is shown, where the active switches are working against ground, and the capacitors are connected in series. Instead of the coils used in a Boost converter, here they are replaced by transformers. The secondary sides of the transformers are used to make an additional step-up of the output voltage. Ref. [7] shows a two-stage converter, where the stages are constructed by tristate Boost converters. The tristate concept applied to a step-up converter makes it possible for it to become a phase-minimum system, when the converter is controlled in a special way (c.f., [8]). A converter consisting of two step-up stages, each built of one active switch, two diodes, two capacitors, and two coupled coils is treated in [9]. Ref. [10] shows several bidirectional floating and interleaved converters, which are built from bidirectional Boost converters. A quadratic Boost with two stages is treated in [11]. The circuit is very complex. The design and the analyses of a floating converter (the type displayed in Figure 1b) are performed in [12]. The stages need one active switch, four diodes, two coils, and three capacitors. The extension of a floating two-stage Boost converter by resonance circuits is explained in [13]. The main inductor of the Boost converter is here split into two magnetically coupled windings, which form a resonance circuit with an additional capacitor.

An interesting paper [14] shows similar concepts, which are called there double-dual DC-DC conversion. In this paper, 52 references are treated concerning many possible converter topologies. The converters that are treated in the next sections cannot be found in the literature. A paper that treats two-stage Buck converters based on limited-duty-cycle Buck converters can be found in [15]. To round up the introduction, a fifth concept of combining two stages shall be mentioned. The two converters are connected in cascade, as shown in Figure 2c; this topology is also used to reach large voltage transformation ratios. Both converter stages, however, must handle the complete power. Therefore, the interleaved and the floating concepts are better fitting for larger power.

Cascaded converters can be found in [14] and are also treated in [16]. Possible converters for charging batteries, summed up with 210 references, can be found in [17]. Studies treating the same topic with 180 references are given in [18] and with 95 references in [19].

2. Floating Two-Stage Converter Type I

2.1. Basics

Two converter stages are connected in parallel at the inputs and in series with the input at the output side. The circuit diagram is shown in Figure 3.

Inspecting the loop consisting of C1, L2, C2, and L1 (this is the same whether one looks at stage one or stage two), and keeping in mind that in the stationary case, the voltage across an inductor is zero in the mean, results in the fact that the voltages across the capacitors must be equal

$$U_{C1}=U_{C2}.$$

(3)

The voltage–time balance across the first inductor can be found according to

$$\left(U_1+U_{2i}\right)d=\left|-U_{C1}\right|\left(1-d\right)=\left|-U_{2i}\right|\left(1-d\right).$$

(4)

where index i stands for the number (1 or 2) of the stages of the converter leading to the output voltage of the stage, in compliance with

$$M={\displaystyle \frac{U_{2i}}{U_1}}={\displaystyle \frac{d}{1-2d}}.$$

(5)

The duty cycle must be lower than half. In practice, one will limit the duty cycle to 0.4. The output voltage of the complete converter is the sum of the output voltages of the two stages and the input voltage. For the complete converter, the output voltage results in

$${\displaystyle \frac{U_2}{U_1}}=2{\displaystyle \frac{d}{1-2d}}+1={\displaystyle \frac{1}{1-2d}} \mathrm{with} \mathrm{the} \mathrm{restriction} 0\le d<0.5.$$

(6)

Figure 4 shows the voltage transformation ratios of the complete converter, which is larger, and of one stage, which is lower.

2.2. Model with Included Losses

The mathematical model can not only be used for making a linear small signal model by linearizing it around an operating point, calculating the transfer functions, drawing the Bode plots, and helping to design the control, but it can also be used for solving the differential equations with a simulation tool, which shows the mean values of the signals. Therefore, it helps to show the dynamics. The calculation time is much faster than for the circuit-oriented simulation. This kind of simulation is only shown for type I (Figure 12 and Figure 13), type III (Figure 26), and type IV (Figure 32). It is also easy to calculate a Bode plot without calculating the transfer function. This is shown for type IV in Figure 33, and can also be used to prove a calculation of the transfer function.

The two stages are controlled by signals that are shifted by 180 degrees. For the model, we need only one stage. Here, the lower stage is used. An equivalent resistor R is used as load. Figure 5 shows the equivalent circuit of the second stage.

For the calculation, we skip the second number 2 of the index which marks the second stage. First, the current through the output capacitor is calculated with the help of KCL, according to

$${\displaystyle \frac{R_{C2}{i}_{C2}+u_{C2}}{R}}+i_{C2}=-i_{L1}, i_{C2}=-{\displaystyle \frac{R{i}_{L1}+u_{C2}}{R+R_{C2}}}.$$

(7)

Now the four state equations are given according to

$${\displaystyle \frac{d{i}_{L1}}{dt}}={\displaystyle \frac{1}{L_1}}\left\{-\left(R_{L1}+R_S+R//R_{C2}\right)i_{L1}-R_S{i}_{L2}+{\displaystyle \frac{R}{R+R_{C2}}}{u}_{C2}+u_1\right\},$$

(8)

$${\displaystyle \frac{d{i}_{L2}}{dt}}={\displaystyle \frac{1}{L_2}}\left\{u_1-R_S\left(i_{L1}+i_{L2}\right)-R_{C1}{i}_{L2}+u_{C1}-R_{L2}{i}_{L2}\right\},$$

(9)

$${\displaystyle \frac{d{u}_{C1}}{dt}}=-{\displaystyle \frac{i_{L2}}{C_1}},$$

(10)

$${\displaystyle \frac{d{u}_{C2}}{dt}}=-{\displaystyle \frac{R{i}_{L1}+u_{C2}}{C_2\left(R+R_{C2}\right)}}.$$

(11)

Combining into a matrix differential equation leads to

$${\displaystyle \frac{d}{dt}}\left(\begin{array}{c}{i}_{L1}\\ i_{L2}\\ u_{C1}\\ u_{C2}\end{array}\right)=\left[\begin{array}{cccc}-{\displaystyle \frac{+R_{L1}+R_S+R//R_{C2}}{L_1}}& -{\displaystyle \frac{R_S}{L_1}}& 0& {\displaystyle \frac{R}{L_1\left(R+R_{C2}\right)}}\\ -{\displaystyle \frac{R_S}{L_2}}& -{\displaystyle \frac{R_{C1}+R_{L2}+R_S}{L_2}}& {\displaystyle \frac{1}{L_2}}& 0\\ 0& -{\displaystyle \frac{1}{C_1}}& 0& 0\\ -{\displaystyle \frac{R}{C_2\left(R+R_{C2}\right)}}& 0& 0& -{\displaystyle \frac{1}{C_2\left(R+R_{C2}\right)}}\end{array}\right]\left(\begin{array}{c}{i}_{L1}\\ i_{L2}\\ u_{C1}\\ u_{C2}\end{array}\right)+\left[\begin{array}{c}{\displaystyle \frac{1}{L_1}}\\ {\displaystyle \frac{1}{L_2}}\\ 0\\ 0\end{array}\right]\left(u_1\right).$$

(12)

The equivalent circuit of mode M2 is depicted in Figure 6.

One gets, for the four state equations,

$${\displaystyle \frac{d{i}_{L1}}{dt}}={\displaystyle \frac{1}{L_1}}\left\{-R_{L1}{i}_{L1}-R_D\left(i_{L1}+i_{L2}\right)-V_D-u_{C1}-R_{C1}{i}_{L1}\right\},$$

(13)

$${\displaystyle \frac{d{i}_{L2}}{dt}}={\displaystyle \frac{1}{L_2}}\left\{-u_{C2}-R_{C2}\left({\displaystyle \frac{R{i}_{L2}-u_{C2}}{R+R_{C2}}}\right)-R_D\left(i_{L1}+i_{L2}\right)-V_D-R_{L2}{i}_{L2}\right\},$$

(14)

$${\displaystyle \frac{d{u}_{C1}}{dt}}={\displaystyle \frac{i_{L1}}{C_1}},$$

(15)

$${\displaystyle \frac{d{u}_{C2}}{dt}}={\displaystyle \frac{R{i}_{L2}-u_{C2}}{C_2\left(R+R_{C2}\right)}}.$$

(16)

Combining into one matrix differential equation gives

$${\displaystyle \frac{d}{dt}}\left(\begin{array}{c}{i}_{L1}\\ i_{L2}\\ u_{C1}\\ u_{C2}\end{array}\right)=\left[\begin{array}{cccc}-{\displaystyle \frac{R_{C1}+R_D+R_{L1}}{L_1}}& -{\displaystyle \frac{R_D}{L_1}}& -{\displaystyle \frac{1}{L_1}}& 0\\ -{\displaystyle \frac{R_D}{L_2}}& -{\displaystyle \frac{R_{C2}+R_{L2}+R//R_{C2}}{L_2}}& 0& -{\displaystyle \frac{R}{L_2\left(R+R_{C2}\right)}}\\ {\displaystyle \frac{1}{C_1}}& 0& 0& 0\\ 0& {\displaystyle \frac{R}{C_2\left(R+R_{C2}\right)}}& 0& -{\displaystyle \frac{1}{C_2\left(R+R_{C2}\right)}}\end{array}\right]\left(\begin{array}{c}{i}_{L1}\\ i_{L2}\\ u_{C1}\\ u_{C2}\end{array}\right)+\left(\begin{array}{c}-{\displaystyle \frac{V_D}{L_1}}\\ -{\displaystyle \frac{V_D}{L_1}}\\ 0\\ 0\end{array}\right).$$

(17)

The two systems can be combined by weighting Equation (12) for mode M1 by the duty cycle and Equation (17) by one minus the duty cycle. This results in

$${\displaystyle \frac{d}{dt}}\left(\begin{array}{c}{u}_{C1}\\ u_{C2}\\ i_{L1}\\ i_{L2}\end{array}\right)=A\left(\begin{array}{c}{u}_{C1}\\ u_{C2}\\ i_{L1}\\ i_{L2}\end{array}\right)+B\left(u_1\right)+Const,$$

(18)

with the state matrix A, the input matrix B, and the constant vector Const:

$$A=\left[\begin{array}{cccc}-{\displaystyle \frac{\left(R//R_{C2}+R_S\right)d+\left(R_{C1}+R_D\right)\left(1-d\right)+R_{L1}}{L_1}}& -{\displaystyle \frac{R_{S}d+R_D\left(1-d\right)}{L_1}}& -{\displaystyle \frac{1-d}{L_1}}& {\displaystyle \frac{Rd}{L_1\left(R+R_{C2}\right)}}\\ -{\displaystyle \frac{R_{S}d+R_D\left(1-d\right)}{L_2}}& -{\displaystyle \frac{\left(R_{C1}+R_S\right)d+\left(R//R_{C2}+R_D\right)\left(1-d\right)+R_{L2}}{L_2}}& {\displaystyle \frac{d}{L_2}}& -{\displaystyle \frac{R\left(1-d\right)}{L_2\left(R+R_{C2}\right)}}\\ {\displaystyle \frac{1-d}{C_1}}& -{\displaystyle \frac{d}{C_1}}& 0& 0\\ -{\displaystyle \frac{Rd}{C_2\left(R+R_{C2}\right)}}& {\displaystyle \frac{R\left(1-d\right)}{C_2\left(R+R_{C2}\right)}}& 0& -{\displaystyle \frac{1}{C_2\left(R+R_{C2}\right)}}\end{array}\right]$$

(19a)

$$B=\left[\begin{array}{c}{\displaystyle \frac{d}{L_1}}\\ {\displaystyle \frac{d}{L_2}}\\ 0\\ 0\end{array}\right], Const=\left(\begin{array}{c}-{\displaystyle \frac{V_D\left(1-d\right)}{L_1}}\\ -{\displaystyle \frac{V_D\left(1-d\right)}{L_2}}\\ 0\\ 0\end{array}\right).$$

(19b)

2.3. Simulation in the Steady State

Figure 7 shows the input current, the current through the second coil of the second stage, the current through the first coil of the second stage, the current through the second coil of the first stage, the current through the first coil of the first stage, the input voltage, the control signal of the second stage, the control signal of the first stage, and the output voltage. The control signals are shifted by 180 degrees. The frequency of the input current, therefore, has double the frequency of the stages.

A remark concerning the duty cycle in all circuit-oriented dynamic simulations: one can interpret the duty cycle as a percentage between 0 and 100, but also as a number between 0 and 1. The duty cycle is generated by a voltage source (lower than one volt). In the simulation, this signal is compared to a triangle signal, which has an amplitude of one. The output signal of the comparator is combined with an enable signal and amplified by a voltage-controlled voltage source, which controls the active switch. Another remark concerns the black frame in the signal graphs of the simulation: the black frame is insignificant, it shows only the last active graph.

The simulation of one stage can also be executed by an equivalent resistor for the second stage (Figure 8).

2.4. Dynamic Simulation

Figure 9 shows the simulation circuit used for the dynamic simulations. The pwm signals are produced by the comparators U1 and U2. Triangle signals are used as carrier signals, which are shifted by 180 degrees. The floating drivers of the active switches are modeled by the voltage-controlled voltage sources E1 and E2. They have a gain of ten to amplify the pwm signals.

Figure 10 shows the start-up by increasing the duty cycle starting from zero, duty-cycle steps, and input-voltage steps. One can see the current through the second coil of stage one, the current through the first coil of stage one, the duty cycle (both stages are controlled by the same duty cycle), the input voltage, and the output voltage.

The duty-cycle steps lead to a high overcurrent through the coils. Therefore, the duty cycle must be changed by a ramp; this is shown in Figure 11. It should be mentioned that the parasitic resistor of the coils is RL = 4 mΩ, and of the capacitors it is RC = 10 mΩ. Again, during start-up, the duty-cycle changes and the steps of the input voltage are shown. The signals are the current through the second coil of stage one, the current through the first coil of stage one, the duty cycle, the input voltage, and the output voltage.

2.5. Simulation by Solving the Differential Equations (18) and (19)

This simulation is much faster than the simulation by the circuit and displays only the mean value of the signals and not the ripple. Figure 12 shows the circuit used. The integration is performed by a current through a capacitor of 1 F. The parallel resistor of 10 MΩ serves only for stabilizing. The derivative is written as the current of an arbitrary current source B. With the voltage-controlled current sources L1 and L2, the voltage of the integrator is transferred into a current; therefore, currents are seen in the result.

Figure 12. Type I simulation circuit to solve the differential matrix Equation (18).

Figure 12. Type I simulation circuit to solve the differential matrix Equation (18).

Figure 13 shows the result. The signals shown are as follows: the current through second coil of the first stage, the current through first coil of the first stage, the duty cycle, the input voltage, and the output voltage. Both simulation methods lead to the same results.

Figure 13. Type I start-up, duty-cycle changes, input-voltage steps. For simulation circuit, see Figure 12. Top to bottom—current through the second coil of the first stage (violet), current through the first coil of the first stage (red); duty cycle (turquoise); input voltage (blue), output voltage (green).

Figure 13. Type I start-up, duty-cycle changes, input-voltage steps. For simulation circuit, see Figure 12. Top to bottom—current through the second coil of the first stage (violet), current through the first coil of the first stage (red); duty cycle (turquoise); input voltage (blue), output voltage (green).

2.6. Idealized Model

Setting all parasitic resistors and the forward voltage of the diode in Equation (18) to zero describes the idealized model. One obtains

$${\displaystyle \frac{d}{dt}}\left(\begin{array}{c}{i}_{L1}\\ i_{L2}\\ u_{C1}\\ u_{C2}\end{array}\right)=\left[\begin{array}{cccc}0& 0& -{\displaystyle \frac{1-d}{L_1}}& {\displaystyle \frac{d}{L_1}}\\ 0& 0& {\displaystyle \frac{d}{L_2}}& -{\displaystyle \frac{1-d}{L_2}}\\ {\displaystyle \frac{1-d}{C_1}}& -{\displaystyle \frac{d}{C_1}}& 0& 0\\ -{\displaystyle \frac{d}{C_2}}& {\displaystyle \frac{1-d}{C_2}}& 0& -{\displaystyle \frac{1}{C_{2}R}}\end{array}\right]\left(\begin{array}{c}{i}_{L1}\\ i_{L2}\\ u_{C1}\\ u_{C2}\end{array}\right)+\left[\begin{array}{c}{\displaystyle \frac{d}{L_1}}\\ {\displaystyle \frac{d}{L_2}}\\ 0\\ 0\end{array}\right]\left(u_1\right).$$

(20)

The linearized model around the operating point is given by

$${\displaystyle \frac{d}{dt}}\left(\begin{array}{c}{\stackrel{\wedge }{i}}_{L1}\\ {\stackrel{\wedge }{i}}_{L2}\\ {\stackrel{\wedge }{u}}_{C1}\\ {\stackrel{\wedge }{u}}_{C2}\end{array}\right)=\left[\begin{array}{cccc}0& 0& {\displaystyle \frac{D_0-1}{L_1}}& {\displaystyle \frac{D_0}{L_1}}\\ 0& 0& {\displaystyle \frac{D_0}{L_2}}& {\displaystyle \frac{D_0-1}{L_2}}\\ {\displaystyle \frac{1-D_0}{C_1}}& -{\displaystyle \frac{D_0}{C_1}}& 0& 0\\ -{\displaystyle \frac{D_0}{C_2}}& {\displaystyle \frac{1-D_0}{C_2}}& 0& -{\displaystyle \frac{1}{R{C}_2}}\end{array}\right]\left(\begin{array}{c}{\stackrel{\wedge }{i}}_{L1}\\ {\stackrel{\wedge }{i}}_{L2}\\ {\stackrel{\wedge }{u}}_{C1}\\ {\stackrel{\wedge }{u}}_{C2}\end{array}\right)+\left[\begin{array}{cc}{\displaystyle \frac{D_0}{L_1}}& {\displaystyle \frac{U_{C10}+U_{C20}+U_{10}}{L_1}}\\ {\displaystyle \frac{D_0}{L_2}}& {\displaystyle \frac{U_{C10}+U_{C20}+U_{10}}{L_2}}\\ 0& -{\displaystyle \frac{I_{L10}+I_{L20}}{C_1}}\\ 0& -{\displaystyle \frac{I_{L10}+I_{L20}}{C_2}}\end{array}\right]\left(\begin{array}{c}{\stackrel{\wedge }{u}}_1\\ \stackrel{\wedge }{d}\end{array}\right).$$

(21)

The connections between the operating point values are for the voltages

$$-\left(1-D_0\right)U_{C10}+D_0{U}_{C20}+D_0{U}_{10}=0,$$

(22)

$$D_0{U}_{C10}-\left(1-D_0\right)U_{C20}+D_0{U}_{10}=0.$$

(23)

This leads to

$${\displaystyle \frac{U_{C10}}{U_{10}}}={\displaystyle \frac{1-D_0}{1-2D_0}}, {\displaystyle \frac{U_{C20}}{U_{10}}}={\displaystyle \frac{D_0}{1-2D_0}}.$$

(24)

For the currents, one gets

$$\left(1-D_0\right)I_{L10}-D_0{I}_{L20}=0, -D_0{I}_{L10}+\left(1-D_0\right)I_{L20}-{\displaystyle \frac{U_{C20}}{R}}=0$$

(25)

$${\displaystyle \frac{I_{L10}}{I_{LOAD}}}={\displaystyle \frac{D_0}{1-2D_0}}, {\displaystyle \frac{I_{L20}}{I_{LOAD}}}={\displaystyle \frac{1-D_0}{1-2D_0}}.$$

(26)

Keep in mind that the results describe one stage alone.

2.7. Inrush

When the converter is connected to a stable input voltage, no inrush current occurs—an advantage compared to the other three types treated here. This is shown in Figure 14, where the input current, the input voltage, the output voltage of the two stages, and the output voltage of the complete converter are shown.

The voltage across the load is about the same as the input voltage. A steady-state current is flowing through the load. The current flows through the loop consisting of U1, L22, D2, load R, D1, and L21. A small ringing occurs, but the converter has no problem when applied to a stable input voltage.

2.8. Dimensioning Hints for Converter Type I

For the dimensioning, the voltage stress of the semiconductors is important. With KVL, one gets for the active switch when the diode is conducting

$$U_{Si}=U_1+U_{2i}+U_{C1i}=U_1+2U_{2i}.$$

(27)

The same stress occurs across the diode when the transistor is on. For the coils, one can choose a current ripple ΔI and the switching frequency f. The signal of the voltage across both coils of one stage is the same; therefore, one can dimension the coils according to

$$L_i={\displaystyle \frac{\left(U_1+U_{2i}\right)d}{\Delta I\cdot f}}={\displaystyle \frac{\left(U_1+U_{2i}\right)U_{2i}}{\Delta I\cdot f\left(U_1+2U_{2i}\right)}}.$$

(28)

The output capacitors only need to smooth the current ripple of the output coil and have the value

$$C_{2i}={\displaystyle \frac{\Delta I}{8\Delta u\cdot f}}.$$

(29)

This is the equation for the ideal capacitor. To choose the correct value, one must look at the series resistor of the capacitor. Typically, the value to achieve a desired maximum voltage ripple is about three times this value.

During the on-time of the switch, the first capacitor is discharged by the current through the second coil. The mean current through the first coil is equal to the load current. For the charge balance, through C_1i, one obtains

$$\left|-{\stackrel{\_}{I}}_{L2}\right|d=I_{LOAD}\left(1-d\right).$$

(30)

The mean value of the current through the second coil is, therefore,

$${\stackrel{\_}{I}}_{L2}=I_{LOAD}{\displaystyle \frac{1-d}{d}}=I_{LOAD}{\displaystyle \frac{U_1+U_{2i}}{U_{2i}}}.$$

(31)

For the first capacitor, one gets

$$C_{1i}={\displaystyle \frac{{\stackrel{\_}{I}}_{L2}dT}{\Delta u_{C1i}}}=I_{LOAD}{\displaystyle \frac{U_1+U_{2i}}{U_1+2U_{2i}}}{\displaystyle \frac{1}{\Delta u_{C1i}f}}.$$

(32)

2.9. Interleaved Converter Type I

A second way to combine two converters is by connecting them in parallel. The control signals are shifted by a half period. The so-realized converter again has no inrush current when connected to a stable input source. The capacitors can be slowly charged by increasing the duty cycle from zero to the desired value. The voltage transformation ratio of the complete converter is only that of one stage

$$M={\displaystyle \frac{U_2}{U_1}}={\displaystyle \frac{d}{1-2d}} \mathrm{with} d<0.5.$$

(33)

The graph is shown in the lower line of Figure 3. The converter is an inverting step-up–down converter. The output voltage is significantly lower than that of the floating converter. The reference, however, is the same for both stages. One can also use more than one stage in parallel when larger output power is desired. Figure 15 shows the dynamic behavior during start-up, changes in the duty cycle, and steps of the input voltage. The signals shown are as follows: the currents through the coils, the duty cycle, and the input and output voltages.

Figure 16a shows the converter in the steady state. Depicted are the following parameters: the input current, which has double the frequency of the stages, the current through the coils of both stages, the input voltage, the control signals of the switches, and the output voltage. Figure 16b shows the start-up, changes in the duty cycle, and steps of the input voltage. The simulation is performed by solving the differential equation. One can see that it is wise to change the duty cycle by ramps and not by steps.

3. Floating Two-Stage Converter Type II

3.1. Basics of Type II

There exists a second circuit to obtain the same voltage transformation ratio of

$$M={\displaystyle \frac{U_2}{U_1}}=2{\displaystyle \frac{d}{1-2d}}+1={\displaystyle \frac{1}{1-2d}} \mathrm{with} d<0.5.$$

(34)

The diagram of the voltage transformation ratio is, therefore, again equal to Figure 3.

The circuit diagram is shown in Figure 17.

In the steady state, the voltage across the first capacitor is equal to the sum of the input voltage and the output voltage of the stages

$$U_{C1i}=U_1+U_{2i}.$$

(35)

With the help of the charge balance at the first capacitor, one gets a connection between the currents through the coils according to

$$I_{L2i}\cdot d=I_{L1i}\cdot \left(1-d\right).$$

(36)

The charge balance of the second capacitor is given by

$$\left(I_{L1i}+I_{LOAD}\right)\cdot d=\left(I_{L2i}-I_{LOAD}\right)\cdot \left(1-d\right).$$

(37)

The mean values of the current through the coils referred to the load current can now be calculated according to

$${\displaystyle \frac{{\stackrel{\_}{I}}_{L1i}}{I_{LOAD}}}={\displaystyle \frac{d}{1-2d}}, {\displaystyle \frac{{\stackrel{\_}{I}}_{L2i}}{I_{LOAD}}}={\displaystyle \frac{1-d}{1-2d}}.$$

(38)

3.2. Model of Type II

The model can be calculated in the same way as shown in the previous section, and leads to state matrix A, the input matrix B, and the constant vector Const according to

$$A=\left[\begin{array}{cccc}-{\displaystyle \frac{\left(R_S+R//R_{C2}\right)d+\left(R_{C1}+R_D\right)\left(1-d\right)+R_{L1}}{L_1}}& -{\displaystyle \frac{\left(R_S+R//R_{C2}\right)d+R_D\left(1-d\right)}{L_1}}& -{\displaystyle \frac{1-d}{L_1}}& {\displaystyle \frac{Rd}{L_1\left(R+R_{C2}\right)}}\\ -{\displaystyle \frac{R_{S}d+R_D\left(1-d\right)}{L_2}}& -{\displaystyle \frac{\left(R_{C1}+R_S\right)d+\left(R_D+R//R_{C2}\right)\left(1-d\right)+R_{L2}}{L_2}}& {\displaystyle \frac{d}{L_2}}& -{\displaystyle \frac{R\left(1-d\right)}{L_2\left(R+R_{C2}\right)}}\\ {\displaystyle \frac{1-d}{C_1}}& -{\displaystyle \frac{d}{C_1}}& 0& 0\\ -{\displaystyle \frac{Rd}{C_2\left(R+R_{C2}\right)}}& {\displaystyle \frac{R\left(1-d\right)}{C_2\left(R+R_{C2}\right)}}& 0& -{\displaystyle \frac{1}{C_2\left(R+R_{C2}\right)}}\end{array}\right],$$

(39)

$$B=\left[\begin{array}{c}{\displaystyle \frac{1}{L_1}}\\ 0\\ 0\\ 0\end{array}\right], Const=\left(\begin{array}{c}-{\displaystyle \frac{V_D\left(1-d\right)}{L_1}}\\ -{\displaystyle \frac{V_D\left(1-d\right)}{L_2}}\\ 0\\ 0\end{array}\right).$$

(40)

3.3. Simulation in the Steady-State Type II

Figure 18 shows the currents through stages one and two, the load current, the input voltage, the control signals, and the output voltage.

3.4. Dynamic Simulation Type II

The used simulation circuit is depicted in Figure 19a. It is similar to the one used in Section 2.

The results are shown in Figure 19b. The currents through the coils of the first stage are shown, in addition to the duty cycle, the input voltage, the output voltage of stage one, and the output voltage of the complete two-stage converter. The results from stage two are not shown because they are equal.

The dynamics of the two stages are similar.

3.5. Idealized Model Type II

By setting the parasitic resistors to zero, one gets an idealized model

$${\displaystyle \frac{d}{dt}}\left(\begin{array}{c}{i}_{L1}\\ i_{L2}\\ u_{C1}\\ u_{C2}\end{array}\right)=\left[\begin{array}{cccc}0& 0& -{\displaystyle \frac{1-d}{L_1}}& {\displaystyle \frac{d}{L_1}}\\ 0& 0& {\displaystyle \frac{d}{L_2}}& -{\displaystyle \frac{1-d}{L_2}}\\ {\displaystyle \frac{1-d}{C_1}}& -{\displaystyle \frac{d}{C_1}}& 0& 0\\ -{\displaystyle \frac{d}{C_2}}& {\displaystyle \frac{1-d}{C_2}}& 0& -{\displaystyle \frac{1}{C_{2}R}}\end{array}\right]\left(\begin{array}{c}{i}_{L1}\\ i_{L2}\\ u_{C1}\\ u_{C2}\end{array}\right)+\left[\begin{array}{c}{\displaystyle \frac{1}{L_1}}\\ 0\\ 0\\ 0\end{array}\right]\left(u_1\right)\left[\begin{array}{cc}{\displaystyle \frac{1}{L_1}}& 0\\ 0& 0\\ 0& 0\\ 0& -{\displaystyle \frac{1}{C_2}}\end{array}\right]\left(\begin{array}{c}{u}_1\\ i_{LOAD}\end{array}\right).$$

(41)

Linearization around the operating point leads to the small signal model and the connections between the operating point values (for one stage)

$${\displaystyle \frac{d}{dt}}\left(\begin{array}{c}{\stackrel{\wedge }{i}}_{L1}\\ {\stackrel{\wedge }{i}}_{L2}\\ {\stackrel{\wedge }{u}}_{C1}\\ {\stackrel{\wedge }{u}}_{C2}\end{array}\right)=\left[\begin{array}{cccc}0& 0& {\displaystyle \frac{D_0-1}{L_1}}& {\displaystyle \frac{D_0}{L_1}}\\ 0& 0& {\displaystyle \frac{D_0}{L_2}}& {\displaystyle \frac{D_0-1}{L_2}}\\ {\displaystyle \frac{1-D_0}{C_1}}& -{\displaystyle \frac{D_0}{C_1}}& 0& 0\\ -{\displaystyle \frac{D_0}{C_2}}& {\displaystyle \frac{1-D_0}{C_2}}& 0& -{\displaystyle \frac{1}{C_{2}R}}\end{array}\right]\left(\begin{array}{c}{\stackrel{\wedge }{i}}_{L1}\\ {\stackrel{\wedge }{i}}_{L2}\\ {\stackrel{\wedge }{u}}_{C1}\\ {\stackrel{\wedge }{u}}_{C2}\end{array}\right)+\left[\begin{array}{cc}{\displaystyle \frac{1}{L_1}}& {\displaystyle \frac{U_{C10}+U_{C20}}{L_1}}\\ 0& {\displaystyle \frac{U_{C10}+U_{C20}}{L_1}}\\ 0& -{\displaystyle \frac{I_{L10}+I_{L20}}{C_1}}\\ 0& -{\displaystyle \frac{I_{L10}+I_{L20}}{C_1}}\end{array}\right]\left(\begin{array}{c}{\stackrel{\wedge }{u}}_1\\ \stackrel{\wedge }{d}\end{array}\right).$$

(42)

$${\displaystyle \frac{U_{C10}}{U_{10}}}={\displaystyle \frac{1-D_0}{1-2D_0}}, {\displaystyle \frac{U_{C20}}{U_{10}}}={\displaystyle \frac{D_0}{1-2D_0}}, {\displaystyle \frac{I_{L10}}{I_{LOAD}}}={\displaystyle \frac{D_0}{1-2D_0}}, {\displaystyle \frac{I_{L20}}{I_{LOAD}}}={\displaystyle \frac{1-D_0}{1-2D_0}}.$$

(43)

3.6. Inrush Type II

A disadvantage of this converter type is the inrush current. This version has a significant inrush overcurrent and ringing compared to the converter described in Section 2. Connecting the converter immediately to a strong, stable input source is shown in Figure 20a. The input current, the currents through the coils, the output voltages of the complete converter, and the stages now show a pronounced ringing and a significant overcurrent.

A way to avoid the inrush is to connect a Buck converter in front of the two-stage converter. The voltage can now be increased by a ramp; this is shown in Figure 20b. The same signals as in Figure 20a are depicted. The Buck converter only has to work during the start-up. Afterwards, the switch of the Buck converter is always conducting. In case of an error, this switch can be used as an electronic fuse. The Buck converter is simplified in the simulation by a ramp in the input voltage.

4. Floating Two-Stage Converter Type III

4.1. Basics of Type III

Combining two (2d − 1)/(1 − d) converters, as shown in Figure 21, leads to the voltage transformation ratio

$$M={\displaystyle \frac{U_2}{U_1}}=2{\displaystyle \frac{2d-1}{1-d}}+1={\displaystyle \frac{3d-1}{1-d}}, \mathrm{with} \mathrm{the} \mathrm{restriction} d\ge 0.5.$$

(44)

The restriction of the duty cycle is caused by the restriction of the stages. It cannot be seen directly in the equation.

In the steady state, the voltage across the first capacitor of a stage is the sum of the input and the output voltages

$$U_{C1i}=U_1+U_{2i}.$$

(45)

The mean value of the current through the second coil is equal to the output current. The output capacitors of the stages only need to smooth the ripple of the current through the output coil. The charge balance of the first inductor is again the same as for type I and is shown in Equation (29). Therefore, the dimensioning hints given in Section 2 also assist in designing type III.

Figure 22 shows a diagram of the voltage transformation ratio of the complete converter (the larger one) and of one stage.

4.2. Model with Equivalent Resistor Type III

Both stages are driven by the same duty cycle. The control signals of the two stages are shifted by 180 degrees. The load R is an equivalent resistor representing the load of one stage of the converter. During mode M1, when the active switch is turned on, the equivalent circuit of the second stage is given in Figure 23.

For the calculation, we skip part two of the second stage. The current through the output capacitor can be found with KCL, according to

$$i_{L2}=i_{C2}+{\displaystyle \frac{R_{C2}{i}_{C2}+u_{C2}}{R}}·i_{C2}={\displaystyle \frac{i_{L2}R-u_{C2}}{R+R_{C2}}}.$$

(46)

The state equations are

$${\displaystyle \frac{d{i}_{L1}}{dt}}={\displaystyle \frac{1}{L_1}}\left\{-R_{L1}{i}_{L1}-R_S\left(i_{L1}+i_{L2}\right)+u_1\right\},$$

(47)

$${\displaystyle \frac{d{i}_{L2}}{dt}}={\displaystyle \frac{1}{L_2}}\left\{-R_{C1}{i}_{L2}+u_{C1}-R_S\left(i_{L1}+i_{L2}\right)-u_{C2}-R_{C2}{i}_{C2}-R_{L2}{i}_{L2}\right\},$$

(48)

$${\displaystyle \frac{d{u}_{C1}}{dt}}=-{\displaystyle \frac{i_{L2}}{C_1}},$$

(49)

$${\displaystyle \frac{d{u}_{C2}}{dt}}={\displaystyle \frac{R{i}_{L2}-u_{C2}}{C_2\left(R+R_{C2}\right)}}.$$

(50)

Combination leads to the matrix differential equation

$${\displaystyle \frac{d}{dt}}\left(\begin{array}{c}{i}_{L1}\\ i_{L2}\\ u_{C1}\\ u_{C2}\end{array}\right)=\left[\begin{array}{cccc}-{\displaystyle \frac{R_{L1}+R_S}{L_1}}& -{\displaystyle \frac{R_S}{L_1}}& 0& 0\\ -{\displaystyle \frac{R_S}{L_2}}& -{\displaystyle \frac{R_{C1}+R_{L2}+R_S+R//R_{C2}}{L_2}}& {\displaystyle \frac{1}{L_2}}& -{\displaystyle \frac{R}{L_2\left(R+R_{C2}\right)}}\\ 0& -{\displaystyle \frac{1}{C_1}}& 0& 0\\ 0& {\displaystyle \frac{R}{C_2\left(R+R_{C2}\right)}}& 0& -{\displaystyle \frac{1}{C_2\left(R+R_{C2}\right)}}\end{array}\right]\left(\begin{array}{c}{i}_{L1}\\ i_{L2}\\ u_{C1}\\ u_{C2}\end{array}\right)+\left[\begin{array}{c}{\displaystyle \frac{1}{L_1}}\\ 0\\ 0\\ 0\end{array}\right]\left(u_1\right).$$

(51)

The equivalent circuit of one stage (the second stage is used for the calculation) during mode M2 (the active switch is off and the diode is conducting) can be seen in Figure 24.

The current through the output capacitor is the same as in mode M1. The state equations can be found with Kirchhoff’s laws, according to

$${\displaystyle \frac{d{i}_{L1}}{dt}}={\displaystyle \frac{1}{L_1}}\left\{-R_{L1}{i}_{L1}-u_{C1}-R_{C1}{i}_{L1}-R_D\left(i_{L1}+i_{L2}\right)-V_D\right\},$$

(52)

$${\displaystyle \frac{d{i}_{L2}}{dt}}={\displaystyle \frac{1}{L_2}}\left\{-R_D\left(i_{L1}+i_{L2}\right)-V_D-u_1-u_{C2}-R//R_{C2}{i}_{L2}+{\displaystyle \frac{R_{C2}}{R+R_{C2}}}{u}_{C2}-R_{L2}{i}_{L2}\right\},$$

(53)

$${\displaystyle \frac{d{u}_{C1}}{dt}}={\displaystyle \frac{i_{L1}}{C_1}},$$

(54)

The equation for the change in the voltage across the output capacitor is equal to the one given for mode M1 in Equation (47).

Summarization into a matrix equation gives

$${\displaystyle \frac{d}{dt}}\left(\begin{array}{c}{i}_{L1}\\ i_{L2}\\ u_{C1}\\ u_{C2}\end{array}\right)=\left[\begin{array}{cccc}-{\displaystyle \frac{R_{C1}+R_D+R_{L1}}{L_1}}& -{\displaystyle \frac{R_D}{L_1}}& -{\displaystyle \frac{1}{L_1}}& 0\\ -{\displaystyle \frac{R_D}{L_2}}& -{\displaystyle \frac{R_D+R_{L2}+R//R_{C2}}{L_2}}& 0& -{\displaystyle \frac{R}{L_2\left(R+R_{C2}\right)}}\\ {\displaystyle \frac{1}{C_1}}& 0& 0& 0\\ 0& {\displaystyle \frac{R}{C_2\left(R+R_{C2}\right)}}& 0& -{\displaystyle \frac{1}{C_2\left(R+R_{C2}\right)}}\end{array}\right]\left(\begin{array}{c}{i}_{L1}\\ i_{L2}\\ u_{C1}\\ u_{C2}\end{array}\right)+\left[\begin{array}{c}0\\ -{\displaystyle \frac{1}{L_2}}\\ 0\\ 0\end{array}\right]\left(u_1\right)+\left(\begin{array}{c}-{\displaystyle \frac{V_D}{L_1}}\\ -{\displaystyle \frac{V_D}{L_1}}\\ 0\\ 0\end{array}\right)\hspace{0.33em}\left|\cdot \left(1-d\right)\right..$$

(55)

In continuous mode, it is easy to combine the two matrix Equations (51) and (55) by weighting the first one by the duty cycle d, and the second one by 1 − d. Solving the result of this operation (called state-space averaging) leads to a model that can be calculated much faster than the circuit simulation. Only the mean values are shown. With the state vector x, the input vector u (which is in our case only the input voltage), the state matrix A, the input matrix B, and a constant vector—which includes the constant part of the forward voltage of the diode—one gets

$${\displaystyle \frac{d}{dt}}\left(\begin{array}{c}{u}_{C1}\\ u_{C2}\\ i_{L1}\\ i_{L2}\end{array}\right)=A\left(\begin{array}{c}{u}_{C1}\\ u_{C2}\\ i_{L1}\\ i_{L2}\end{array}\right)+B\left(u_1\right)+Const, \mathrm{with}$$

(56)

$$A=\left[\begin{array}{cccc}-{\displaystyle \frac{R_{S}d+\left(R_{C1}+R_D\right)\left(1-d\right)+R_{L1}}{L_1}}& -{\displaystyle \frac{R_{S}d+R_D\left(1-d\right)}{L_1}}& -{\displaystyle \frac{1-d}{L_1}}& 0\\ -{\displaystyle \frac{R_{S}d+R_D\left(1-d\right)}{L_2}}& -{\displaystyle \frac{\left(R_{C1}+R_S\right)d+R_D\left(1-d\right)+R_{L2}+R//R_{C2}}{L_2}}& {\displaystyle \frac{d}{L_2}}& -{\displaystyle \frac{R}{L_2\left(R+R_{C2}\right)}}\\ {\displaystyle \frac{1-d}{C_1}}& -{\displaystyle \frac{d}{C_1}}& 0& 0\\ 0& {\displaystyle \frac{R}{C_2\left(R+R_{C2}\right)}}& 0& -{\displaystyle \frac{1}{C_2\left(R+R_{C2}\right)}}\end{array}\right],$$

(57)

$$B=\left[\begin{array}{c}{\displaystyle \frac{d}{L_1}}\\ -{\displaystyle \frac{1-d}{L_2}}\\ 0\\ 0\end{array}\right], Const=\left(\begin{array}{c}-{\displaystyle \frac{V_D\left(1-d\right)}{L_1}}\\ -{\displaystyle \frac{V_D\left(1-d\right)}{L_2}}\\ 0\\ 0\end{array}\right).$$

(58)

4.3. Idealized Model with Equivalent Resistor Type III

In the first step, one can use the idealized model—which is obtained by setting all parasitic resistors to zero—for calculating the transfer functions. The idealized large signal model can, therefore, be written according to

$${\displaystyle \frac{d}{dt}}\left(\begin{array}{c}{i}_{L1}\\ i_{L2}\\ u_{C1}\\ u_{C2}\end{array}\right)=\left[\begin{array}{cccc}0& 0& -{\displaystyle \frac{1-d}{L_1}}& 0\\ 0& 0& {\displaystyle \frac{d}{L_2}}& -{\displaystyle \frac{1}{L_2}}\\ {\displaystyle \frac{1-d}{C_1}}& -{\displaystyle \frac{d}{C_1}}& 0& 0\\ 0& {\displaystyle \frac{1}{C_2}}& 0& -{\displaystyle \frac{1}{C_{2}R}}\end{array}\right]\left(\begin{array}{c}{i}_{L1}\\ i_{L2}\\ u_{C1}\\ u_{C2}\end{array}\right)+\left[\begin{array}{c}{\displaystyle \frac{d}{L_1}}\\ {\displaystyle \frac{d-1}{L_2}}\\ 0\\ 0\end{array}\right]\left(u_1\right),$$

(59)

Linearization around the operating point (marked by capital letters) leads to the small signal model (the disturbances are marked by hatted small letters)

$${\displaystyle \frac{d}{dt}}\left(\begin{array}{c}{\stackrel{\wedge }{i}}_{L1}\\ {\stackrel{\wedge }{i}}_{L2}\\ {\stackrel{\wedge }{u}}_{C1}\\ {\stackrel{\wedge }{u}}_{C2}\end{array}\right)=\left[\begin{array}{cccc}0& 0& {\displaystyle \frac{D_0-1}{L_1}}& 0\\ 0& 0& {\displaystyle \frac{D_0}{L_2}}& -{\displaystyle \frac{1}{L_2}}\\ {\displaystyle \frac{1-D_0}{C_1}}& -{\displaystyle \frac{D_0}{C_1}}& 0& 0\\ 0& {\displaystyle \frac{1}{C_2}}& 0& -{\displaystyle \frac{1}{C_{2}R}}\end{array}\right]\left(\begin{array}{c}{\stackrel{\wedge }{i}}_{L1}\\ {\stackrel{\wedge }{i}}_{L2}\\ {\stackrel{\wedge }{u}}_{C1}\\ {\stackrel{\wedge }{u}}_{C2}\end{array}\right)+\left[\begin{array}{cc}{\displaystyle \frac{D_0}{L_1}}& {\displaystyle \frac{U_{C10}+U_{10}}{L_1}}\\ {\displaystyle \frac{D_0-1}{L_2}}& {\displaystyle \frac{U_{C10}+U_{10}}{L_2}}\\ 0& -{\displaystyle \frac{I_{L10}+I_{L20}}{C_1}}\\ 0& 0\end{array}\right]\left(\begin{array}{c}{\stackrel{\wedge }{u}}_1\\ \stackrel{\wedge }{d}\end{array}\right).$$

(60)

The small signal model now has two input variables: the input voltage and the duty cycle. For the connections between the operating point values of one stage, one gets

$${\displaystyle \frac{U_{C10}}{U_{10}}}={\displaystyle \frac{D_0}{1-D_0}}, {\displaystyle \frac{U_{C20}}{U_{10}}}={\displaystyle \frac{2D_0-1}{1-D_0}}, {\displaystyle \frac{I_{L10}}{I_{LOAD}}}={\displaystyle \frac{D_0}{1-D_0}}, {\displaystyle \frac{I_{L20}}{I_{LOAD}}}=1$$

(61)

The output current is equal to the currents through the output coils of the stages.

4.4. Simulation Type III

4.4.1. Steady-State

The steady state is shown in Figure 25. Depicted are the following: the input current, the currents through the coils of stage 2, the load current; in the next graph, the currents through the coils of stage 1 and the load current; and in the final graph, the absolute value of the output voltage, the voltage across the output capacitor of stage 1, the input voltage, and the control signals of the switches.

4.4.2. Dynamic Analyses

Figure 26 shows the start-up, changes in the duty cycle, and steps of the input voltage. Depicted are the following: the current through the second coil, the current through the first coil, the duty cycle, the input voltage, the output voltage of stage 1, and the output voltage of the complete converter. The ramp in the duty cycle should be slower to avoid the overcurrent through the first coils of the stage during start-up.

Figure 26. Type III: (a) Simulation circuit. (b) Top to bottom—current through the second coil (violet); current through the first coil (red); duty cycle (gray); input voltage (blue), output voltage of stage 1 (turquoise), output voltage (green).

Figure 26. Type III: (a) Simulation circuit. (b) Top to bottom—current through the second coil (violet); current through the first coil (red); duty cycle (gray); input voltage (blue), output voltage of stage 1 (turquoise), output voltage (green).

In Figure 27, the same signals are shown, but calculated with the differential Equation (53). The voltages show good agreement. The ringing of the currents is more pronounced and reaches negative values, caused by the fact that in the circuit, the diodes stop the current, but in the model, the current can ring freely. When the duty cycle changes with a ramp, both simulation results are equal.

4.5. Inrush Type III

As can be seen in Figure 26 and Figure 27, an inrush occurs. One can see the pronounced ringing through the coils and the transients of the voltages at the output of the stages and at the output of the complete converter.

During inrush, the output capacitors are charged to half of the input voltage; the output voltage is, therefore, zero. The output voltages of the two stages are not inverted.

To avoid problems with the inrush, the input voltage can be increased linearly by a pre-stage; this is demonstrated in Figure 28. The ramp takes 50 ms, and so the input current is only small. The voltages change without ringing in the used scale.

5. Floating Two-Stage Converter Type IV

5.1. Basics of Type IV

The second topology to achieve the voltage transformation ratio according to

$$M={\displaystyle \frac{U_2}{U_1}}=2{\displaystyle \frac{2d-1}{1-d}}+1={\displaystyle \frac{3d-1}{1-d}} \mathrm{with} \mathrm{the} \mathrm{restriction} d\ge 0.5$$

(62)

is shown in Figure 29.

The graph of the voltage transformation ratio can be found in Figure 22.

5.2. Steady-State Type IV

Figure 30 shows the behavior of the converter in the steady state. It works similarly to type V. The input current is pulsating, but always flowing into the converter. One can see the large output voltage compared to the input voltage. Shown are the input current, the currents through all coils, the output current, the input voltage, the control signals, the output voltage of one stage (dark blue), and the output voltage.

5.3. Dynamic Simulation Type IV

The dynamic simulation (Figure 31) shows the typical behavior of the here-treated converters.

5.4. Model with Equivalent Resistor Type IV

The state matrix A, the input matrix B, and the constant vector are given as follows:

$$A=\left[\begin{array}{cccc}-{\displaystyle \frac{\left(R_{C1}+R_S\right)d+\left(R_D+R//R_{C2}\right)\left(1-d\right)+R_{L1}}{L_1}}& -{\displaystyle \frac{R_{S}d+\left(R_D+R//R_{C2}\right)\left(1-d\right)}{L_1}}& {\displaystyle \frac{d}{L_1}}& -{\displaystyle \frac{R\left(1-d\right)}{L_1\left(R+R_{C2}\right)}}\\ -{\displaystyle \frac{R_{S}d+\left(R_D+R//R_{C2}\right)\left(1-d\right)}{L_2}}& -{\displaystyle \frac{R_{S}d+\left(R_{C1}+R_D+R//R_{C2}\right)\left(1-d\right)+R_{L2}}{L_2}}& -{\displaystyle \frac{1-d}{L_2}}& -{\displaystyle \frac{R\left(1-d\right)}{L_2\left(R+R_{C2}\right)}}\\ -{\displaystyle \frac{d}{C_1}}& {\displaystyle \frac{1-d}{C_1}}& 0& 0\\ {\displaystyle \frac{R\left(1-d\right)}{C_2\left(R+R_{C2}\right)}}& {\displaystyle \frac{R\left(1-d\right)}{C_2\left(R+R_{C2}\right)}}& 0& -{\displaystyle \frac{1}{C_2\left(R+R_{C2}\right)}}\end{array}\right],$$

(63)

$$B=\left[\begin{array}{c}-{\displaystyle \frac{1-d}{L_1}}\\ {\displaystyle \frac{d}{L_2}}\\ 0\\ 0\end{array}\right], Const=\left(\begin{array}{c}-{\displaystyle \frac{V_D\left(1-d\right)}{L_1}}\\ -{\displaystyle \frac{V_D\left(1-d\right)}{L_2}}\\ 0\\ 0\end{array}\right).$$

(64)

The idealized model can easily be found by setting the parasitics to zero. From this idealized model, the transfer functions can be obtained. Figure 32 shows the currents through the coils, the duty cycle, the output voltage of one stage, the input voltage, and the output voltage of one stage and of the complete converter.

Figure 32. Type IV: (a) Simulation circuit. (b) Top to bottom—current through the second coil (violet); current through the first coil (red); duty cycle (gray); input voltage (blue), output voltage of one stage (turquoise), output voltage (green).

Figure 32. Type IV: (a) Simulation circuit. (b) Top to bottom—current through the second coil (violet); current through the first coil (red); duty cycle (gray); input voltage (blue), output voltage of one stage (turquoise), output voltage (green).

Setting the input voltage and the duty cycle as constant, one can easily draw the Bode plot for that operating point; this is shown in Figure 33. A fourth-order converter has two conjugate complex poles, which shift the phase by minus 360 degrees. The poles can be seen as the two resonances. The transfer function has three zeroes. One of them is a conjugate complex on the left side of the complex plane, which shifts the phase by plus 180 degrees, and the third zero is on the right side of the complex plane and causes a phase shift of minus 90 degrees. At high frequencies, the phase of the converter tends towards minus 270 degrees. Bode diagrams are important for the design of controllers. From the Bode plot, one can also take the frequencies of the poles and the zeroes. The resonant poles have the frequencies at 360 Hz and 1.3 kHz; the resonant zero is at 1.1 kHz; and the zero on the right side of the complex plane is far away at 28 kHz.

Figure 33. Type IV Bode diagram: (a) simulation circuit; (b) connection between the output voltage of one stage in dependence on the duty cycle; solid line: gain, dotted line: phase.

Figure 33. Type IV Bode diagram: (a) simulation circuit; (b) connection between the output voltage of one stage in dependence on the duty cycle; solid line: gain, dotted line: phase.

5.5. Inrush Type IV

The inrush can be avoided by a damping resistor (Figure 34) that is shunted later or by increasing the input voltage slowly (Figure 35). The second variant can also be used as an electronic fuse.

5.6. Influence of the Tolerances

The influence of the tolerances is shown for type IV, but is also valid for the other three types. Figure 36 shows the input current, the currents through the coils, the load current, the input voltage, the control signals, and the output voltage when the values of the inductors of the second stage differ from those of the first stage by plus/minus 10%. The slopes of the current are changing, but the load current and the output voltage stay constant compared to Figure 30.

Figure 37 shows the same signals as before, but now the output voltages of the stages are included, and the duty cycle of the stages differs by 5%. The stage with the larger duty cycle has the higher output voltage. The output currents are still equal. This automatic symmetrizing is a great advantage of these converter types. In the case of the interleaved converter with parallel connections of the stages, a large asymmetry in the output currents of the stages occurs.

6. Conclusions

The main purpose of this paper is to present four converters with high voltage transformation ratios because the output voltages of both stages are added with the input voltage. The efficiency is checked by the simulations. The load is 60 Ω, Uin = 24 V for all types, the duty cycle is 0.4 for types I and II, the output voltage is near 132 V, and the efficiency is 93.4% and 95.8%, respectively. The duty cycle for types III and IV is chosen as 0.8, leading to an output voltage of about 180 V and an efficiency of 96.8% and 96.5%, respectively. The efficiency is a little bit higher for types III and IV, because the conducting time of the diodes is only 20% of the switching period.

The methods used to study the circuits are as follows:

• Basics were found by inspecting the circuits in the steady state;
• Circuit simulation with the help of LTSpice XVII from Analog Devices for the steady state and for the transients—the calculation time is long;
• Calculating a state-space averaging model and solving the differential equations again by LTSpice—the calculation time is short and the results are correct when the changes are so small that the converter stays in continuous mode;
• Bode plots can be fast and easily achieved from the circuit, which solves the differential equations;
• An error in the state-space model can be immediately found by the results of the simulation used.

Interesting features of the treated converters are outlined below:

• They are floating, which means one can take a terminal of the input side or of the output side as reference.
• Higher voltage transformation ratio because the two output voltages of the stages, plus the input voltage, are added.
• Two different voltage transformation ratios can be achieved.
• The duty cycle of the stages is limited—it must be lower than 0.5 for types I and II, and higher than 0.5 for types III and IV.
• The voltage stress of the components of the stages is lower than the voltage across the output of the complete converter—the stages have to be dimensioned only for half of this voltage.
• The output current of the stages is equal to the load current, and symmetrizes the current through the stages.
• The output voltage is directly influenced by the input voltage. To reduce this, reverse-polarity protection consisting of a diode and a capacitor can be connected between the source and the converter.
• Type I has the additional advantage that the start-up is easy when slowly increasing the duty cycle from zero to the desired value; no inrush current occurs. All other types need a pre-stage when the start-up is problematic. Therefore, type I was studied more comprehensively.