Efficiency Optimization of a Series-Resonant Dual-Active-Bridge Converter with Voltage-Doubler Rectification

Abstract

This paper investigates a dual-active-bridge (DAB) converter topology based on a voltage-doubler rectifier and series resonant network. By integrating phasor-domain analysis with time-domain modeling, a comprehensive mathematical model of the output voltage and instantaneous inductor current is established. The voltage gain expression is further refined by accounting for the effects of dead-time and power switch output capacitance. Based on this model, a multi-objective global optimization is performed, aiming to minimize reactive power, RMS current, and switch conduction losses, while simultaneously satisfying zero-voltage switching (ZVS) conditions and voltage gain requirements. Leveraging the optimization results, an extended phase-shift control strategy incorporating phase-shift feedforward and frequency closed-loop regulation is proposed. Experimental results demonstrate that the proposed topology achieves high efficiency across the entire operating range, with a peak efficiency of 96.92%. The results validate the effectiveness and engineering practicability of both the topology and the control scheme.

1. Introduction

With the rapid development of photovoltaic and energy storage systems, high-efficiency and high-power-density power electronic converters have become key enablers for efficient energy conversion and flexible power management [1,2]. The series-resonant dual-active-bridge (SRDAB) converter, as an evolution of the conventional dual-active-bridge (DAB) topology [3,4], offers significant advantages such as inherent soft-switching capability, bidirectional power flow, and galvanic isolation [5]. These features make it highly promising for applications in solid-state transformers, renewable energy storage systems, bidirectional electric vehicle charging, and micro-inverters [6,7,8,9]. Compared to the traditional DAB, the SRDAB incorporates a series resonant tank, which extends the soft-switching range [10], reduces voltage stress, suppresses current harmonics, and thereby enhances both power density and overall efficiency—making it a focal point of recent research in both academia and industry.

In this paper, we focus on an SRDAB topology employing a voltage-doubler rectifier on the secondary side. This configuration reduces the number of power switches on the transformer secondary, thereby lowering conduction losses and further improving power density, which is particularly advantageous for low-to-medium power applications.

Despite extensive studies on SRDAB converters, critical challenges remain unresolved, especially for topologies with voltage-doubler rectification. First, the widely adopted fundamental harmonic approximation (FHA) method simplifies modeling but neglects higher-order harmonics, leading to significant inaccuracies when the switching frequency deviates from resonance [11,12,13,14]. Second, existing optimization strategies often target only reactive power or RMS current minimization [15,16,17], yet they fail to simultaneously consider zero-voltage switching (ZVS) constraints and conduction losses, resulting in suboptimal efficiency across wide input/output ranges. Third, practical non-ideal factors such as dead time and switch output capacitance ($C_{oss}$) introduce phase delays that degrade model accuracy and control performance, but they are rarely incorporated into analytical models. Finally, some advanced control schemes involve complex analytical expressions that hinder real-time implementation on embedded platforms like microcontrollers or DSPs [18].

Therefore, there exists a clear need for a comprehensive modeling and control framework, due to: (i) lack of high-fidelity models accounting for dead time and Coss-induced phase shifts; (ii) absence of a unified optimization objective balancing ZVS, conduction loss, and reactive power under wide operating conditions; and (iii) limited practicality of existing control strategies for digital implementation. To address these gaps, this paper proposes a phasor-time domain hybrid modeling approach for the voltage-doubler-based SRDAB converter, enabling accurate analysis beyond the limitations of FHA [19]. The voltage gain model is refined by incorporating the effects of dead time and $C_{oss}$, significantly improving accuracy across the entire operating range [20]. Furthermore, a novel multi-objective optimization is performed to minimize the root-mean-square (RMS) value of the switching instantaneous current, defined as $\sqrt{i_L{\left(t_0\right)}^2+i_L{\left(t_1\right)}^2+2i_L{\left(t_2\right)}^2}$, which simultaneously reduces conduction losses, reactive power, and ensures ZVS feasibility. Based on the optimization results, an extended phase-shift (EPS) control strategy with phase-shift feedforward and frequency closed-loop regulation is developed, facilitating real-time implementation on low-cost digital controllers. Experimental validation on a 3 kW prototype demonstrates a peak efficiency of 96.92%, verifying the effectiveness and engineering practicability of the proposed methodology.

2. Operating Principle of the Voltage-Doubler-Based SRDAB Converter

2.1. Topology Description

This section analyzes the operation of the voltage-doubler-based series-resonant dual-active-bridge (SRDAB) converter under forward power transfer, as illustrated in Figure 1. The main circuit consists of an input H-bridge, a high-frequency transformer $T_r$, a resonant inductor $L_r$, and a voltage-doubler rectifier. Assuming ideal switching with the duty ratio 50% for all power switches (neglecting dead time), the transformer turns ratio is defined as $N_{tr}$:1.

When the output filter capacitor $C_o$ is sufficiently large, the output voltage $V_o$ can be considered constant within one control cycle and is equivalent to a DC source. By referring the secondary-side voltage to the primary side, the equivalent circuit of the SRDAB converter is obtained, as shown in Figure 2. Due to the symmetry of the voltage-doubler structure, the effective transformer turns ratio is half that of a conventional SRDAB. In the high-frequency resonant path, two resonant capacitors C are connected in parallel on the secondary side. When referred to the primary side, the total resonant capacitance is $C_r=2C/N_{tr}^2$, and the total resonant inductance is $L_r=N_{tr}^{2}L$.

Figure 3 illustrates the key waveforms under extended phase-shift (EPS) control. $V_i$ and $V_o$ denote the input and output DC voltages, respectively. $u_{AB}$ and $u_{CD}$ are the AC voltages across the primary and secondary bridge arms, $i_L$ is the resonant inductor current, $f_s$ is the switching frequency, and $f_r$ is the resonant frequency. The inner phase shift is denoted as ${\varphi }_1$, and the outer phase shift as ${\varphi }_2$.The normalized phase-shift ratios are defined as $D_1={\varphi }_1/\pi$ and $D_2={\varphi }_2/\pi$. Under forward power flow, the ranges of $D_1$ and $D_2$ are $0<D_1<1$ and $0<D_2<1$.

2.2. Phasor-Time Domain Hybrid Modeling

In the equivalent circuit, the primary voltage $u_{AB}$ can be decomposed into the sum of two square waves, each with amplitude $V_i/2$, and phase angles of 0 and $-{\varphi }_1$, respectively. The secondary voltage $u_{CD}$ has an amplitude of $V_o/2$. Using Fourier series expansion:

$$u_{AB}={\displaystyle \frac{2V_i}{\pi }}\sum _{n=1,3,5,\dots }^{\infty }{\displaystyle \frac{sin\left(n\omega t\right)}{n}}+{\displaystyle \frac{2V_i}{\pi }}\sum _{n=1,3,5,\dots }^{\infty }{\displaystyle \frac{sin(n\omega t-n{D}_1\pi )}{n}}$$

(1)

$$u_{CD}={\displaystyle \frac{2N_{tr}{V}_o}{\pi }}\sum _{n=1,3,5,\dots }^{\infty }{\displaystyle \frac{sin(n\omega t-n{D}_2\pi )}{n}}$$

(2)

where $\omega =2\pi f_s$. According to the superposition principle, instantaneous and average values of voltage, current, and power can be obtained by summing harmonic components. The phasor representation of the n-th harmonic is:

$${\dot{u}}_{AB\left(n\right)}={\displaystyle \frac{\sqrt{2}{V}_i}{n\pi }}\left(cos\left(n{D}_1\pi \right)-jsin\left(n{D}_1\pi \right)+1\right)$$

(3)

$${\dot{u}}_{CD\left(n\right)}={\displaystyle \frac{\sqrt{2}{N}_{tr}{V}_o}{n\pi }}\left(cos\left(n{D}_2\pi \right)-jsin\left(n{D}_2\pi \right)\right)$$

(4)

The n-th harmonic phasor of the inductor current is:

$${\dot{i}}_{L\left(n\right)}={\displaystyle \frac{{\dot{u}}_{AB\left(n\right)}-{\dot{u}}_{CD\left(n\right)}}{\frac{1}{j\omega C_r}+j\omega L_r}}$$

(5)

The complex power is given by:

$${\dot{S}}_{\left(n\right)}={\dot{u}}_{AB\left(n\right)}{\dot{i}}_{L\left(n\right)}^{*}=P_{\left(n\right)}+j{Q}_{\left(n\right)}$$

(6)

where $P_{\left(n\right)}$ and $Q_{\left(n\right)}$ are the active and reactive power of the n-th harmonic. The total output active power $P_o$ and reactive power $Q_o$ are:

$$P_o=\sum _{n=1,3,5\dots }^{\infty }{\displaystyle \frac{2N_{tr}F{V}_i{V}_o\left(sin\left(n(D_1-D_2)\pi \right)-sin\left(n{D}_2\pi \right)\right)}{n{\pi }^2{Z}_r(1-n^2{F}^2)}}$$

(7)

$$Q_o=\sum _{n=1,3,5\dots }^{\infty }{\displaystyle \frac{2N_{tr}F{V}_i{V}_o\left(cos\left(n(D_1-D_2)\pi \right)+cos\left(n{D}_2\pi \right)\right)-V_i-V_{i}cos\left(n{D}_1\pi \right)}{n{\pi }^2{Z}_r(1-n^2{F}^2)}}$$

(8)

Let the characteristic impedance be $Z_r=\sqrt{L_r/C_r}$ and the frequency ratio $F=f_s/f_r$. Neglecting losses, the output power is fully delivered to the load resistor $R_o$, i.e., $P_o=V_o^2/R_o$. Thus, the output voltage is:

$$V_o=\sum _{n=1,3,5\dots }^{\infty }{\displaystyle \frac{2N_{tr}F{R}_o{V}_i\left(sin\left(n(D_1-D_2)\pi \right)-sin\left(n{D}_2\pi \right)\right)}{n{\pi }^2{Z}_r(1-n^2{F}^2)}}$$

(9)

To facilitate the subsequent numerical solution, the series can be summed up to obtain the time-domain expression of $V_o$ as follows:

$$V_o={\displaystyle \frac{N_{tr}F{V}_i{R}_o}{\pi Z_{r}cos\left(\frac{\pi }{2F}\right)}}\left(sin\left({\displaystyle \frac{|D_2-D_1|}{2F}}\pi \right)sin\left({\displaystyle \frac{1-|D_2-D_1|}{2F}}\pi \right)+sin\left({\displaystyle \frac{D_2}{2F}}\pi \right)sin\left({\displaystyle \frac{1-D_2}{2F}}\pi \right)\right)$$

(10)

The time-domain expression of the inductor current is obtained via inverse phasor transformation:

$$i_{L\left(n\right)}\left(t\right)=\mathrm{Im}\left(i_{L\left(n\right)}^{*}{e}^{j\omega t}\right)$$

(11)

$$i_L\left(t\right)=\sum _{n=1,3,5\dots }^{\infty }{\displaystyle \frac{2N_{tr}F{V}_{o}cos(n{D}_2\pi -n\omega t)-2F{V}_i\left(cos(n{D}_2\pi -n\omega t)+cos\left(n\omega t\right)\right)}{\pi Z_r(n^2{F}^2-1)}}$$

(12)

At key switching instants $t_0$, $t_1$, $t_2$ substituting into Equation (10) and summing the series yields the instantaneous inductor current:

$$\left\{\begin{array}{cc}\hfill i_L\left(t_0\right)& ={\displaystyle \frac{N_{tr}{V}_{o}sin\left({\displaystyle \frac{\pi -2D_2\pi }{2F}}\right)-V_{i}sin\left({\displaystyle \frac{\pi -2D_1\pi }{2F}}\right)-V_{i}sin\left({\displaystyle \frac{\pi }{2F}}\right)}{2Z_{r}cos\left({\displaystyle \frac{\pi }{2F}}\right)}}\hfill \\ \hfill i_L\left(t_1\right)& ={\displaystyle \frac{N_{tr}{V}_{o}sin\left({\displaystyle \frac{\pi -2|D_2-D_1|\pi }{2F}}\right)-V_{i}sin\left({\displaystyle \frac{\pi -2D_1\pi }{2F}}\right)-V_{i}sin\left({\displaystyle \frac{\pi }{2F}}\right)}{2Z_{r}cos\left({\displaystyle \frac{\pi }{2F}}\right)}}\hfill \\ \hfill i_L\left(t_2\right)& ={\displaystyle \frac{N_{tr}{V}_{o}sin\left({\displaystyle \frac{\pi }{2F}}\right)-V_{i}sin\left({\displaystyle \frac{\pi -2|D_2-D_1|\pi }{2F}}\right)-V_{i}sin\left({\displaystyle \frac{\pi -2D_2\pi }{2F}}\right)}{2Z_{r}cos\left({\displaystyle \frac{\pi }{2F}}\right)}}\hfill \end{array}\right.$$

(13)

The RMS value of the inductor current is:

$$i_{RMS}=\sqrt{\sum _{n=1,3,5,\dots }^{\infty }{i}_{RMS\left(n\right)}^2}=\sqrt{\sum _{n=1,3,5,\dots }^{\infty }{\left({\displaystyle \frac{i_{max\left(n\right)}}{\sqrt{2}}}\right)}^2}$$

(14)

where $i_{RMS\left(n\right)}$ and $i_{max\left(n\right)}$ are the RMS value and the maximum value of the n-th harmonic component of the inductor current.

3. Output Voltage Gain Correction Considering Dead Time and Parasitic Parameters

In practical applications, dead time is introduced to prevent shoot-through faults in power switches. However, this results in an effective duty cycle of the AC bridge voltages that is less than 50%, leading to inaccuracies in the voltage gain and current expressions derived under ideal square-wave assumptions.

Although a full time-domain segmentation of the $C_{oss}$-$L_r$ resonant process [21] could offer higher modeling precision, such an approach imposes significant computational overhead. Instead, we approximate the net impact of $C_{oss}$, the charge during dead time, as an equivalent reduction in active duty cycles, which is compensated via feedforward. Any residual deviation is effectively regulated by the closed-loop frequency controller, ensuring robust ZVS without requiring cycle-by-cycle harmonic analysis. Therefore, the output capacitance $C_{oss}$ of power devices interacts with the inductor current $i_L$ during the dead time, generating a voltage variation $\mathrm{\Delta }u=i_L{t}_d/C_{oss}$. When the dead time $t_d$ is relatively large compared to $C_{oss}$, this voltage variation can sustain the bridge output level, causing a phase delay that effectively alters the phase-shift angle. Therefore, phase-shift compensation is necessary to improve model accuracy.

Taking the secondary-side driving signals as an example, as shown in Figure 4a, at time $t_2$, if $t_2<0$, the current charges $C_{oss}$, maintaining the negative voltage level during the dead time and resulting in a phase delay of $t_d{f}_s$. Similarly, at $t_5$, if $t_5>0$, the positive level is sustained, also introducing a delay of $t_d{f}_s$. Consequently, the effective outer phase shift becomes $D_2+t_d{f}_s$. In contrast, as shown in Figure 4b, when $t_2>0$ and $t_5<0$, the current direction during dead time does not support voltage hold, resulting in no phase delay, and thus no compensation is required.

By analyzing the direction of inductor current at key switching instants and its impact on phase delay, a phase-shift compensation mechanism is established.

Table 1. Phase delay and output voltage expressions after phase-shift compensation.

${\mathit{i}}_{\mathit{L}}\left({\mathit{t}}_0\right)$	${\mathit{i}}_{\mathit{L}}\left({\mathit{t}}_1\right)$	${\mathit{i}}_{\mathit{L}}\left({\mathit{t}}_2\right)$	Compensated Output Voltage ${\mathit{V}}_{\mathit{o}\_\mathit{td}}$
>0	>0	<0	$V_o(D_1,D_2)$
<0	<0	>0	$V_o(D_1,D_2)$
>0	>0	>0	$V_o(D_1,D_2-t_d{f}_s)$
<0	<0	<0	$V_o(D_1,D_2+t_d{f}_s)$
<0	>0	>0	$V_o(D_1+t_d{f}_s,D_2)$
<0	>0	<0	$V_o(D_1+t_d{f}_s,D_2+t_d{f}_s)$

summarizes the phase delays and corresponding compensated output voltage $V_{o\_td}$ expressions under forward power flow (where $D_1>0$ and $i_L\left(t_1\right)\ge i_L\left(t_0\right)$).

With the proposed compensation strategy, a more accurate prediction of the output voltage is achieved, laying the foundation for high-efficiency control design.

4. Efficiency Optimization Under Soft-Switching Conditions

4.1. Reactive Power and RMS Current Minimization

To achieve zero-voltage switching (ZVS) for power switches, the output capacitance $C_{oss}$ must be fully discharged before the gate signal is applied, which requires the inductor current to be negative at turn-on, i.e., $i_L<0$. Thus, ZVS feasibility can be evaluated using Equations (13) and (15):

$$\left\{\begin{array}{cc}\hfill i_L\left(t_0\right)& <0\hfill \\ \hfill i_L\left(t_1\right)& <0\hfill \\ \hfill i_L\left(t_2\right)& >0\hfill \end{array}\right.$$

(15)

Due to the complexity of the time-domain model of the voltage-doubler-based SRDAB, an analytical optimal solution is difficult to derive under Karush–Kuhn–Tucker (KKT) conditions. This paper adopts a numerical optimization approach: given fixed hardware parameters, the objective function is minimized subject to constraints such as ZVS conditions and output voltage regulation. The optimization results are then plotted and curve-fitted for practical implementation. The proposed method is applicable over wide input and output ranges. The following parameters are used for illustration: transformer turns ratio $N_{tr}=$ 1:4, resonant inductance $L_r=1$ µH, equivalent resonant capacitance $C_r=5.12$ µF, input voltage range $V_i=$ 42–58 V, regulated output voltage (after dead-time compensation) $V_0=400$ V, and dead time $t_d=200$ ns.

First, reactive power minimization (as Equation (6)) is performed, and the results are shown in Figure 5. It can be observed that the inner phase-shift ratio $D_1$ is consistently zero, indicating that single-phase-shift control is sufficient for optimal performance. Moreover, the outer phase shift $D_2$ varies slightly across different load levels, which facilitates a unified control strategy from light to heavy loads.

Second, RMS current minimization (based on Equation (12)) is conducted, with the results shown in Figure 6. The analysis shows that $D_1$ remains zero, again validating the effectiveness of SPS control. However, $D_2$ varies significantly with load power, necessitating output current feedforward in closed-loop control to enhance the dynamic response.

4.2. Minimization of RMS Switching Instantaneous Current

Although $i_L\left(t\right)<0$ ensures ZVS for switch $Q_1$, a large current magnitude at turn-on leads to increased cross-conduction losses and significant reactive circulating current, degrading overall efficiency. To address this trade-off, this paper proposes a novel optimization objective: minimization of the root-mean-square (RMS) of the switching instantaneous current, defined as:

$$i_{RMS\_SW}=\sqrt{i_L{\left(t_0\right)}^2+i_L{\left(t_1\right)}^2+2i_L{\left(t_2\right)}^2}$$

(16)

This metric comprehensively evaluates current stress at the three critical switching instants, aiming to balance ZVS feasibility with conduction loss minimization. The optimization results are presented in Figure 7. Key observations include:

• At $V_i=50$ V, $D_1=D_2=0$, and $f_s=f_r$, the system operates near resonance in an open-loop manner, resembling an LLC resonant converter, achieving peak efficiency;
• When $V_i<50$ V, $D_1$ is close to zero, resulting in SPS-like behavior;
• When $V_i>50$ V, $D_1\approx D_2$, equivalent to primary-side internal phase-shift control, similar to a phase-shift full-bridge (PSFB) converter.

Compared with Figure 5 and Figure 6, the proposed method requires the smallest frequency regulation range.

4.3. Closed-Loop Control Design and Implementation

When $D_1$ and $D_2$ are fixed, the output voltage $V_o$ is a monotonically decreasing function of the switching frequency $f_s$, as indicated by Equation (10). As shown in Figure 7, load power has a noticeable impact on $D_1$ and $D_2$, requiring output current feedforward in closed-loop control for improved accuracy. Based on the above optimization, a closed-loop control scheme is proposed, as illustrated in Figure 8. The components are defined as follows:

• $V_{r}ef$: reference output voltage;
• $I_o$: sampled output current;
• $D_1,D_2,f_0$: phase-shift ratios and base frequency calculated online from fitted optimization curves;
• $f_{s\_min},f_{s\_max}$: minimum and maximum allowable switching frequencies.

The polynomial fitting formula is obtained by performing polynomial fitting on the optimized results of Figure 7 using Mathcad.The feedforward frequency command $f_0$, derived from the fitting formula, is continuously updated based on real-time measurements of input voltage $V_o$ and output current $I_o$. This adaptive feedforward mechanism plays a pivotal role in maintaining system robustness:

• During load transients, it proactively shifts the operating point to the new optimal frequency, minimizing the magnitude and duration of resonant current excursions;
• More importantly, it ensures ZVS for all power switches—even under worst-case step-load conditions.

Without this feedforward action, the feedback loop alone would respond too slowly to prevent temporary entry into the capacitive region, risking hard switching and potentially destructive $V_{DS}$ spikes on the MOSFETs. The PI-based feedback loop thus operates as a fine-tuning element, correcting only minor modeling mismatches or disturbances, while the bulk of the dynamic response is handled by the physics-informed feedforward path.

5. Experimental Validation

5.1. Prototype Setup

To validate the proposed mathematical model, optimization methods, and control strategy, a 3 kW experimental prototype was built, as shown in Figure 9.

The main circuit parameters are listed in

Table 2. Key parameters of the experimental prototype.

Parameter	Value
Input voltage $V_i$ (V)	42–58
Output voltage $V_o$ (V)	400
Transformer turns ratio $N_{tr}$	1:4
Secondary Resonant inductance L (including leakage) (µH)	25
Secondary Resonant capacitor C (nF)	110
Switching frequency $f_s$ (kHz)	70–220

.

5.2. Soft-Switching Performance and Efficiency Evaluation

Figure 10 shows the gate-to-source voltage and resonant inductor current waveforms under 500 W and 2000 W output power, with $V_o=400$ V, at input voltages of 46 V and 54 V, respectively. It can be observed that: At turn-on of $Q_1$ and $Q_4$, $i_L\left(t_0\right)<0,i_L\left(t_1\right)<0$; At turn-on of $Q_5$, $i_L\left(t_2\right)>0$; indicating that all power switches achieve zero-voltage switching (ZVS). These results confirm that the proposed optimization-based control ensures reliable ZVS across wide input voltage and load ranges.

To evaluate the accuracy of the proposed phasor-time domain hybrid model, it is compared with the conventional first-harmonic approximation (FHA) method. The phase-shift ratios and frequencies optimized using the corrected model $V_{o\_td}$ are applied to the FHA-based model. The predicted, simulated, and measured output voltages are plotted in Figure 11. For each $V_i$, the optimal $f_s$, $D_1$, and $D_2$ values are computed using the proposed model to achieve $V_o$ = $V_{o\_td}$ = 400 V. These parameters are then applied to the experimental prototype, PSIM simulation, and FHA model. The resulting $V_o$ values are compared against the target 400 V to assess model accuracy and practical feasibility. It is evident that the corrected phasor-time model matches closely with both simulation and experimental results and exhibits significant deviation, especially under low-input or high-load conditions. This demonstrates the superior accuracy of the proposed model under non-ideal operating scenarios.

Figure 12 presents the efficiency comparison among the three optimization strategies under 1 kW output power while varying $V_i$ from 42 V to 58 V. The results show that when $V_i<50$ V, the efficiencies of all three methods are similar; when $V_i>50$ V, the RMS switching instantaneous current minimization method achieves significantly higher efficiency; when $V_i=58$ V, its efficiency exceeds the other two by approximately 4%. These results validate the superiority of the proposed optimization objective in enhancing overall converter efficiency, particularly under high-input-voltage conditions.

5.3. Dynamic Performance Validation

While steady-state efficiency is a key metric, the practical viability of the proposed control strategy hinges on its ability to maintain regulation, soft-switching, and device safety during transient events. To this end, comprehensive dynamic tests were conducted on the 3 kW prototype under both load-step and line-step conditions. The control architecture—featuring real-time feedforward of $D_1$, $D_2$, and $f_0$ based on measured $V_i$ and $I_o$, augmented by a voltage-mode PI feedback loop—was rigorously evaluated.

The system was subjected to a full-load transient sequence ($V_o$ = 45 V): 0 kW → 1 kW → 3 kW → 1 kW, with all key waveforms captured simultaneously using a digital oscilloscope. As shown in Figure 13, At time $t_1$, the load steps from 0 kW to 1 kW, causing the output current $I_o$ to rise abruptly to 2.5 A. This results in a small undershoot in the output voltage $V_o$ of approximately 5% (20 V), which recovers to within ±1% of the 400 V reference in less than 100 ms. Subsequently, at time $t_2$, the power demand increases further from 1 kW to the rated 3 kW. The output voltage exhibits the same undershoot of 5% (20 V) and settles back to the regulation band (±1%) in under 300 ms. Throughout both transients, the input voltage $V_i$ remains stable, confirming that the observed dynamics are solely due to load variation. Finally, at time $t_3$, when the load steps down from 3 kW to 1 kW, the system demonstrates excellent damping with negligible overshoot and no oscillation, highlighting the robustness of the closed-loop controller.

Figure 14 shows the system response to a ±20% input voltage step ($V_i$: 45 V → 55 V) at full load (3 kW). The output voltage deviation is limited to <3.5%, and the recovery time is under 150 ms. The resonant inductor current $i_L$ responds immediately to the increased input energy, exhibiting a small transient spike before stabilizing at its new operating level. Notably, the output current $i_o$ remains constant at 7.5 A throughout the transition, confirming precise power regulation and effective rejection of input disturbances.

6. Conclusions

This paper has proposed a phasor-time domain hybrid model for the voltage-doubler-based series-resonant dual-active-bridge converter under extended phase-shift control. The model incorporates the effects of dead time and power switch output capacitance $C_{oss}$ on the output voltage gain, significantly improving modeling accuracy across wide input voltage and load ranges.Based on this model, three optimization objectives—reactive power, RMS current, and the proposed RMS of switching instantaneous current—are investigated under constraints of zero-voltage switching (ZVS) and regulated output voltage. A frequency-variable phase-shift control algorithm is then developed accordingly. The proposed modeling and control strategies are experimentally validated on a 3 kW prototype. The experimental results demonstrate that:

1.

The proposed phasor-time domain model achieves high accuracy in predicting output voltage gain and ZVS conditions, closely matching both simulation and measurement data;

2.

The RMS switching instantaneous current minimization strategy achieves higher overall efficiency compared to reactive power minimization and RMS current minimization, with up to 4% efficiency improvement under high-input-voltage conditions;

3.

The proposed optimization and control method ensures reliable ZVS across wide voltage gain and load ranges, fully leveraging the soft-switching advantages of resonant DAB converters.

4.

The real-time feedforward implementation enables fast and stable dynamic response under both load and line transients. Experimental waveforms show that the output voltage recovers from large steps (e.g., 1 kW → 3 kW) within less than 300 ms, with minimal overshoot/undershoot, and maintains regulation during ±20% input voltage variations, confirming the practical viability of the model-driven control approach.