Non-Linear Switching Circuit for Active Voltage Rectification and Ripples Reduction of Piezoelectric Energy Harvesters

Abstract

This paper describes an improved non-linear switching circuit (INLSC) for active rectification of voltage and reduction of ripples in the voltage waveform for the piezoelectric energy harvesting (PEH) system. The proposed converter controls the alternating current (AC) generated by the piezoelectric device (PD) under mechanical vibration. The proposed circuit combines the boost and buck-boost processes through a switching process, which functions in both positive and negative cycles. In addition, it controls the voltage and frequency of the load capacitor. In this process, the passive components in the circuit are energised by being short with the AC voltage using switching signals, which facilitates the active rectification of ultra-low AC voltage. Design considerations, theoretical analysis, simulations and experimental results are presented. It was shown that the circuit was able to control the switching signal and to convert low AC voltage (0.44 V_i) to high direct current (DC) voltage (6.5 V_dc) while achieving an output power of 469 µW which outperforms the existing similar circuits and synchronous rectifier circuit. The ripples in the rectified voltage were also comparatively less. Application-wise, the proposed circuit could power a manually connected 7-segments display, commonly used for traffic applications.

1. Introduction

Power electronic circuits play a significant role in the piezoelectric energy harvesting (PEH) system by acting as a mediator to convert the AC voltage, which is generated by PD from mechanical energy (ME) [1,2,3] into direct current (DC) voltage. In practice, the PD generates limited power due to its high internal impedance and erratic waveform due to random vibrations from nature. Therefore, the efficiency of electronic circuits is essential to minimise losses during the conversion process. The converted DC voltage can be used in various applications, namely charging of storage devices [4], powering of wireless sensor nodes for structural health monitoring and powering small scale devices for military and medical use [5].

Numerous AC-DC rectification circuits for PEH systems have been developed and reported in the literature [6,7,8,9,10,11,12,13,14,15,16,17,18]. The simplest one is a conventional full-bridge rectifier (FBR) circuit. Despite their simplicity and popularity, this rectifier circuit suffers from several limitations: (1) It comprises of diodes, which results in unavoidable voltage drop across them; (2) it does not step up the voltage of PD, which limits its application as most of the electronic devices require 2–3 V_dc; (3) the presence of ripple voltage (V_r) in the converted voltage waveform. Therefore, it is arduous to design a power electronic circuit suitable for converting and boosting the low voltage generated by PD, as well as to reduce the ripples in converted voltage waveform. Various enticed circuits/methods have also been proposed in the literature, namely single-stage, dual-stage, and non-linear circuits. The key difference between the single and the dual-stage circuits is that a single-stage circuit includes AC-DC conversion, while the dual-stage includes AC-DC and DC-DC conversion stages. A flow chart illustrating the process of single and dual-stage circuits for the PEH system is depicted within the context of Figure 1a,b.

A recent study on a single-stage rectifier circuit by the authors [4,19] improved MOSFET bridge rectifier circuit into a self-powered H-Bridge circuit. The proposed circuit was proven applicable with ultra-low voltage and high-frequency excitation. The outcome showed that the proposed circuit notably increased the output voltage and power produced from the PD in comparison with FBR circuits. The ripples in rectified voltage waveform were also lower, in comparison with the conventional rectifier circuit. However, the output voltage was low, which was insufficient for powering any electronic devices.

A dual-stage rectifier circuit was proposed by [20], where a controller varied the switching frequency (fs) of the step-down converter circuit to maximise the output power flowing into the battery. However, due to its switching frequency, the switching losses were higher than the output power. Another possible way of converting low voltage into regulated DC is by using a dual-stage converter [21]. This circuit achieved maximum power flowing into the storage by controlling the ripples of the output. However, the proposed dual-stage circuit was very complex and costly.

Another approach, namely an energy-harvester circuit with a clock booster for PEH, was proposed by [22] to minimise the voltage drop in the rectification process. The proposed circuit, also known as the second stage converter, included a clock booster to maximise the pulses’ amplitude and turn the buck-boost converter quickly. It was constructed in CMOS and tested through simulation. The output voltage was nearly 0.8 V_dc at a frequency of 100 kHz with an input voltage of 1.6 V_ac. Despite the use of additional components in the circuit, the rectified voltage was limited and unstable. Synchronous rectification is another well-known power extraction method for PEH. One of its main advantages is that the power generated by PD is independent of the connected load. However, recent literature [10,23,24,25] mainly focused on synchronous power rectification using the non-linear technique. Active rectification is not possible because the PD delivers low output power in most cases.

To address the abovementioned shortcomings (i.e., voltage drop, low voltage and ripple voltage) of the FBR circuit (i.e., linear circuit), a non-linear approach is proposed in this study.

This paper mainly focuses on the improvement of active rectifiers; however, the proposed circuit does not involve auxiliary interfaces. The main novelty of the proposed circuit and similar circuits (i.e., similar to INLSC) [22,26,27,28,29,30], is that the proposed circuit also efficiently works with the duty cycle of 50%, input voltage of 0.44 V_i, and achieves maximum output power, which is not possible by the abovementioned literature circuits in comparison with INLSC circuit. In addition, the proposed INLSC circuit requires only one PD, whereas other literature circuits adopted a few PD’s, which results in additional costs. Besides, the applicability of similar circuits is not shown in the literature. Therefore, as a primary rule, an active and non-linear rectifier circuit is desired to achieve a high rectified voltage (HRV) and high output power (HOP) with only 50% of the duty cycle. However, the balance between HRV and HOP has not been adequately addressed in the literature. Therefore, this study proposes a non-linear circuit, aiming to achieve optimal rectified voltage and high output power with active rectification. To verify the applicability, INLSC was also tested briefly with a 7-segment display.

The motivation of this proposed study is to utilise the benefits of the conventional boost converter [31], buck-boost converter [32], and synchronous rectifier circuits [23,33,34]. As a result, the proposed circuit is expected to reduce the voltage drop in the rectification process, boost the input voltage, and minimise the ripples in the output voltage waveform. The proposed circuit, namely an improved rectifier-less switching circuit, INLSC, consists of both boost and buck-boost operations controlled by a switching process using bidirectional switches. This circuit employs a polarity detector and an inductor that enables low voltage operation with less complexity. Besides, it uses only one capacitor to reduce complexity and cost.

To validate the performance of the proposed INLSC, a series of experimental tests and numerical simulations were carried out in this study. A real-life application, which is not attempted in the literature, is also presented in the proposed study.

2. Power Extracting Circuits for PEH

This section asserts the basics of the PEH system, including internal circuit modelling of PD and commonly used conventional circuits in the rectification process. Subsequently, the proposed INLSC is outlined.

2.1. Optimal Power Flow of PD

A vibrating PD is modelled as an AC current source, i_i (t) or a voltage source, V_i (t) in parallel or in series with its internal capacitance, C_P, respectively, to ascertain its power flow characteristics depicted within the context of Figure 2. The generated voltage or current fluctuates with the mechanical vibrations; however, it is assumed to be constant regardless of external loading [9].

2.2. Conventional FBR Circuit

The simplest rectifier circuit to convert AC to DC is the FBR circuit. The operation of the FBR circuit and its corresponding output waveforms are outlined in Figure 3.

From Figure 3, it can be observed that the current produced by PD needs to first charge its internal capacitor, C_P. During this period, the PD voltage is less than the sum of rectified voltage and forward voltage (i.e., PD voltage ≤ V_dc + 2 V_d), where V_d is the voltage drop across diodes. Thus, the FBR is blocked, and the load capacitor, C_L does not charge. Such process occurs in both positive and negative half cycles. Intervals 1 and 3 are known as non-harvesting periods (i.e., PD is charging its internal capacitor). When the magnitude of the PD voltage matches the rectified voltage (i.e., PD voltage ≥ V_dc + 2 V_d), the FBR is in conduction state. The load capacitor is now charged. Intervals 2 and 4 are known as harvesting periods [4,19,35].

The PD voltage (V_i) and the DC voltage (V_dc) rectified by FBR circuit are illustrated in Figure 4a,b, respectively. From Figure 4b, it can be noticed that, in the positive half cycle, the PD voltage charges the load capacitor from V₂ to V_m. Then, at t = π/2, the load capacitor discharges through the load resistor R_L, and the ripple voltage is depicted in Figure 4c. Besides, the currents through the load capacitor, C_L and resistor, R_L, denoted as i_CL and i_RL, respectively, are shown in Figure 4d,e.

The description of a negative half cycle is herein omitted, as it is similar to the positive half cycle. It can be seen from Figure 4 that the maximum voltage drop occurs between V_m to V₂ (i.e., V_m − V₂). From Figure 2 and Figure 4, the PD voltage applied to the proposed circuit can be expressed as follows [36]:

$${\mathrm{V}}_{\mathrm{i}} \left(\mathrm{t}\right)= {\mathrm{V}}_{\mathrm{m}} \sin \left(\frac{2 \mathsf{\pi } \mathrm{t}}{{\mathrm{T}}_{\mathrm{in}}}\right)$$

(1)

where T_in is the period of vibration of PD and V_m is the magnitude of the AC.

Referring to Figure 4c, considering one cycle of charging and discharging time of FBR as T_s, and the charging time as ∆t, the discharging time period can be written as:

T_s − ∆t

(2)

Considering the load capacitor, C_L is charged and discharged through load resistor, R_L, the voltage of the capacitor can be expressed as:

$${\mathrm{V}}_{\mathrm{dc}} \left(\mathrm{t}\right)={ {\mathrm{V}}_{\mathrm{dc}} \mathrm{e}}^{\left(\frac{-\mathrm{t}}{{\mathrm{R}}_{\mathrm{L}}{\mathrm{C}}_{\mathrm{L}}}\right)}$$

(3)

The maximum value of the ripple voltage, V_P1 and the minimum value of the peak ripple voltage, V_P2, can then be derived:

V_P1 = V_m

(4)

$${\mathrm{V}}_{\mathrm{P}1}= {\mathrm{V}}_{\mathrm{dc}} ={ {\mathrm{V}}_{\mathrm{m}} \mathrm{e}}^{\left[\frac{-\left({\mathrm{T}}_{\mathrm{S} -}\Delta \mathrm{t}\right)}{{\mathrm{R}}_{\mathrm{L}}{\mathrm{C}}_{\mathrm{L}}}\right]}$$

(5)

Assuming that ∆t $\ll$ T_s:

$${\mathrm{V}}_{\mathrm{P}1}= {\mathrm{V}}_{\mathrm{dc}} ={ {\mathrm{V}}_{\mathrm{m}} \mathrm{e}}^{\left[\frac{-\left({\mathrm{T}}_{\mathrm{S}}\right)}{{\mathrm{R}}_{\mathrm{L}}{\mathrm{C}}_{\mathrm{L}}}\right]}$$

(6)

1st assumption:

$${\mathrm{V}}_{\mathrm{m}}\left[1+\left(1+{( \frac{-{ \mathrm{T}}_{\mathrm{S}}}{{\mathrm{R}}_{\mathrm{L}}{\mathrm{C}}_{\mathrm{L}}})}^1. \frac{1}{1!}+(\frac{-{ \mathrm{T}}_{\mathrm{S}}}{{\mathrm{R}}_{\mathrm{L}}{\mathrm{C}}_{\mathrm{L}}}{)}^2. \frac{1}{2!} +(\frac{-{ \mathrm{T}}_{\mathrm{S}}}{{\mathrm{R}}_{\mathrm{L}}{\mathrm{C}}_{\mathrm{L}}}{)}^3. \frac{1}{3!} \right)\right]$$

(7)

Assuming that T_s $\ll$ R_L C_L:

$${\mathrm{V}}_{\mathrm{P}2}= {\mathrm{V}}_{\mathrm{m}} \left[1-\left(\frac{{\mathrm{T}}_{\mathrm{S}}}{{\mathrm{R}}_{\mathrm{L}}{\mathrm{C}}_{\mathrm{L}}}\right)\right]$$

(8)

In addition, the ripple voltage (Figure 4c) can be written as:

V_ripple = (max peak − min peak)

(9)

= (V_{P1 −} V_P2)

(10)

Substituting Equations (6) and (8) into Equation (10), the ripple voltage of the FBR circuit can be written as:

$${\mathrm{V}}_{\mathrm{ripple}} = {\mathrm{V}}_{\mathrm{m}} \left[ \frac{{\mathrm{T}}_{\mathrm{s}}}{{\mathrm{R}}_{\mathrm{L}}{\mathrm{C}}_{\mathrm{L}}} \right]$$

(11)

$${\mathrm{Considering} \mathrm{T}}_{\mathrm{S}}=\frac{1}{{\mathrm{f}}_{\mathrm{s}} {\left(\mathrm{frequency}\right)}^{\prime }}$$

(12)

$${\mathrm{V}}_{\mathrm{ripple}} = {\mathrm{V}}_{\mathrm{m}} \frac{1}{2{ \mathrm{f}}_{\mathrm{s}}{\mathrm{R}}_{\mathrm{L}}{\mathrm{C}}_{\mathrm{L}}}$$

(13)

From Figure 4, it can be observed that the rectified voltage differs from the expected DC voltage. This issue (i.e., ripple voltage) is also taken into consideration in this study. A switching control circuit that includes boost and buck-boost modes is proposed to overcome these issues, namely forward voltage, boosting voltage, and ripple reduction.

2.3. Proposed Circuit’s Benifits

For ease of switching operation, bidirectional switches are used, which consist of four N-MOSFETs. These switches work in both positive and negative half cycles simultaneously. In addition, one inductor and one capacitor are included in the circuit. The main benefits of the proposed switching circuit are:

• Low input voltage for activation;
• Smaller size and lower cost;
• Able to boost low voltage into high voltage;
• Able to reduce ripples in the output waveform;
• It utilises the internal body diode of the transistors to reduce the forward voltage, which reduces the cost.

Further explanation of the circuit is delineated in the following sections.

3. Operation Principle

The proposed INLSC and its operation are depicted in Figure 5. An input AC voltage of 0.44 V_i at a frequency of 100 Hz is utilised to rectify the output of the PD. In order to convert AC into DC, the switches must be able to conduct and to block the currents in both cycles during ON and OFF conditions.

Therefore, four MOSFET (bidirectional) switches were adopted and connected. Note that, in both positive and negative half cycles, switches M3 and M4 were only in ON state, while M1 and M2 are in OFF state, which prevents the circuit from reverse recovery loss. In other words, the voltage stored in the load capacitor could not flow back to the PD, and this process is known as return phenomenon, which is a significant research gap in the SSHI method [33,37]. Therefore, these M1, M2 switches are always in OFF state.

In this study, a polarity detector is employed to detect the polarities of PD. Therefore, the switches M3 and M4 are always synchronised with the PD voltage. When the polarity detector detected the polarity, the resultant signal was sent to the logic AND gates, A1 and A2. Besides, the gates were also powered by PWM (pulse with modulation) of the controller [2].

Thus, the output signal of the polarity detector and the pulse signal was compared. The resultant signals from both AND gates (A1 and A2) are sent to switch M3 and M4, respectively. The switch, M3 conducts in positive half cycle, while the switch, M4 works in negative half cycle. In the positive half-cycle of the PD voltage, it operates as a boost converter while in the negative half cycle, it works as a buck-boost converter. This type of discontinuous mode (DCM) circuit has the advantage of limiting the switching losses. Besides, it reduces the reverse recovery loss of the diode.

In this operation, the proposed circuit possesses four main operating modes in each half cycle. Modes 1–4 and Modes 5–8, corresponding to the positive half cycle and the negative half cycle, respectively. Each mode is described below:

Mode 1: In the beginning, the PD charges its internal capacitor, C_P while the proposed INLSC is in OFF state.

Mode 2: During t₀, the switch, M3 is in ON state, and the PD voltage feeds the inductor, L1. The current flow path in this mode is PD–L1–M3–D4–PD. Thus, the inductor is energised. However, since the inductor does not allow a sudden change in current, the current linearly increases from zero to its peak value. At this instant, the load capacitor powered the load resistor, R_L.

Mode 3: During this time, the switch, M3 is in OFF state. The energised inductor in Mode 2, freewheels via D1, which is an internal body of M1. As stated above, the inductor does not discharge instantly as well; it discharges linearly and charges the load capacitor, C_L. However, the capacitor also energises linearly since it does not allow a sudden change in voltage. Therefore, it charges from zero to its peak value.

Mode 4: When the inductor current reaches zero through the internal body diode, D1 of M1, the internal body diode turned OFF automatically. This mode effectively eliminates the reverse recovery loss of the diode since in practice, a diode is not physically presence. Besides, switch M1 is in OFF state.

Mode 5: Modes 4–8 occur in the negative half cycle of PD. This mode is similar to Mode 1, but it works in the negative half cycle of the PD and charges its internal capacitor.

Mode 6: During this time, the switch, M4 is in ON state, while the other switches are in OFF state and the PD feeds the inductor, L1. The current flow path in this mode is PD–M4–D3–L1–PD. Thus, the inductor is energised from zero to its peak value. At this instant, the load capacitor powered the load resistor, R_L.

Mode 7: During this time, the switch, M4 is in OFF state. The energised inductor in Mode 6, freewheels via D2, which is an internal body of M2. As stated above, the inductor discharges and charges the load capacitor linearly. Therefore, the load capacitor charges from zero to its peak value.

Mode 8: When the inductor current discharges to zero, the internal body diode, D2 of M1 is turned OFF automatically. This mode eliminates the reverse recovery loss of the diode since there is no presence of a diode in practice. Besides, the switch M2 is in OFF state.

Considering the operating modes, both M1 and M2 are in OFF state in both positive and negative half cycles while the other two switches, M3 and M4, are in ON and OFF states simultaneously.

4. Theoretical Analysis and Design

To increase the extracted output power from PD and reduce the ripples in the output waveform, two key aspects were considered in the design of the circuit, namely the impedance matching and the switching process. It is worth noticing that the impedance of the proposed converter circuit can be varied by adjusting the duty cycle. Considering the primary focus of this study is on the basic topology of circuit and its verification, sinusoidal AC voltage was taken as input voltage to simplify the process of analysis. The proposed circuit enjoyed the benefits of lower cost and complexity, as only one inductor and one capacitor were used. Unlike most previously proposed circuits, no diode was used to transfer the energy from inductor to load capacitor. For the purpose of analysis, a few assumptions were made for the switching process:

• The output load capacitor must be large enough to keep the rectified voltage stable.
• The switching frequency, f_s should be higher than the external vibration frequency applied to the PD to minimise the ripples. Besides, due to high f_s, the vibration frequency of PD is assumed constant across each switching period [31,36]. Subsequently, the PD voltage can also be considered as a constant voltage source, as expressed in Equation (1).
• For ease of calculations, internal properties of passive components in the circuit are not taken into consideration.

In addition, the power semiconductor components used in the proposed circuit turns ON with the zero current switching (ZCS) method. Due to this reason, most of the switching losses could be eliminated. The switching signals applied to the switches, namely M3 and M4, are shown in Figure 6. The proposed circuit integrated the boost and buck-boost operations in the positive and negative half cycles, respectively by applying the abovementioned switching signals to M3 and M4. The operation loops of the circuit in the positive half cycle are outlined below and plotted in Figure 7. where D1 and D2 are the duty cycle of ON and OFF periods, respectively, and T_sw is the switching frequency of the duty cycle. V_L1 is the voltage across the inductor.

Loop 1: Loop 1 occurs in Mode 2. During this time, the PD voltage charges the inductor, L1 and the circuit is shorted. Therefore, the voltage across the inductor, V_L1 is equal to the PD voltage, V_i, and it can be expressed as:

V_L1 = V_i

(14)

At this instant, the load capacitor is powering the load resistor. Thus, the voltages across the load capacitor and resistor are the same, and the current flow through C_L can be expressed as:

$${\mathrm{i}}_{{\mathrm{C}}_{\mathrm{L}}}=\frac{-{\mathrm{V}}_{\mathrm{dc}}}{{\mathrm{R}}_{\mathrm{L}}}$$

(15)

Loop 2: Loop 2 takes place in Mode 3. At this time, the load capacitor is powered by the peak inductor current, i_pk, which was initially charged in Mode 2. The voltage across the inductor can be expressed as:

$${\mathrm{V}}_{\mathrm{L}1}={ \mathrm{V}}_{\mathrm{i}}-{\mathrm{V}}_{\mathrm{dc}}$$

(16)

Furthermore, the current through C_L is expressed as:

$${\mathrm{i}}_{{\mathrm{C}}_{\mathrm{L}}}={ \mathrm{i}}_{\mathrm{L}1}-{ \mathrm{V}}_{\mathrm{dc}}/{\mathrm{R}}_{\mathrm{L}}$$

(17)

Loop 3: Loop 3 occurs in Mode 4. When all the switches are in OFF condition, no PD voltage and current are flowing through the circuit. At this time, the PD voltage and current across the inductor can be expressed as:

V_L1 = 0, i_i (t)

(18)

Furthermore, the current through the load capacitor can be written as:

$${\mathrm{i}}_{{\mathrm{C}}_{\mathrm{L}}}=\frac{-{\mathrm{V}}_{\mathrm{dc}}}{{\mathrm{R}}_{\mathrm{L}}}$$

(19)

The output waveforms of the proposed INLSC in switching process, when the switches are in ON, OFF state, are shown in Figure 8. The inductor slope during the time interval from t₀ to t₁ can be expressed as:

$$\frac{{\mathrm{di}}_{\mathrm{L}1} \left(\mathrm{t}\right)}{\mathrm{dt}}=\frac{{\mathrm{V}}_{\mathrm{L}1} \left(\mathrm{t}\right)}{\mathrm{L}1}=\frac{{\mathrm{V}}_{\mathrm{i}}}{\mathrm{L}1}$$

(20)

Similarly, the current slope of inductor, L1 can be written as:

$$\frac{{\mathrm{di}}_{\mathrm{L}1} \left(\mathrm{t}\right)}{\mathrm{dt}}=\frac{{\mathrm{V}}_{\mathrm{L}1} \left(\mathrm{t}\right)}{\mathrm{L}1}=\frac{{\mathrm{V}}_{\mathrm{i}}}{\mathrm{L}1}$$

(21)

From Equations (20) and (21), the peak ripple current of inductor, ∆i_L1 is solved:

$$\Delta {\mathrm{i}}_{\mathrm{L}1}=\frac{{\mathrm{V}}_{\mathrm{i}}}{2\mathrm{L}1}{ \mathrm{DT}}_{\mathrm{sw}}$$

(22)

Similarly, slope of the load capacitor in time intervals of t₀ to t₁, and t₁ to t₂ are shown in Figure 8. Note that the energy stored in an inductor by the PD and voltage stored in the load capacitor by the inductor must be the same. From the capacitor slope equations, the ripple voltage can be written as follows:

$$\Delta {\mathrm{V}}_{\mathrm{dc}}=\frac{{\mathrm{V}}_{\mathrm{i}}}{2{\mathrm{C}}_{\mathrm{L}}{\mathrm{R}}_{\mathrm{L}}}{ \mathrm{DT}}_{\mathrm{sw}}$$

(23)

However, to verify the performance of the electronic circuit, it is necessary to calculate the voltage gain and power. Therefore, in this study, the peak value of input current is only calculated in the boost mode. A similar trend was observed in other modes, and it can be represented as follows [36]:

i_Pk (t) = D1 T_sw V_i/L1

(24)

As per inductor volts-second balance, net volt-seconds added to inductor during one switching period is:

V_i D1T_sw = (V_dc/2 − V_i) D2T_sw

(25)

$$\mathrm{D}2\mathrm{Tsw} =\frac{{\mathrm{V}}_{\mathrm{i}} \mathrm{D}1 \mathrm{Tsw}}{\left(\frac{{\mathrm{V}}_{\mathrm{dc}}}{2}-{ \mathrm{V}}_{\mathrm{i} }\right) }$$

(26)

From the above, in each switching time, the average input power, P_in can be derived:

P_in = V_i i_Pk (D1 + D2)/2

(27)

The boost ratio was designed based on a specific application, and the power output from the circuit was based on R_L, which was connected in parallel to the proposed circuit. To meet the requirement of the application, the inductor, the duty cycles, and the switching frequency must be designed accordingly. The larger is the switching frequency, the smaller is the inductance.

Therefore, to reduce the cost, complexity and weight of the proposed circuit, a higher frequency was chosen to reduce the ripples. The drawback of higher switching frequency is the inherent higher losses. The voltage ratings of the passive components in the proposed circuit were chosen higher than the rectified/output voltage for safe operation. One significant advantage of the proposed circuit is the sole use of internal body diodes of the MOSFETs, which are always in turn OFF state to transfer the stored energy in the inductor, while the other circuits in the literature [38,39,40,41] were using separate diodes. As a result, the forward voltage drop, rectification losses, cost, and complexity of the circuit can be reduced.

5. Simulation Results

Waveforms of the proposed circuit with the input voltage of 0.44 V_i at a frequency of 100 Hz (time period: 10 ms or 0.01 s), simulated using LTSPICE and the enveloped inductor current, and rectified voltage, is shown in Figure 9.

In the simulation, the PD source impedance was neglected to produce an ideal waveform for ease of verification of the proposed concept. In the experiment, the ideal source was replaced by the actual PD. To further understand the performance of simulation waveforms, namely the zoom-in view of a positive half cycle with the duty cycle of 0.50 and the resultant rectified voltage (in both half cycles) due to switching, is shown in Figure 10.

6. Experimental Results and Discussion

The experimental setup and the proposed circuit constructed on a breadboard are shown within the context of Figure 11. The performance of the circuit was tested using one test setup. In this test, the power extracted from the PD through the proposed circuit was investigated by varying the input voltages at a fixed frequency.

Table 1. Parameters of various components used in the experiment.

Components	Parameters
MOSFETs (M1, M2, M3, M4)	0.3 Vth, 20 V
Inductors (L1–L4)	4.7, 10, 22, 47 µH
Load capacitors (CL: C1–3)	1, 10, 100 µF
Load resistors (RL)	100 kΩ, 200 kΩ, 300 kΩ, and 400 kΩ
Vibration frequency	100 Hz
Input voltage	0.44 Vi
Switching frequency	50 kHz
Duty cycle	0.50, 0.87

summarises various components and their parameters for the abovementioned testing scenario.

The experimental setup and flow chart of this study is shown in Figure 11. The piezoelectric cantilever beam was made up of an aluminium beam (dimensions: 205 × 20 × 1 mm), with one end fixed on the vibration shaker (APS—113), while the other end of the cantilever beam carried two permanent magnets. These permanent magnets were placed at the tip of the aluminium beam, acting as proof mass. A microfiber composite (MFC) patch (category: M2814-P2, 37 mm × 17 mm × 0.180 mm, C_P = 33.90 nF) was attached near the fixed end of the aluminium beam, where the highest strain occurred.

A function generator (Agilent 33210A) was used to deliver a sinusoidal signal to a power amplifier (2706, B & K Agilent), which then amplified the signal before activating the shaker. The shaker generated mechanical excitations according to the input vibration frequency and amplitude to excite the piezoelectric cantilever beam.

For this test, the vibration frequency was fixed at 100 Hz, and the amplitude of input voltage was adjusted to obtain the desired peak open-circuit (OC) voltages during the experiment. Then, the OC voltage was connected to the proposed circuit for conversion into DC. The converted DC voltage was stored in a capacitor, which behaved like a battery or source for low electric current at a fixed voltage level. The average current of the proposed circuit was calculated using a resistor that was connected in parallel with the proposed circuit. A voltmeter (FLUKE 117) and an oscilloscope (TBS 1052B) was used to measure the voltage across the capacitor.

In addition, the calculated current through the load was also verified using a current meter (CD 771). The experimental waveforms of the proposed circuit with the duty cycle of 0.87 are presented in Figure 12.

When the abovementioned switching signals (Figure 12) were applied to the proposed circuit, the applied gate voltage, energising inductor current, and energising inductor current, the rectified voltage over one switching period are shown in Figure 13 and Figure 14. Besides, the extracted rectified voltage and calculated output power over different resistances are shown in Figure 15.

As can be seen from Figure 15a, the rectified voltage through the proposed circuit increased with its load resistance at constant input voltage and inductance. It can also be noticed that the proposed circuit was extracting the highest rectified voltage with an inductance of L1 at a resistance of 400 KΩ. Ohm’s law can be used to explain the positive correlation between the rectified voltage and resistance. Besides, as stated above, the PD current charged the inductor in the form of a magnetic field. When the PD current began to flow into the inductor, an opposing magnetic force was generated. At this time, in the positive cycle, the switch S1 was turned ON and OFF. Therefore, when the switch was ON, the PD current in the inductor was shorted in the circuit, which resulted in a higher magnetic field across the inductor as changing the magnetic field caused the higher potential difference.

When the switch was in the OFF state, the stored magnetic field across the inductor discharged through the switch, M1, to charge the load capacitor. In other words, the enveloped inductor current (L1 = 4.7 µH) was synchronised with the PD at 100 Hz. As a result, it delivered maximum rectified voltage.

During this time, the voltage across and current through the load resistor was measured to calculate the extracted output power through the proposed circuit, as illustrated in Figure 15b. The resistors in Table 1 were connected sequentially as load. Note that only the case of inductance, L1 = 4.7 µH is presented with the three load capacitors. In Figure 15c,d, only the case of load capacitor, C1 = 1 µF with different inductances is presented, as other capacitances followed the same trend.

As identified in Figure 15, the increasing trend of rectified voltage was observed with other inductances as well. Despite using the inductance of L3 = 22 µH, the proposed circuit has delivered maximum rectified voltage and output power. Overall, the proposed circuit delivered a maximum output power of 469 µW with an input voltage of 0.44 V_i at 100 Hz.

Figure 16 illustrates the captured voltage waveform of the proposed circuit using the oscilloscope (input voltage = 0.5 V_i, inductance = 22 µH, frequency = 100 Hz). The rectified voltage waveform was compared with a recently published H-Bridge circuit [3]. It can be observed that the ripples in the voltage rectified by the proposed circuit were significantly less pronounced in comparison with the H-Bridge circuit. The main reason for the fewer ripples through the proposed circuit was the inclusion of the non-linear method and the switching process, while the H-Bridge includes only the linear method. The following observations were also made regarding ripples reduction:

• By neglecting the smaller ripples in the output voltage of the proposed circuit, the discharging time was much shorter than the H-Bridge circuit (Zoom-in view).
• The ripples in the H-Bridge circuit could also be controlled by applying the switching method proposed in this study.

Note that the proposed circuit was also tested with other input voltages, namely 0.55 V_i and 0.75 V_i, at various frequencies, namely 100, 110, 120, 130 Hz. However, only the case of input voltage of 0.44 V_i at a frequency of 100 Hz is presented, where the proposed circuit delivered prominent output in comparison with other scenarios, and the remaining testing scenario trends were similar.

Finally, the applicability of the proposed circuit was tested through powering a 7-segment display, as shown in Figure 17. For such purpose, the load resistor was replaced with a 7-segment display, which is commonly used in traffic applications. The segment display was manually connected on the breadboard, and it is noted that the proposed circuit could power the 7-segment display, which was not shown in the existing similar designs and literature.

Lastly, the performance of the proposed circuit was compared with some previously proposed similar circuits, and the outcome is tabulated in

Table 2. Comparison of the output of numerous circuits available in the literature.

Methods	No of PD’s	Input Voltage (Vi)	Output Voltage (Vdc)	Output Power (µW)	External Power Supply
[36]	1	0.4	3.3	-	Yes
[40]	1	2.5	5.5	300	No
[42]	1	0.65	1.8	75	Yes
[43]	1	10	20	310	Yes
[26] (Similar design)	3	3.5	-	254	Yes
[22] (Similar design)	1	4.9	-	136	No
[44]	1	-	10	-	Yes
[45]	1	0.5	-	43.35	Yes
[46]	1	1.6	5.5	200	Yes
Proposed INLSC	1	0.44	6.5	469.1	Yes

. The proposed circuit outperformed all previously proposed circuits/methods in terms of rectified voltage and output power.

7. Conclusions

An INLSC capable of extracting higher power from low voltages and reducing the ripple in rectified voltage waveform was proposed and investigated in this study. The proposed INLSC could rectify and boost the low magnitude AC voltage generated by the PD used in PEH systems. The proposed converter combines the process of synchronous rectifier boost, buck-boost, and dual-stage circuits into an improved rectifier-less switching circuit. An additional advantage of the proposed circuit is that it does not require programming or external tuning, as it can self-adjust while the PD harvests energy from ambient vibrations. The operation and performance of the proposed circuit were verified through simulation and experiment. The proposed circuit converted 0.44 V_i to 6.5 V_dc and extracted a maximum output power of 469 µW, which is superior to similar circuits in the literature. The ripples in the rectified voltage were reduced. The circuit was found to be superior to the existing circuits/methods. In addition, the proposed circuit was capable of powering a 7 segment display.