NPC Seven-Level Single-Phase Inverter with DC-Link Voltage Balancing, Input Voltage Boosting, and AC Power Decoupling

Abstract

This paper presents a novel concept of the DC-AC system with the input voltage boost ability, seven-level output voltage modulation, and the input AC current reduction at the double frequency of the output voltage. The system integrates the NPC full-bridge inverter which is composed of four-level legs and an active input voltage balancer (AIVB). The DC-link is composed of three capacitors connected in a series. The source of the energy is connected directly to the middle capacitor while the upper and lower capacitors of the DC-link are charged by the AIVB. The operation of the AIVB leads to balancing of the DC-link voltage and a three-fold boosting of the input voltage. The AIVB utilizes a novel switched-capacitor (SC) topology and can be designed as a low-volume quasi-magneticless converter with a simple open-loop control. One of the proposed methods of the control of the AIVB allows for a double frequency reduction in the input current. The application of the AIVB allows for the use of a seven-level NPC full-bridge (FB) inverter with a simple classic carrier-based PWM which is not applicable in the typical DC-link configurations. This paper presents the converter’s concept, its operation, control methods, and the results of simulations and experiments.

1. Introduction

Neutral-point-clamped (NPC) inverters are an established solution in high power systems [1,2,3]. However, a number of applications of this multilevel inverter (MLI) concept can still be expanded. The majority of concepts with NPC inverters are limited to three-level topologies. However, single-phase NPC-based inverters are also indicated as a favorable solution in low power, transformerless photovoltaic systems [3,4,5,6,7]. Furthermore, increasing the number of levels to four brings the important benefit of an improved output voltage quality, a decrease of the voltage stress on the switches, and a decrease of an AC filter volume. The design of a multilevel converter may also allow the achievement of an efficient thermal management, which can lead to a design where heat-sinks and fans are not required. An industrial trend for the replacement of conventional topologies by the multilevel converters is addressed in [8], which analyzes the single-phase bridge multilevel inverter. The single-phase NPC multilevel inverter with more than three levels is not applicable with typical PWM due to the DC-link voltage imbalance. This paper demonstrates how an adequate balancing circuit can utilize a four-level NPC bridge with the PD-PWM method. The research problems addressed in this paper include a partial power conversion, a DC-link voltage balance, a DC-link voltage boosting, and an AC power decoupling. All these issues are important when considering the prospective application of the NPC multilevel inverter in single-phase photovoltaic system. The overall topology of the converter and methods of switching are the concepts which are novel in this paper.

Four-level and five-level NPC converters are analyzed in [9,10,11,12,13]. The research demonstrates that the DC-link voltage balancing can be a major problem in such converters. To maintain the DC-link voltages sharing, various types of balancing circuits are proposed in [9,10,11,12,13]. The balancing circuit presented in [9] reinforces the natural balancing mechanism in the NPC-bridge composed of four-level legs. In [10], the balancing circuits based on switch mode converters are presented, and in [11,12], flying-capacitor circuits are proposed for the DC-link voltage balancing. SC-based balancing circuits are one of the proposed solutions for the NPC MLIs in [12,13,14,15,16,17]. Meanwhile, refs. [15,16,17] present a circuit where a switched capacitor can transfer energy between three capacitors of the DC-link. In [15], this concept is also extended to five series connected capacitors. A similar problem appears in the series connected battery banks, where the SC converters are analyzed as equalizers [18,19]. After the optimization, the circuit proposed in [15] can be used with a four-level single-phase NPC inverter to boost the total input, perform the voltage balancing and power decoupling, which is presented in this paper. In such a system, the front-end circuit can be controlled to charge the upper and lower capacitor from the middle capacitor of three series connected devices.

Another benefit of the proposed converter configuration is its operation with partial power conversion. When the PD-PWM is used, a considerable part of energy is converted by the inverter to the AC side directly from the energy source. The AIVB front-end converter charges the upper and lower DC-link capacitor in a DC-DC manner, but it only converts approximately 50% of the energy. A classic PD-PWM modulation applied in an NPC bridge (composed of four level branches and three series connected DC-link capacitors) causes the middle capacitor in the DC-link to be overloaded. For the concept of the topology and control, presented in this paper (Figure 1), such a phenomenon is found to be especially favorable as the input DC voltage source is connected to the middle capacitor of the DC-link. Other DC-link capacitors are charged by the AIVB. This method of operation makes the total DC-link voltage three-times higher than the voltage of the source. This is an advantage since inverters with the input voltage boosting are suitable for some applications such as low power photovoltaic systems.

The issue of partial conversion and the total DC voltage boosting is analyzed in the class of cascaded inverters [20,21,22]. In [20], a concept of partial power conversion to input capacitors of an asymmetrical CHB inverter is presented. Five DC-link capacitors are supplied by a multi-winding transformer to auxiliary bridges at a high frequency, but the majority of energy is converted to the load by the main, non-isolated bridge. In the topologies in [21], the utilization of a multi-winding transformer and, in many cases, additional DC-DC converters are also presented. Ref. [22] presents a seven-level cascaded inverter with a single DC source and a switched-capacitor auxiliary circuit. The auxiliary circuits charge the input capacitors of two bridges whilst one of the bridges is connected to the input source directly. In comparison to this idea [22], we propose the application of a novel SC circuit in an NPC inverter with a DC-link composed of three capacitors. Furthermore, the operation of the SC circuit proposed in this paper is improved when compared to the solution presented in [22]. The circuit and the method presented here allows for the recharging of the switched capacitor in a resonant circuit. This allows for inrush currents and the risk of converter failure, as well as electromagnetic noise generation to be avoided.

AC-power decoupling from the DC-link voltage is one of the most important problems of single-phase systems. The issue of AC power decoupling can be overcome by energy of the AC voltage frequency storing in passive components, the use of additional converters, or by two stage conversion. Various methods for the power decoupling at a low frequency are presented in [23,24,25,26,27]. Utilization of the DC-link capacitors for the power decoupling are presented in [26,27]. In [26], the DC-link is supported by the switched-capacitor converter, and in [27], the NPC T-type inverter with two DC-link capacitors and controlled DC-link voltage imbalance is proposed.

In the NPC inverter proposed in this paper, the power decoupling is achieved by storing energy in the two DC-link capacitors by an adequate control of the AIVB. Power of the DC-link middle capacitor, connected to the source, has reduced the double frequency component since other DC-link capacitors store the energy. This solution allows for a cost optimization of the inverter as it does not require any additional components.

The research contribution covers the concept of the system (Figure 1) and its control, which allows for a seven-level output voltage modulation with the use of the NPC topology, DC voltage boosting, partial energy conversion, DC-link voltage balancing, and double frequency reduction in the source’s voltage. It is achieved with the use of a novel front-end converter which matches to the NPC inverter with three DC-link capacitors. The paper demonstrates relevant results related to features of the converter and their feasibility which is an important contribution to the research. In the proposed system the PWM pattern for NPC inverter is significantly simplified in comparison to [9] as it uses the classic PD-PWM. Furthermore, in comparison to the established boost-inverter concept the proposed system does not require the input boost converter, nor special control of an inverter. The proposed converter features are also compared to seven-level single phase inverters based on switched capacitor circuits which are rapidly developed recent years [28,29,30,31,32].

The paper is organized as follows: Section 2 presents the concept of the operation of the system with an explanation of the inverter’s modulation and the AIVB topology and switching stages. Section 3 discusses the operation and control strategies with a demonstration of cases via the simulation results. Section 4 presents the experimental verification of the proposed concepts.

2. Concept of Operation of the System

2.1. Modulation of the Inverter

The proposed system can utilize simple switching strategy based on the classic PD-PWM method (Figure 2). From the model of operation presented in Figure 2 it is seen that the discharge rate of the C₂ capacitor is much larger than in the case of capacitors C₁ and C₃. This indicates that the PD-PWM may not be applicable for the NPC inverter with four-level legs (as in the analyzed case) because it leads to an unequal discharging of the DC-link capacitors. However, it is an advantage in the proposed system, since the C₂ capacitor takes energy directly from a source. The other capacitors are supplied by the AIVB which also assures boosting of the input voltage and DC-link voltages balancing.

The AIVB (Figure 1 and Figure 3) charges the upper and lower DC-link capacitor (C₁ and C₃) from the source (connected to C₂) with unity voltage gain. In ideal conditions, it leads to the state where u_C1 = u_C2 = u_C3 = u_in. The AIVB is based on SC resonant circuits with low volume resonant chokes (L₁ and L₂ = 3 uH in the demonstrated design). The resonant chokes limit the inrush current in the SC circuits and allows for oscillatory currents in ZCS (zero current switching) mode (Figure 3). More details related to selection of passive components are included in Section 2.2.2. The AIVB contains five switches which is significantly optimized in relation to the voltage balance circuits presented in [15,16].

The basic control principle of the AIVB assumes the use of switching states which charge the switched capacitor from the source and discharge to one of the DC-link capacitors C₁ and C₃ (Figure 3). It is conducted in the following order with the frequency f_sw:

SwitchingOrder = {St1, St2, St1, St3, St1…},

(1)

The switching frequency of the AIVB (f_sw) is aligned to the oscillation frequency of the resonant circuits:

$$f_{01}=\frac{1}{2\pi \sqrt{\left(L_1+L_2\right)C_s}} (\mathrm{in} St1 \mathrm{state}), f_{02}=\frac{1}{2\pi \sqrt{L_n{C}_s}} (\mathrm{in} St2, St3),$$

(2)

The use of switching order (1) causes charging the C₁ and C₃ capacitors from the source (connected with the C₂) when u_C1 < u_C2 and u_C3 < u_C2. It is performed in open loop control system.

To limit source current ripples, the source is separated by a filter Z_f (Figure 1).

2.2. Realization of AIVB Control Concept

The control principle of the AIVB assumes operation in an open loop and the generation of switching states in an appropriate order (1). In the demonstrated case, the sequence of states (1) is achieved based on a state machine decoder. The period of each state is maintained by a counter which allows for a constant or variable switching frequency of the AIVB. The ratio of the time duration of the state St1 to states St2 and St3 is 58:42 in order to handle the difference in oscillation frequencies (2). Each of the states (St1, St2, and St3) have assigned transistors to be turned on. In case of operation with a variable switching frequency of the AIVB, the reference frequency is synchronized with the instantaneous output power (Figure 4). The described control method has been implemented in Matlab/Simulink for simulation and Cyclone III FPGA, DE0 development kit in experimental setup.

2.2.1. Reduction of the AC Component in the Source Voltage at the Double Frequency of the Output Voltage

The AIVB can reduce the AC double frequency component of the input current by controlling the amount of the energy transfer to C₁ and C₃. The function which determines the power of the AIVB should have an inverse character to the power on the output of the inverter (p_out). When p_out approaches its maximum, the charging rate of the C₁ and C₃ is the lowest. Therefore, the double frequency component is decreased in the source current and increases in C₁ and C₃ voltages where the instantaneous energy is stored. A concept of the AIVB power control will be presented in the sections with the simulation and experimental results (Section 3 and Section 4) in more details.

The AIVB operates with maximum power when the switched capacitor is fully recharged in each cycle. Its maximum voltage is 2U_in and the power is also a function of the switching frequency and the capacitance:

P_AIVBmax = 0.5C_s(2U_in)²f_sw,

(3)

From the relationship (3), it is seen that a variation of the switching frequency (f_sw), in the range below the rated frequency, allows to control the AIVB’s power. With adequate synchronization of the output’s instantaneous power, this allows for a reduction in the double grid frequency from the source’s current. Figure 4 presents the concept of the closed control system for the power synchronization and double frequency reduction.

2.2.2. Selection of Components

The parameters of the switched capacitor circuits (C_s and also L_s) are dependent on the required power of the AIVB and the assumed switching frequency (which affects switching losses). The balancer can take the energy from the source with P = P_max whilst C₁ and C₃ capacitors can be charged with the maximum power P_1,3 = 0.5 P_AIVBmax. From the principle of operation of the inverter the C₁ and C₃ DC-link capacitors transfers only part of the energy available on the AC side (on the basis of Figure 5):

P_{(C1 and C3)max} = (0.63·m_a − 3.2)P_invmax,

(4)

where: m_a is the modulation index of the inverter.

Considering the target control of the system, the C₁ and C₃ capacitor will store nearly the entire AC energy which allows for very low ripples in the DC source’s current (adequate results will be presented in the Section 3 and Section 4). For the average output power P_out = 1000 W, the AC energy in a half period is obtained as an integral of the AC output power:

p_outAC = 1000 sin(618 t) ⇒ W_AC = 1000∙(1/618)∙2 = 3.24 J,

(5)

To store half of the total AC energy, the C₁ or C₃ capacitor should have the following capacitance:

C₁ = 2∙(W_AC/2)/(U_C1max²−U_C1min²),

(6)

For the demonstration purpose, the following range of DC-link capacitor C₁ and C₃ voltage is assumed: U_C1max = 133 V and U_C1min = 100 V. In such a case, the relationship (6) allows to calculate the capacitance C₁ = C₃ = 421 μF. In further tests, the DC-link capacitances are 500 μF for simulations (

Table 1. Parameters for simulation of the proposed SC-AC system.

Parameter	Uin [V]	Uload [V]	Pload [kW]	UDC [V]	fsw [kHz]	C1,2,3 in DC Link [μF]	Cs [nF]	L1, L2 [uH]
Value	133	230	1	400	110	500	320	3

) and 470 μF for experiments (Section 4). Such values of capacitances allow to clearly demonstrate phenomenon of AC energy storage. To operate with lower voltage ripples, larger capacitance of C₁ and C₂ DC-link capacitor banks is required, according to the relationship (6).

Capacitance of the C₂ capacitor should be selected to meet the assumed requirements for the source’s current filter design.

To control the AC output power, the power of the balancer, expressed by the relationship (3), should comply with the condition:

P_AIVBmax ≥ 0.5P_{(C1 and C3)max},

(7)

Based on (3), for U_in = 133 V, f_sw = 110 kHz, and C_s = 320 = nF the AIVB’s maximum power is P_AIVBmax = 1245 W, which satisfies the requirements of the demonstrated design with not significant oversizing (for experiments C_s = 260 = nF, P_AIVBmax = 1011 W). To operate in ZCS, the AIVB utilizes low volume resonant chokes (L₁, L₂) which makes the switched capacitor current oscillatory. Selection of L₁ and L₂ inductance is determined by earlier selected parameters of the AIVB such as its rated power, switching frequency, and switched capacitance. The frequency of natural oscillation in the circuit composed of the C_s and resonant chokes (L₁, L₂) should be higher than the switching frequency. The chokes (L₁, L₂) of 3μH satisfy this requirement, giving f₀ = 115 kHz when the circuit contains two chokes as in Figure 3a, and f₀ = 162 kHz when the circuit contains one choke as in Figure 3b,c.

In the simpler case of control, the AIVB boosts the voltage of C₂ capacitor. Voltages on C₁ or C₃ reflect the u_C2 voltage and selection of their capacitance should assume high frequency ripples reduction.

3. Simulation Results

The results of the simulation presented in this section verify the concept of the inverter’s operation, the AIVB and the complete system. The research was conducted with the use of Matlab/Simulink software with the parameters presented in Table 1.

3.1. Power of DC-Link Capacitors in Seven-Level HB Inverter

To demonstrate the operation of the inverter and energy required for particular DC-link capacitors, the inverter with three input voltage sources were analyzed (Figure 5a). Figure 6 presents the waveforms of the operation of the inverter with three input voltage sources and PD PWM. The results shown in Figure 6 confirms that the load of the internal source, connected to C₂ capacitor, is the highest. For the lower modulation index of m_a = U_{ref_max}/U_{carrier_max}, the discharging rate of C₂ capacitor becomes significantly higher than the discharging rate of the C₁ (or C₃) capacitor. For m_a = 0.6, 67% of power comes from the C₂ capacitor and for m_a = 1, P_C2/P_out it is over 0.41 (Figure 5b). These results show that the use of the classic PD modulation is favorable when the source is connected to the middle DC-link capacitor (C₂). The energy required for the maintenance of voltage on the C₁ and C₃ capacitors is transferred by the AIVB. In the analyzed case of operation of the inverter (U_DC = 400 V, U_out = 230 V) the auxiliary circuit AIVB transfers approximately only 50% of power to the C₁ and C₃ capacitors.

3.2. The Converter with the AIVB Operating in the Continuous Mode with Fixed Frequency

The basic control method of the AIVB assumes the use of a repetitive sequence of states defined by the SwitchingOrder (1) series. According to (1) the AIVB is constantly switching without additional control. As the voltage on C₁ or C₃ capacitor is below the source voltage the capacitor is charged. Figure 7, Figure 8, Figure 9 and Figure 10 present simulation results of this case. These results demonstrate that the AIVB maintains the voltages on C₁ and C₃ DC-link capacitors. Figure 7 and Figure 9 show the instantaneous increase of power of the AIVB when the output voltage is modulated on higher levels.

The AIVB’s operation is presented in Figure 8 and Figure 10 with details (25 μs/div). It is a fragment of the waveforms when the load of the AIVB is the highest. Resonant charging and discharging of the DC-link capacitors with the use of a switched capacitor is clearly visible. In every switching period the C₂ capacitor is discharged and the C₁ or C₃ capacitor is charged. The frequency of pulses of the current in the C₂ capacitor is two times higher than in the C₁ and C₃ (Figure 8).

In the proposed test case, the switched capacitor is not fully discharged in the switching period (Figure 9 and Figure 10). Even at the maximum instantaneous output power the AIVB operates below its maximum available power (which was calculated in Section 2.2). Frequency voltage ripples of 100 Hz are seen on C₁ and C₂ capacitors due to voltage drops on parasitic resistances and diodes of the balancer. Assuming 100 mΩ total parasitic resistance of a circuit during the stage of the C_s discharging, the resistive voltage drop is 3.5 V at the maximum current 35A. Considering the resistive voltage drop which occurs during C_s charging as well as forward voltage on diodes, the total maximum voltage drop between the input port (C₂) and the output port (C₁ or C₃) of the balancer can be estimated at 9 V which corresponds with results presented in Figure 7 and Figure 11. The low frequency ripples in DC-link C₁ and C₃ capacitors can be minimized by reduction of stray resistance, R_ds(on) of transistors and voltage drops on diodes of the balancer.

3.3. Double Frequency Reduction in the Source Current by Control of the AIVB Power

As can be observed in Figure 7, the DC source current (i_source) has an AC component at double frequency of the output voltage. In order to reduce this component from the source’s current, a method for additional control of the AIVB’s operation was introduced. The concept is based on the switching frequency of the AIVB variations (f_sw = var) which affects the amount of energy transferred from the C₂ to C₁ and C₃ DC-link capacitors. The method of the reference generation for the switching frequency of the AIVB (f_{sw_ref}) is based on the concept presented in Figure 4. It is composed of sinusoidal signal with amplitude of 0.65 positive biased by 0.1, limited to maximum value of 1 and phase shifted by 2π/3 [rad] (Figure 12). Such a reference for the AIVB’s control has been developed by the simulation study where a sweep of bias and phase shift has been performed, seeking the best double frequency reduction.

At the peak input current of the DC source, the switching frequency of the AIVB reaches its minimum and the rate of energy transferred from the DC source to the C₁ and C₂ capacitors is minimal. Meanwhile, the inverter output power decreases and, thus, the current drawn from the DC source, C_1, and C₂ are charged with a higher energy ratio. Figure 13, Figure 14, Figure 15, Figure 16 and Figure 17 present simulation results in the case when the AIVB operates with variable frequency. The results presented in Figure 7 and Figure 13 show that when the AIVB operates with variable frequency the AC component of the input current is considerably decreased whilst the variation of voltage on the C₁ and C₃ DC-link capacitor increases.

These DC-link capacitors store the instantaneous energy, and the load of the DC source is more even. The load of the AIVB is better distributed in a time period of the inverter voltage when its power is controlled (comparison of Figure 9 and Figure 14). Figure 15 and Figure 16 present a shorter time span (500 µs/div) when the AIVB switching frequency (f_sw) varies from its minimum to maximum. As observed, the switched capacitor is fully discharged in every switching period thus it is utilized with the maximum power.

The overall energy transfer rate between the DC-link capacitor is controlled by the variation of the switching frequency. The method’s effectiveness for double frequency reduction in the input current is seen when comparing of the results achieved in the two analyzed cases of AIVB operation presented in Figure 17. When the source voltage is constant the significant reduction of double-frequency ripples from the source’s current confirms the effectiveness of the proposed active power decoupling method.

3.4. Switch Load by Currents of Converters and Conduction lLosses

To estimate conduction losses and the thermal design in the converter, the switches and diodes load should be evaluated. In the AIVB, the currents’ load of switches can be simply compared based on its operation principle. The use of the switching order (1) creates a slight inequality of conduction among the switches (

Table 2. Active switches (A) in subperiods of the AIVB’s operation.

State	D1	D2	Sib1	Sib2	Sib3	Sib4	Sib5
St1 (used 2 times) in a period	-	-	A	A	A	A	-
St2	A	-	-	A	A	-	A
St3	-	A	A	-	-	A	A
Number of active subperiods	1	1	3	3	3	3	2

). The value of the current is equal in switches S_ib1–S_ib4. They conduct the current during the three of four subperiods of (1) whilst the switch S_ib5 during the two of four. It creates nearly equal heat distribution from the switches. The lowest current value is seen in diodes D₁ and D₂.

The current stress of the inverter switches depends here on the modulation index (m_a) and the output power value as well as its character. Additionally, the number of switching operations of devices varies versus m_a, P_out, and Q_out. Figure 18 presents the simulation results of such comparison and the chart with the dependency of the current load of switches and diodes versus the modulation index and power. From these results (Figure 18) it is seen that for operation with the active power and high m_a, the current value of switches is nearly the same in all devices and the inequality of current stress is seen among the diodes. Under the determined range of m_a, P_out, and Q_out, the thermal design requirements can be estimated.

From Figure 3 it is also seen that voltage stress on the AIVB’s switches reaches u_CSmax (≤U_in). The voltage stress of semiconductor devices in the inverter is equal to the U_in (which 1/3 of the total DC-link voltage).

3.5. Step Change of Load

The AIVB does not regulate voltage in a closed loop control, but it operates with the unity voltage gain (U_C3 = U_C2 and U_C1 = U_C2). Its dynamics can be described as a first order system, which is demonstrated by the example simulation results presented in Figure 19 where the step changes of load occur on the AC side.

4. Experimental Results

The experimental tests were performed with the converters and setup described in Figure 20. The experiment was prepared to confirm the correctness of the concept of the system configuration and control. The system is composed of two converters and two methods of the input power control were verified as well. To implement the single-phase inverter at 400 V on DC-link, the MOSFET with V_DS = 200 V and low on-state resistance were used. The AIVB was designed as a GaN based converter to minimize C_oss losses, since operating in ZCS mode transistors of the AIVB are turned-on when their output capacitance is charged. A typical drain to source voltage V_DSS = 650 V allows to avoid overvoltage failure in the tested AIVB circuit.

4.1. Operation of the Inverter with the PD-PWM Method and Three DC Sources

Using the setup configured according to Figure 5a, where the voltage on each DC-link capacitor is supplied by an independent DC power supply, the seven-level inverter with the PD-PWM was verified. Figure 21 presents the waveforms of the inverter operating with P_out = 982 and the measurements of particular input powers with the values: P_C1 = 255 W, P_C3 = 251 W, and P_C2 = 521 W. This means that over 50% of the power can be converted to the AC side directly from the source which is connected to the C₂ (Figure 1) and 50% of energy will be converted by the boost stage in the system with the AIVB.

4.2. Operation of the AIVB

The operation of the AIVB is documented by the experimental waveforms presented in Figure 22, Figure 23, Figure 24, Figure 25 and Figure 26. The results illustrate that the converter operates exactly in accordance with the original concept. The switched capacitor is charged from the C₂ DC-link capacitor in the circuit composed of two resonant inductors. It is further discharged to the upper and lower DC-link capacitors (C₁ or C₃) in a series connection with one of the resonant inductors.

4.3. Operation of the Inverter with the AIVB Converter

In the analyzed system, the energy source is connected to the middle capacitor (C₂) of the DC-link of the seven-level NPC bridge inverter (as Figure 1). The AIVB transfers the energy to other capacitors of the DC-link (C₁ and C₃). It assures the input voltage boosting and the DC-link voltage balancing. The operation of the AIVB is confirmed by the results presented in Figure 22. Figure 23 and Figure 24 demonstrate the operation of the whole system, where the AIVB is controlled according to the switching order defined by function (1) with a constant switching frequency. In this low complex method, the voltage on the DC-link capacitors is maintained correctly. Any measurements on the DC-link capacitors are not required. Power of the AIVB depends on the instantaneous power on the output of the inverter.

To reduce the 100 Hz component in the source current, power control can be implemented in the AIVB. The method is presented in Section 3.3 and it allows to control the power of the AIVB by variation of its switching frequency. Figure 25 and Figure 26 present the operation of the DC-AC system with the AIVB operation with variable frequency. These results show that the significant reduction of the 100 Hz component in the current of the DC-power supply connected with the C₂ capacitor can be achieved by the control of the AIVB.

For the demonstrated implementation of the converter (Figure 20), the overall efficiency results are presented in Figure 27.

5. Comparison to Existing Solutions

The demonstrated results prove a versatile ability of the proposed front-end converter for the DC-link voltages management in the four-level NPC converter. The converter is finally compared to other topologies of auxiliary balancing circuits (

Table 3. Comparison of circuits for voltage balance.

Number of Components and Gain	Ref. [10]	Ref. [11]	Ref. [12]	Ref. [13]	Ref. [14]	Ref. [17]	Proposed
Switches	8	8/12	8	6	8	5	5
Diodes	4	0	0	0	0	2	2
Inductors	2 (2 or 5 mH)	2 (20 mH)	2	0	0	0	2 × 3 µH
Capacitor	0	2/4 2.2 mF	2 9.4 mF	2 2.2 mF	3 470 μF	0	1 260 nF
DC-link capacitors	3	4	4	3	4	3	3
Voltage Gain Ability	1	1	1	3	2 or 4 *	3	3

* with 12 switches.

). The comparison of the number and volume of components can be considered beneficial for the proposed circuit as it uses one 260 nF switched capacitor and low volume 3 µH resonant inductor.

Table 4. Comparison of the proposed converter to switched-capacitor 7-level boost-inverters (the type of total standing voltage TSV coefficients specified as in cited references).

Parameter	Ref. [29]	Ref. [30]	Ref. [31]	Ref. [32]	Proposed
Gain	3	3	1.5	1.5	3
Switches	12	8	9	10	17
Diodes	11	1	-	-	10 (and 3 protection diodes)
Voltage stress on switches	TSVp.u. = 5.3	TSVp.u. = 6	TSV × Vstep = 16	0.5 Vdc (2 switches) Vdc (6 switches) 2 Vdc (2 switches) TSVp.u. = 11/1.5 = 7.3	TSVp.u. = 7.3 TSV × Vstep = 22

presents the comparison of the proposed converter with 7-level single phase inverter based on SC technique. An important benefit of the proposed converter, which is seen when compared to the other SC inverters, is its AC power decoupling ability. Furthermore, the presented AIVB front-end converter can be used in 3-phase NPC inverter with 4-level legs for voltage boosting and DC-link voltage balancing. It is also important that in some power converter topologies based on a pure switched capacitor concept, the problem of inrush currents exists and often makes the design challenging. Therefore, another positive quality of the proposed converter is the concept of resonant circuits in the front-end AIVB converter and recharging the switched capacitor by oscillatory currents.

6. Conclusions

In the proposed concept of the bridge inverter composed of four-level NPC legs and the active input voltage balancer (AIVB) in front, the three-fold boosting of the input voltage and the DC-link voltage balancing is achieved. It is favorable that the majority of energy can be transferred from the source to the AC side without DC-DC conversion, directly from the middle capacitor of the DC-link. The AIVB transfers only part of the energy among the DC-link capacitors.

This paper presents the novel concept of the system with an original input balancer (AIVB) and two methods of its control. In the first method the AIVB operates with a given sequence of switching states with a constant frequency. This simple strategy assures an adequate DC-link capacitor voltage balance and operation of the system. In the second proposed approach, the power of the AIVB is synchronized with the output power. It is a very favorable approach of a single-phase system as it allows for a decrease in the variable component in the DC source current at double frequency of the output voltage. The instantaneous power of the AIVB can be controlled by its switching frequency variation, to decrease when the output power increases.

The proposed system can be considered for single-phase photovoltaic systems. Typical functions required in such conversion systems, such as voltage boosting, AC power decoupling and DC-link voltage balancing, are assured by the proposed converter. The performed experiment shows that the 7-level inverter can operate at 400 V on the DC-link using MOSFET switches with V_DS = 200 V and very low R_DS(on).