1. Introduction
Three-phase voltage-source inverters (VSIs) are widely adopted in different applications. In the case of unbalanced AC loads, four-wire topologies are employed in place of the classical three-wire inverters due to their built-in feature to handle zero-sequence components of both voltages and currents [
1]. Typical applications for this kind of topology are grid-forming converters [
2,
3], shunt power filters [
4,
5], active rectifiers [
6,
7,
8,
9,
10], electric drives [
11], and battery chargers for electric vehicles [
12,
13,
14]. Recently, these converters have been considered for trending smart EV chargers that are featuring vehicle-to-grid (V2G), vehicle-to-home (V2H), or even vehicle-to-vehicle (V2V) operating modes. Several configurations exist and have recently been studied in the literature, such as four-leg topologies with [
15,
16] and without [
8,
13,
17] a neutral inductor, and four-wire split capacitor inverters, also with [
18] and without [
19] a neutral inductor.
Different modulation strategies have been proposed in the literature to control these converters—namely, space vector modulation (SVM) and carrier-based techniques. The latter are widely adopted because of their simplicity in analog and digital implementation, well-known harmonic spectrum that makes the filter design easier, and the fixed switching frequency. This last aspect is advantageous when the converter switching losses must be evaluated by simplifying the whole converter design. Among the different carrier-based PWM techniques, the sinusoidal PWM (SPWM) and the centered PWM (CPWM) are the most employed and are taken into consideration in this paper. In particular, CPWM is the SVM carrier-based equivalent [
20].
As previously mentioned, a fixed switching frequency simplifies the correct design of a power switching converter and the main parameters to consider are nominal currents and voltages, and the corresponding ripples in both the AC and the DC sides. Different studies and analyses have been presented in the literature. A lot of attention has been given to the AC voltage and current characteristics. Three-phase four-leg PWM inverters are considered in [
13] for evaluating the peak-to-peak and RMS of the current ripple in the three phases and in the neutral wire in case of a sinusoidal PWM technique. All these findings are helpful to estimate the main parameters for the correct design of the converter through straightforward equations. The authors of [
8] optimized three-phase four-leg inverter harmonic performances by employing discontinuous PWM (DPWM) techniques.
On the other hand, considering the characteristics of the DC side, several works are presented in the literature. These analyses can help to design the DC-link capacitor properly and then the whole converter. Moreover, by employing an accurate prediction of the voltage ripple, it is possible to estimate DC-link and DC filtering stage losses and evaluate the converter’s overall efficiency. The DC-link voltage switching ripple and the DC-link capacitor’s proper design have been studied in [
21] for a single-phase two-level inverter. Maximum DC-link voltage switching ripples in three-phase PWM inverters has been predicted in [
22], in the case of SVM, as a function of the modulation index and phase angle. The authors of [
23] investigated the DC-link voltage ripple for neutral point clamped (NPC) converter, and the RMS current of DC-link capacitors was evaluated for the same topology in [
24]. Considering three-phase four-wire split capacitor inverters, DC-link voltage ripples for low order harmonics were calculated in [
4,
15]. A detailed analysis of positive, negative, and zero symmetric voltage components for the same topology is provided in [
2]. An exhaustive study of the DC-link voltage ripple with respect to the switching frequency was given for both the total DC-link voltage and the capacitor voltages in [
19]. Differently from the current manuscript, no mention of the single-phase connection typical of domestic applications (for instance, V2G/V2H) has been presented. In [
25], authors have estimated the power losses in the DC-link ESR on the base of the capacitor current RMS caused by the voltage ripple. All these works highlight the importance of investigating the DC-link voltage and current characteristics.
However, to the best of the authors’ knowledge, no works provide such analysis for a three-phase four-leg PWM converter. The main novelties of this work can be summarized as follows. Firstly, the DC-link current has been calculated for both balanced and unbalanced loads. Then, the peak-to-peak DC-link voltage switching ripple has been evaluated in both cases for the sinusoidal and the centered PWM techniques. Finally, their RMS values have also been determined. The derived mathematical equations are simple and effective, and they can be used to design the DC-link capacitor properly and evaluate the whole inverter efficiency. The achieved findings are demonstrated in both simulations and experimental results.
The paper is organized as follows. In
Section 2, the system configuration under analysis is presented together with the adopted modulation principles. Then, the converter DC-link current for both balanced and unbalanced phase currents is evaluated in
Section 3. The next section provides the peak-to-peak and RMS voltage switching ripple analysis in both cases for sinusoidal and centered (SVM) PWM techniques and single-phase operations. Experimental results are given in
Section 5 to validate the mathematical findings. Finally, conclusions are drawn in
Section 6.
2. System Configuration and Modulation Principle
The four-leg topology studied here will be considered employed as an inverter in which the power is transferred from the DC side to the AC side. This is what usually happens in EV charger applications when employed in V2G and V2H operations. For this reason, the DC quantities will be indicated as “input” and the AC ones will be referred to as “output”. This choice is purely arbitrary because the voltage ripple considerations made in this manuscript are valid regardless of the power-flow direction and therefore can be straightforwardly employed in applications dealing with active rectifiers as well (for instance, grid-to-vehicle operations).
The considered three-phase four-wire four-leg inverter is depicted in
Figure 1. To analyze the ripple on the DC-link capacitor (
Cdc), an input impedance (
Ldc and
Rdc) was considered in series with the DC voltage supply (
Vdc). This representation opens to the assumption that the whole switching component of the inverter input current
i flows through the DC-link capacitor. On the output (ac) side, a set of three ideal sinusoidal currents indicated as
ia,
ib, and
ic is assumed, neglecting at this stage the output current ripple.
In the case of three-phase symmetric systems,
ma =
mb =
mc =
m, the modulating signals are obtained as the ratio between the phase reference voltages and the average of the DC-link voltage (
V), as pointed out in Equation (1). Only one phase equation among the three should be considered in the case of single-phase systems.
The injected common-mode signal γ is added to the sinusoidal modulating signals ux for obtaining the actual modulating signal identified by the symbol *. Subscript x denotes the three phases, a, b, and c, and the neutral leg n. The sinusoidal components represent a three-phase symmetric system having the modulation index m as amplitude and the fundamental (grid) angular frequency ω implicitly included in the phase angle ϑ = ωt. Given the close relationship between them, the terms t (time) and ϑ will be considered interchangeable.
In this paper, common-mode signals for SPWM and CPWM are, respectively, defined by the following relation:
It is known that the CPWM technique (equivalent to SVM) extends the linear operation from m = 0.5 (i.e., the limit of SPWM) to m = 1/√3 ≅ 0.577.
In grid-connected applications, the set of grid currents, whether balanced or not, might have pretty small variation in the modulating signals of Equation (1). Indeed, as highlighted in [
8,
13], a small voltage unbalance can cause a considerable current unbalance. For this reason, the modulating signals can be approximated as sinusoidal and balanced waveforms if such a grid voltage is considered. In the case of a classical balanced system having a unity power factor, the set of currents can be specified as:
where
Ia,
Ib, and
Ic are the amplitudes of output current on phase
a,
b, and
c, respectively.
The extreme case of unbalanced currents visible in Equation (4) has been considered to extend the validity of here presented findings. The latter is the case that can happen in EV-charging applications when the Transmission System Operator (TSO) demands to drawn/inject power from/to one specific phase only rather than having the standard power sharing among the three phases.
However, it can also be the case that that the converter is connected to a single-phase grid (for instance, EV home-charging or V2H services) using two of the four available legs with a single-phase plug. In this case, there is no need to preserve an almost symmetric three-phase modulation in the detached legs. Therefore Equations (1) and (2) can, respectively, be updated (considering phase
a as the sole active phase) as:
In this case, the grid current is the same reported in Equation (4). It can be argued that, when SPWM is employed, the converter behaves as a half-bridge, and therefore the maximum modulation index would be m = 0.5 (in linear operations). On the other hand, when CPWM is utilized, setting mb = mc = 0, the converter acts as an H-bridge, and the CPWM technique automatically extends the linear modulation up to m = 1. The best option is represented by the CPWM injection, which can guarantee a much broader operational range.
5. Experimental Results
To confirm the validity of the analytical developments introduced above, some experiments were performed on the laboratory setup, consisting of a DC source and a passive load, as shown in
Figure 17a. The resulting test circuit scheme can be obtained by merging the converter circuit (
Figure 1) with the passive load depicted in
Figure 17b. As mentioned earlier, the designed RLC load can emulate an EV charger in V2G operation with a unity power factor.
The converter is built of four half-bridge legs formed by two IGBT-based three-phase power modules (PS22A76, 1200 V, 25 A, Mitsubishi Electric Corporation, Tokyo, Japan). The DC side of the VSC is linked with an adjustable DC power supply (GEN100-33, 100 V, 33 A, TDK-Lambda Corporation, Tokyo, Japan) through a DC-link capacitor (
Cdc) and the
RL input series circuit (
Rdc,
Ldc). The input inductance serves to form the input voltage ripple path passing solely through the DC-link capacitor. The converter is connected to an induction motor (2.2 kW, 400 V) on the AC side, representing the
RL load series circuit. For this experiment, a relatively high inductance is required to minimize disruptive AC current ripple on the AC side. However, the effect of frequency-driven inductance variation in induction motors should be taken into account [
26]. In this case, inductance at the switching frequency is lower than the value at the fundamental frequency. Since this paper aims to report voltage switching ripple, it is important to obtain an AC output current that is as clean as possible from the corresponding switching current ripple. In addition to the large interface AC inductance, a slightly higher value of switching frequency was applied to mitigate AC current ripple’s detrimental effect. The
RC load parallel circuit was obtained by the parallel connection of an AC capacitor and resistor in each phase (cf.
Figure 17b). For wiring simplicity in the laboratory setup, the
RL series circuit (the induction motor) was swapped with
RC parallel circuit (cf.
Figure 17a,b). This modification does not introduce any change in the equivalent circuit illustrated in
Figure 17b. All the circuital parameters are summarized in
Table 1. Currents and voltages measurements were performed by employing current sensors (LA 55-P, LEM Europe GmbH, Fribourg, Switzerland) and isolated differential voltage probes (PICO TA057, Pico, Tyler, TX, USA), respectively. The converter legs were driven by a DSP board (TMS320 F28379D, Texas Instruments, Dallas, TX, USA) via isolated intermediate optical links. The modulation characteristics were regulated in an open-loop via real-time MATLAB/Simulink (MathWorks, Natick, MA, USA) platform in the external mode. The measured data samples have been acquired using digital oscilloscopes (DS1054Z, Rigol, Beijing, China) with a sampling frequency of 5 MHz. The results were plotted via MATLAB, without additional pre-filtering, unless otherwise specified.
The amplitude of the AC current
I is directly proportional to the modulation index
m, according to:
where
v and
Zeq are the voltage of the DC supply minus voltage drop due to
RL input circuit (cf.
Figure 1) and the unity power factor load impedance, respectively. With reference to
Table 1,
Zeq ≅ 18.8 Ω.
Since the focus is drawn to the grid-connected applications in this paper, only some experimental results associated with high values of the modulating index range are demonstrated.
Figure 18 and
Figure 19 depict the DC-link voltage ripple for three-phase VSI arrangement with balanced currents and two examined modulation schemes, SPWM and CPWM. To obtain only high-frequency (switching) components of the voltage ripple, the measured waveform was prefiltered using a bandpass filter with bandwidth from 1 to 50 kHz. Both figures illustrate two subcases at
m = 0.3 (a) and
m = 0.5 (b). As can be seen, the acquired ripple measurements reasonably match with the analytical envelopes calculated by Equation (23) for SPWM and Equation (27) for CPWM, taking into account the scaling factor
I/(
fsw Cdc) and the amplitude of the AC current
I discussed in Equation (53). It is also interesting to note the frequency doubling effect in
Figure 19 with respect to the voltage ripples at similar modulating indices in
Figure 18. As was discussed in
Section 4.2.3, this happens since primary and secondary ripples have similar magnitudes. The time range in the experimental plots is preserved in terms of how data were acquired. Namely, timing “0” represents the triggering time instant. Simultaneously, the negative and positive diapasons denote the time spans before and after the triggering moment, respectively.
Similarly, the RMS value of the DC voltage ripple can be obtained. Strictly speaking, one should introduce the amplitude of the AC current I from Equation (53) into Equation (40) for SPWM and into Equation (42) for CPWM modulation cases.
An excellent correlation of the theoretical RMS voltage ripple profile with the measured RMS values can be observed in
Figure 20. However, one may notice a slight mismatch of the experimental values at a low range of modulating indices. This fact can be explained by the prevalence of measuring noise and higher uncertainties at lower voltage ranges. Overall, the depicted experimental results confirm the presented development’s validity for the balanced three-phase load/grid operation.
The above considerations are highlighted again in the absolute and relative error assessment in
Table 2. Although the absolute error appears to be restrained in the whole modulating index range, the noise’s effect is particularly detrimental in low-ripple working points (
m < 0.2), where the relative error rises above 1%.
For the sake of completeness, the AC current and phase voltage are depicted in
Figure 21. As visible from
Figure 21a, a set of balanced sinusoidal phase currents has been obtained with a small residual switching current ripple. The harmonic content of the associated phase current (ph.
a) is shown in
Figure 21b. On the other hand,
Figure 21c shows the phase voltage having an identical phase angle with a fundamental component of the corresponding phase current, validating the unity power factor operation.
Figure 22 demonstrates the DC voltage ripple (red traces) and its wrapping envelopes (black traces) measured under an unbalanced single-phase. The figure presents voltage switching ripple at
m = 0.5. To obtain only high-frequency (switching) components of the voltage ripple, the measured waveform was prefiltered using a bandpass filter with a bandwidth from 1 to 50 kHz. It can be noted that primary and secondary ripple envelopes overlap with one another. Therefore, the frequency doubling effect can be observed here as well. Although the derived envelopes nicely bound the measured voltage ripple, the residual noise presence is evident. For low voltage ripple values (when the envelopes get close to zero), the measuring noise and uncertainties become predominant and start to interfere with the ripple. Compared to previous experimental plots, this phenomenon is more evident due to the small magnitude of the voltage ripple in single-phase modulation.
Figure 23 validates theoretical equations presented in
Section 4.4 regarding RMS voltage ripple for the single-phase modulation. The results are depicted for the whole linear modulation range
m ∈ [0, 1]. Differently from numerical verifications, at low modulation indices, the measuring noise and associated uncertainties dominate the voltage ripple in the whole fundamental cycle, causing an inevitable mismatch of experimental data points with the analytically derived trace.
In a similar fashion to
Table 2, a single-phase modulation error assessment is presented in
Table 3. Overall, the absolute error appears to have the same order of magnitude as the one shown in
Table 2. However, the relative error is noticeable worsened due to the single-phase modulation voltage ripple’s lower magnitude.
Overall, experimental results validate the analytical findings and reasonably match the numerical results, ensuring the proposed development’s accuracy.
6. Conclusions
Instantaneous DC-link voltage ripples in three-phase four-leg PWM inverters have been analyzed in this paper. The prediction presented here permits the analytically derivation of the peak-to-peak, maximum, and the RMS of the DC-link voltage switching ripple. Multiple real-world working modes, such as three-phase connection with balanced currents, three-phase connection with single-phase power absorption, and single-phase connection, have been considered and validated numerically and experimentally. A possible application can be easily found in the EV-charging context where different connections/plugs and transmission system operator dispatch orders can be found. Furthermore, the DC-link voltage switching ripple’s prediction is useful in designing the DC-link capacitor and the DC filtering stage to prevent harmonic pollution and mitigate electromagnetic interferences. Additionally, it can also be used to estimate converter overall efficiency and aging of capacitors.
In the case of three-phase connections, the CPWM (SVM) technique should always be preferred. In particular, in the case of a balanced absorption, the RMS value of the voltage ripple might be up to 43% lower than the SPWM counterpart. On the other hand, if the power is drawn/injected from one phase only, the benefit of CPWM is limited to a maximum voltage ripple RMS reduction of about 12%. Concerning single-phase applications, the operating range can almost double, preserving a voltage switching ripple harmonic content in the same range magnitude experienced by the three-phase one. Similar considerations concerning the voltage ripple peak-to-peak maximum value can be taken into account.
Experimental results have been provided to validate the achieved analytical findings on a four-leg converter employed in three-phase and single-phase (V2G/V2H) connection modes. It has been demonstrated that the obtained results adequately match the predicted DC voltage switching ripple. The attained relative error is within 1% for three-phase connections and within 10% for their single-phase counterparts in the most popular working conditions (i.e., m ≥ 0.4 and m ≥ 0.8, respectively).
Future studies might enlarge the prediction proposed here by taking discontinuous PWM techniques into consideration as well. Moreover, variable switching frequency PWM techniques aiming to mitigate DC-link voltage ripple could be developed based on the voltage ripple envelopes prediction carried out here.