Application of High-Frequency Leakage Current Model for Characterizing Failure Modes in Digital Logic Gates

Abedi, Zahra; Hemmady, Sameer; Antonsen, Thomas; Schamiloglu, Edl; Zarkesh-Ha, Payman

doi:10.3390/en14102906

Open AccessArticle

Application of High-Frequency Leakage Current Model for Characterizing Failure Modes in Digital Logic Gates

by

Zahra Abedi

¹,

Sameer Hemmady

¹,

Thomas Antonsen

²,

Edl Schamiloglu

¹

and

Payman Zarkesh-Ha

^1,*

¹

Department of Electrical & Computer Engineering, University of New Mexico, Albuquerque, NM 87131, USA

²

Departments of Electrical and Computer Engineering, Physics, University of Maryland, College Park, MD 20742, USA

^*

Author to whom correspondence should be addressed.

Energies 2021, 14(10), 2906; https://doi.org/10.3390/en14102906

Submission received: 26 February 2021 / Revised: 6 May 2021 / Accepted: 12 May 2021 / Published: 18 May 2021

(This article belongs to the Special Issue Electromagnetic Modeling in Power Electronics)

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Abstract

In this paper, a predictive model is developed to characterize the impact of high-frequency electromagnetic interference (EMI) on the leakage current of CMOS integrated circuits. It is shown that the frequency dependence can be easily described by a transfer function that depends only on a few dominant parasitic elements. The developed analytical model is successfully compared against measurement data from devices fabricated using 180 nm, 130 nm, and 65 nm standard CMOS processes through TSMC. Based on the predictive model, the impact of EMI on leakage current in a CMOS inverter is reduced by increasing the frequency from 10 MHz to 4 GHz.

Keywords: electromagnetic interference; leakage current; predictive modeling of CMOS inverters; VLSI systems

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MDPI and ACS Style

Abedi, Z.; Hemmady, S.; Antonsen, T.; Schamiloglu, E.; Zarkesh-Ha, P. Application of High-Frequency Leakage Current Model for Characterizing Failure Modes in Digital Logic Gates. Energies 2021, 14, 2906. https://doi.org/10.3390/en14102906

AMA Style

Abedi Z, Hemmady S, Antonsen T, Schamiloglu E, Zarkesh-Ha P. Application of High-Frequency Leakage Current Model for Characterizing Failure Modes in Digital Logic Gates. Energies. 2021; 14(10):2906. https://doi.org/10.3390/en14102906

Chicago/Turabian Style

Abedi, Zahra, Sameer Hemmady, Thomas Antonsen, Edl Schamiloglu, and Payman Zarkesh-Ha. 2021. "Application of High-Frequency Leakage Current Model for Characterizing Failure Modes in Digital Logic Gates" Energies 14, no. 10: 2906. https://doi.org/10.3390/en14102906

APA Style

Abedi, Z., Hemmady, S., Antonsen, T., Schamiloglu, E., & Zarkesh-Ha, P. (2021). Application of High-Frequency Leakage Current Model for Characterizing Failure Modes in Digital Logic Gates. Energies, 14(10), 2906. https://doi.org/10.3390/en14102906

Note that from the first issue of 2016, this journal uses article numbers instead of page numbers. See further details here.

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Application of High-Frequency Leakage Current Model for Characterizing Failure Modes in Digital Logic Gates

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