A Single-Phase Nine-Level Boost Inverter

Abstract

A novel single-phase nine-level boost inverter is proposed in this paper. The proposed inverter has an output voltage which is higher than the input voltage by switching capacitors in series and in parallel. The maximum output voltage of the proposed inverter is determined by using the boost converter circuit, which has been integrated into the circuit. The proposed topology is able to invert the multilevel voltage with the high step-up output voltage, simple structure and fewer power switches. In this paper, the circuit configuration, the operating principle, and the output voltage expression have been derived. The proposed converter has been verified by simulation and experiment with the help of PSIM software and a laboratory prototype. The experimental results match the theoretical calculation and the simulation results.

1. Introduction

Recently, multilevel inverters (MIs) have played important roles for high-power applications because of their advantages as better output voltage waveforms quality, a reduced rating of power semiconductor devices, and low electromagnetic interference [1]. The traditional MI topologies are neutral-point-clamped (NPC), flying-capacitor (FC), and cascade H-Bridge (CHB) inverters [2,3,4,5]. Diodes and capacitors are used to generate multilevel at the output voltage in NPC and FC inverters, respectively. On the other hand, to attain voltage levels, the direct current (DC) source must be increased. Nevertheless, both the circuit configurations and their controls become very complicated along with the increasing number of the output voltage levels. Furthermore, these topologies also make capacitors’ imbalanced. Some in-depth studies for NPC’s topologies have been presented in References [6,7,8]. To operate at the higher voltage level, the CHB inverters are used thanks to easy modularization and facilitate to expansion extension [9,10]. However, the topologies request more and more power devices with separate DC voltage sources. When the output voltage has more levels, the number of the required input DC sources is increased. Construction of a multilevel converter was introduced in Reference [11] with the use of multiple modules that made it easy to expand. However, this also increases the number of capacitors and switches required.

A seven-level inverter using series-connected DC voltage sources was presented in Reference [12] with the use of multiple DC voltage sources supplies to reduce switching losses. However, the number of output voltage levels depends on the number of DC voltage sources. A circuit of (4n + 3)-level inverter using voltage sources in serial/parallel operation was introduced in Reference [13] to increase the number of output voltage levels with the complex pattern and increase the conductive losses. By using an additional boost converter to create a multi-step output with capacitors, a seven-level grid-connected inverter for photovoltaic systems was presented in Reference [14], but an imbalance between capacitors is very likely to occur.

Nowadays, the switched-capacitor (SC)-based MIs are a popular solution for single-phase systems because they have a simple topology and reduce the component count. In Reference [15], a serial/parallel connection-based MI was presented. The topology of a SCMI for high-frequency aternative current (AC) microgrids was proposed in Reference [16]. SCMIs are recommended in Reference [17] with the ability to balance capacitor voltage and step-up voltage. The formerly SCMI topologies consist of SC elements with a high-voltage DC source. Then, they are divided into several floating DC sources [15,16,17,18,19] or a cascaded combination of multiple SC converters [20,21,22,23]. However, in most of these topologies, the voltage across the capacitors is only equal to the supply voltage. Therefore, the output voltages are limited. To overcome this limitation, the topology of the single-phase step-up five-level inverter was introduced in Reference [24], which uses the switch-diode-capacitor (SDC) circuit [25] and an additional booster circuit to increase the input voltage. In summary,

Table 1. Advantages and disadvantages of multilevel inverters with reduced switch count.

Topology	Literature	Advantages	Disadvantages
Series-connected DC voltage sources	Proposed in Reference [12]	Reduce switching losses	Number of output voltage levels depends on the number of DC sources Buck voltage
Switched serial/parallel DC voltage sources	Proposed in Reference [13]	Simple topology Input sources can be integrated in both parallel and series	Complex switching pattern Increase conductive losses Buck voltage
Additional boost converter	Proposed in References [14,24]	Single source Boost voltage	Capacitor imbalance is very likely to occur Two-stage conversion
Series/parallel connection	Proposed in References [15,18]	Single source Boost voltage	Large number of switches
Based on switched capacitor	Proposed in References [16,17,19,20,21]	Self-balancing in capacitor voltage Voltage boost capability	Reduce switch count but increase number of diodes High capacitor current stress
Cascaded multilevel inverter	Proposed in References [22,23]	Reduce voltage stress on H-bridge switches Boost voltage	Only show in high-frequency AC output voltage [20] Using separate dc source

shows the advantages and disadvantages of the multilevel inverters with reduced switch count.

In this paper, a new nine-level boost inverter (NLBI) is suggested. The NLBI is an extension of the five-level inverter in Reference [24]. The NLBI combines structure switched-diode-capacitor, switched-capacitor, a conventional boost converter, and an H-bridge circuit to be able to enhance boost ability of output voltage levels with the reduced circuit components. In Section 2, the topology, operating principles and circuit analysis of the proposed inverter are presented. Section 3 presents the selection of the inductor and the capacitor. Simulation and experimental results are shown in Section 4. Finally, the conclusion is summarized in Section 5.

2. Proposed Single-Phase Nine-Level Boost Inverter

Figure 1 shows the proposed single-phase NLBI. As shown in Figure 1, the proposed NLBI consists of a single DC source (V_dc), a conventional boost converter, a switched-diode-capacitor (SDC) circuit [25], a switched-capacitor (SC) circuit [17], an H-bridge circuit, a low-pass filter (L_f–C_f) and a load (R). In the SDC circuit, two capacitors C₁ and C₂ are discharged in serial when the switch S₁ is switched ON. When the switch S₁ is switched OFF, two capacitors C₁ and C₂ are charging by the diodes D₁ and D₂. In the SC circuit, the capacitor C₃ is charged through the body diode of switch S₄ when the switch S₅ is switched ON and the switch S₃ is switched OFF. When the switch S₃ is switched ON and the switch S₅ is switched OFF, the capacitor C₃ is discharged.

2.1. Operating Principle of the Proposed Inverter

Figure 2 describes the level shift multicarrier-based pulse-width modulation (PWM) scheme for the proposed single-phase NLBI. A control waveform (e_x) is compared to four carrier waveforms (e₁–e₄) which these waveforms have the identical phase and amplitude to handle the switches. A constant voltage, e_n is compared to the carrier voltage e₁ to generate a control signal for S₁, which works with duty cycle d_S1 for each cycle T_s. In Figure 1, V_B is the boost voltage value of the boost converter which equals to the collector-emitter voltage of the switch S₂. Figure 3 and Figure 4 show the operating states of the proposed NLBI.

The output voltage is positive from t₀ to t₇ with corresponding to Stages 1–7. Between t₇ and t₁₄, the output voltage is negative, corresponding to Stages 8–14. In the positive period from t₀ to t₇, the circuit operation includes seven stages and nine states (State 1 to State 9, Figure 3 and Figure 4).

Stage 1 (t₀–t₁, Figure 3a–d): When S₁ is switched ON, the inductor L₁ stores energy from the DC source. If T₁ is switched OFF, the output voltage is equal to zero (V_ab = 0) as shown in Figure 3a for State 1. If T₁ is switched ON, the output voltage is equal to the boost voltage (V_ab = V_B) as shown in Figure 3c for State 3.

When S₁ is switched OFF, the diode D₀ is forward-biased, and the inductor L₁ is discharged to the capacitors C₁ and C₂. If T₁ is switched OFF, the output voltage is zero (V_ab = 0) as shown in Figure 3b for State 2. When T₁ is switched ON, the output voltage equals the boost voltage (V_ab = V_B) as shown in Figure 3d for State 4. The operating duty cycle of the boost inductor in this stage is the duty cycle of switch S₁, d_S1.

Stage 2 (t₁–t₂, Figure 3c,d and Figure 4a): The switches S₅ and T₁ are fully switched ON. When S₂ is turned ON, whereas S₁ is switched OFF, the capacitors C₁ and C₂ are working in series supplying power to the load. The capacitor C₃ is charged by C₁ and C₂ through S₅ simultaneously. As shown in Figure 4a for State 5, the load voltage is equal to twice boost voltage (V_ab = 2V_B).

When S₂ is switched OFF, while S₁ is switched ON, the inductor L₁ stores energy from V_dc. The capacitors C₁ and C₂ are working in parallel to feed the load. Although S₅ is switched ON in this state, the current from the capacitors C₁ and C₂ cannot pass through the capacitor C₃ because the capacitor C₃ voltage is greater than the capacitor C₁ and C₂ voltages. Consequently, there is no current flow to S₅ and the load is connected to the capacitors C₁ and C₂ in parallel. This state is the same as the State 3 as shown in Figure 3c, the output voltage equals the boost voltage (V_ab = V_B). The control signal of S₅ during this stage can be changed in another way, which is similar to the control signal for S₂. To reduce the switching losses, the control signal of S₅ is always controlled ON during this stage.

Similarly, when S₁ is switched OFF, whereas S₅ is turned ON, the output voltage is equal to the boost voltage (V_ab = V_B), which is the same as the State 4 as shown in Figure 3d.

As shown in Figure 2, the duty cycle of S₂ in this stage is gradually increased, while the duty cycle of S₁ is fixed at d_S1. The time interval of Stage 2 is divided into two subintervals. In the first subinterval (t₁–t_1m, see Figure 5a), the duty cycle of S₁ is greater than that of S₂. The operating duty cycle of the boost inductor in the first subinterval is d_S1. In the second subinterval (t_1m–t₂, see Figure 5a), the duty cycle of S₂ is more than that of S₁. As a result, the operating duty cycle of the boost inductor in the second subinterval depends on the duty cycle of S₂. The average duty cycle of the boost inductor in this sub-stage can be approximated as

$$d_{S2}\approx \frac{1+d_{S1}}{2},$$

(1)

The time t_1m is calculated as

$$t_{1m}=\frac{{\sin }^{-1}\left(\frac{1+d_{S1}}{A_m}\right)}{2\pi f_{out}},$$

(2)

where f_out and A_m are the frequency of the output voltage and the peak amplitude of control waveform e_x, respectively.

Stage 3 (t₂–t₃, Figure 4b–d): The switch S₃ is complementary to the switch S₂. When S₃ is switched ON, the load voltage is equal to three times the boost voltage (V_ab = 3V_B). If S₁ is switched ON, the inductor L₁ stores energy from V_dc, while the capacitors C₁ and C₂ working in parallel are connected in series to the capacitor C₃ for supplying power to the load as shown in Figure 4c for State 7. When S₁ is switched OFF, the capacitors C₁ and C₂ are charged by the DC voltage source, while the capacitor C₃ is still connected in series with the capacitors C₁ and C₂ as shown in Figure 4d for State 8.

When the switch S₂ is switched ON and the switch S₃ is switched OFF, the inductor L₁ stores energy while the capacitors C₁ and C₂ are in series for supplying power to the load. From Figure 4b for State 6, it can be seen that the output voltage of the inverter equals to twice boost voltage (V_ab = 2V_B).

As shown in Figure 2, the duty cycle of S₂ in this stage is gradually decreased, while the duty cycle of S₁ is fixed at d_S1. The time interval of Stage 3 is divided into two subintervals. In the first subinterval (t₂–t_2m, see Figure 5b), the duty cycle of S₂ is more than that of S₁. The inductor is almost charged during the first subinterval. Therefore, the operating duty cycle of the boost inductor is 1.

In the second subinterval (t_2m–t₃, see Figure 5b), the duty cycle of S₁ is greater than that of S₂. The operating duty cycle of the boost inductor in the second subinterval is total duty cycle of the switches S₁ and S₂, we have

$$d_x=d_{S1}+d_{S2},$$

(3)

where d_S2 is average duty cycle of the switch S₂ in the second subinterval and calculated approximately as (1).

The time t_2m is defined as

$$t_{2m}=\frac{{\sin }^{-1}\left(\frac{2+d_{S1}}{A_m}\right)}{2\pi f_{out}},$$

(4)

Stage 4 (t₃–t₄, Figure 4c–e): When the switches S₁, S₂ and S₃ are switched ON, whereas the switch S₅ is switched OFF, the capacitors C₁, C₂ and C₃ are working in series for supplying power to the load. The load voltage is equal to four times the boost voltage (V_ab = 4V_B) as shown in Figure 4e for State 9. Other states in this stage to reach the output voltage at three times boost voltage are the same as those in Stage 3. In the control method as shown in Figure 2, the duty cycle of S₁ is always greater than S₂ in terms of time (t₃–t₄) and (t₁₀–t₁₁) so that the calculation becomes simpler. Therefore, the following condition is obtained as

$$d_{S1}>A_m-3$$

(5)

The operating duty cycle of the boost inductor in Stage 4 is d_S1.

Stage 5—(t₄–t₅, Figure 4b–d: the same as Stage 3)

Stage 6—(t₅–t₆, Figure 3c,d and Figure 4a: the same as Stage 2)

Stage 7—(t₆–t₇, Figure 3a–d: the same as Stage 1)

In the negative period from t₇ to t₁₄ including seven stages and nine states, the switch T₂ is fully switched ON, while T₁ is fully switched OFF. The signal T₃ is obtained by comparing the carrier e₁ and the control waveform e_x. The signal T₄ is the opposite. All the remaining switches have the same states as in the positive period. The load voltage of the proposed inverter is summarized in

Table 2. Different Switching, Capacitor, and Inductor States of the Proposed NLBI.

State	Stage	ON Diodes	ON Switches	Capacitor State			Inductor L1 State	Output Voltage
				C1	C2	C3
1	1, 7		S1, S4, T2, T4	I	I	I	+	0
2	1, 7	D0, D1, D2	S4, T2, T4	+	+	I	−	0
3	1, 2, 6, 7	D1, D2	S1, S4, T1, T4	−	−	I	+	VB
4	1, 2, 6, 7	D0, D1, D2	S4, T1, T4	+	+	I	−	VB
5	2, 6	D0	S2, S4, S5, T1, T4	−	−	+	+	2 VB
6	3, 5	D0	S2, S4, T1, T4	−	−	I	+	2 VB
7	3, 4, 5	D1, D2	S1, S3, T1, T4	−	−	−	+	3 VB
8	3, 4, 5	D0, D1, D2	S3, T1, T4	+	+	−	−	3 VB
9	4	D0	S1, S2, S3, T1, T4	−	−	−	+	4 VB
10	8, 14		S1, S4, T2, T4	I	I	I	+	0
11	8, 14	D0, D1, D2	S4, T2, T4	+	+	I	−	0
12	8, 9, 13, 14	D1, D2, D3	S1, S4, T2, T3	−	−	I	+	−VB
13	8, 9, 13, 14	D0, D1, D2, D3	S4, T2, T3	+	+	I	−	−VB
14	9, 14	D0, D3	S2, S4, S5, T2, T3	−	−	+	+	−2 VB
15	10, 12	D0, D3	S2, S4, T2, T3	−	−	I	+	−2 VB
16	10, 11, 12	D1, D2	S1, S3, T2, T3	−	−	−	+	−3 VB
17	10, 11, 12	D0, D1, D2	S3, T2, T3	+	+	−	−	−3 VB
18	11	D0	S1, S2, S3, T2, T3	−	−	−	+	−4 VB

Here “I”, “+” and “−” refer to the idle, charging and discharging states, respectively.

.

2.2. Circuit Analysis of the Proposed Inverter

The circuit analysis is begun with the following assumptions: the capacitors C₁ and C₂ are equal, the capacitance is large enough to the voltage across the capacitor is constant, and the pairs of diodes–capacitors (D₁–C₁ and D₂–C₂) are symmetrical and balanced. The operating states of the proposed NLBI simplify into two operating modes: charging inductor and discharging inductor. The charging inductor modes are given in Figure 3a–e. These states are controlled by switch S₁ and S₂, and the inductor L₁ is charged at this time.

Assuming that the T_avg is the average time interval of the charging inductor mode during the period T_s, and d_avg = T_avg/T_s is the average duty cycle of the boost inductor in each period T_s. When S₁ or S₂ is switched ON, the inductor stores energy as shown in Figure 3a–e for States 1, 3, 5, 6, 7 and 9, respectively. The inductor L₁ voltage is:

$$V_L=V_{dc}$$

(6)

When both S₁ and S₂ switches are switched OFF, the inductor is discharged as shown in Figure 3b,d and Figure 4d for States 2, 4 and 8, respectively. The average time of this mode is (1 − d_avg)T_s. The following equations are obtained as

$$\{\begin{array}{l}{V}_L=V_{dc}-V_B\\ V_B=V_{C1}=V_{C2}\end{array}$$

(7)

Because the average voltage crossing the inductor during a period of T_s is zero, from (6) and (7), the boost voltage is calculated as

$$V_B=\frac{1}{1-d_{avg}}{V}_{dc}$$

(8)

The boost factor of the NLBI is determined as

$$B=\frac{V_B}{V_{dc}}=\frac{1}{1-d_{avg}}.$$

(9)

From the analysis of the proposed NLBI in Section 2. The operating duty cycle of the boost inductor is summarized as

$$d_{L1}=\{\begin{array}{ll}{d}_{S1}& t_0\le t<t_{1m}\hspace{0.17em}\mathrm{and}\hspace{0.17em}{t}_3\le t<t_4\\ 0.5(1+d_{S1})& t_{1m}\le t<t_2\\ 1& t_2\le t<t_{2m}\\ 0.5(1+d_{S1})& t_{2m}\le t<t_3,\end{array}$$

(10)

where

$$t_2=\frac{{\sin }^{-1}\left(\frac{2}{A_m}\right)}{2\pi f_{out}},t_3=\frac{{\sin }^{-1}\left(\frac{3}{A_m}\right)}{2\pi f_{out}}$$

The influence of the operating states of S₁ and S₂ on the duty cycle of the circuit is not the same in each operating state. However, the operation of S₁ and S₂ is repeated after a quarter cycle of the output cycle. In one-four time interval of the output voltage time period, the average duty cycle of the boost inductor is calculated as

$$d_{avg}=d_{S1}+2(1-d_{S1})\left(\frac{t_3+t_{2m}-t_2-t_{1m}}{T_{out}}\right),$$

(11)

where T_out = 1/f_out is the period of the output voltage. The voltage gain (G) is expressed as

G = A_mB

(12)

3. Inductor and Capacitor Selections

Figure 6 shows the inductor current and capacitor voltage waveforms in the positive output voltage. In Figure 6, the voltage waveforms on capacitors C₁ and C₂ are the same and equal to V_C.

Assuming that the output power (P_OUT) equals the input power, the average input current can be calculated as

$$I_{L1}=\frac{P_{OUT}}{V_{dc}}$$

(13)

The current ripple of the inductor is defined as

$$\Delta I_{L1}\approx {\displaystyle \underset{t_3}{\overset{t_4}{\int }}\frac{d{i}_{L1}}{dt}}dt=\frac{1}{L_1}{\displaystyle \underset{t_3}{\overset{t_4}{\int }}\left[d_{S1}{V}_{dc}+d_{S1}(V_{dc}-V_C)\right]}dt=d_{S1}\frac{V_{dc}(2-B)}{L_1}(t_4-t_3),$$

(14)

where

$$t_4=\frac{\pi -{\sin }^{-1}\left(\frac{3}{A_m}\right)}{2\pi f_{out}}$$

The inductance is determined by the current ripple factor K_L as

$$K_L=\frac{\Delta I_{L1}}{I_{L1}}=\frac{d_{S1}{V_{dc}}^2(2-B)}{P_{OUT}{L}_1}(t_4-t_3).$$

(15)

The inductance is selected as

$$L_1\ge \frac{d_{S1}{V_{dc}}^2(2-B)}{P_{OUT}{K}_L}(t_4-t_3).$$

(16)

The capacitance C_i (i = 1, 2 and 3) can be calculated based on the voltage ripple on the capacitors C_i. In this case, the capacitor C_i is determined by the maximum voltage ripple at k% of the maximum voltages of the capacitors. The capacitors C₁ and C₂ are charged when the switches S₁ and S₂ are switched OFF. The capacitors C₁ and C₂ are discharged in the remaining cases of the switches S₁ and S₂. The capacitor C₃ is charged when the switch S₅ is switched ON, whereas it is discharged when the switch S₅ is switched OFF.

Assuming that the output load has the power factor (cosφ) of 1, the longest discharging term of the capacitor C₃ in the proposed NLBI is between t₂ and t₅ as shown in the Figure 6. The maximum discharge amounts Q₃ of the capacitor C₃ is:

$$Q_3\simeq I_o\left(t_4-t_3\right)+I_o\sin \left(2\pi f_{out}{t}_3\right)\left(t_3-t_2\right),$$

(17)

where I_o is the amplitude the output current. When the Q₃ is less than k% of the maximum charge of C₃, the capacitance C₃ needs to meet the condition as:

$$C_3\ge \frac{Q_3}{k{V}_{C3}}.$$

(18)

The reduction of the capacitor C₁ or C₂ voltages is equal to the incensement of the capacitor C₃ voltage at times t₁ and t₅ as shown in Figure 6. At this time, the charging of capacitor C₃ affects the ripple of capacitors C₁ or C₂. Because the capacitor C₃ voltage is twice the capacitor C₁ voltage, the ripple of capacitor C₁ will be larger than that of the capacitor C₃. Therefore, the capacitance of selected capacitors C₁ and C₂ will be greater than or equal to the capacitance of capacitor C₃.

4. Simulation and Experimental Results

4.1. Simulation Results

PSIM 9.1.1 software was studied to verify the operational principle of NLBI. The input voltage is set at V_dc = 24 V and the simulation power is 680 W. The inductor L₁ = 2 mH. The capacitors C₁ = C₂ = C₃ = 2200 µF. The switching frequency is 15 kHz. Connect the resistor R = 36 Ω and use the inductor capacitor (LC) filter L_f = 2.5 mH, C_f = 1 µF.

Figure 7 shows the simulation results of the NLBI when A_m = 3.4, d_S1 = 0.4. Figure 7a shows the nine-level output voltage V_ab, the load current i_o and the ripple voltage of the capacitors (V_C1, V_C2, V_C3). Figure 7b shows the voltage waveform of the switches S₁, S₂, S₃, S₅ and the voltage waveform of the H-bridge switches T₁–T₄. The capacitor voltages V_C1, V_C2 and V_C3 are boosted to 65 V from the input voltage of 24 V. The maximum voltage of the switches S₁ and S₂ is 65 V, while the maximum voltage of the switches S₃ and S₅ is 130 V. The maximum voltage on the switches T₁–T₄ is 260 V. Figure 7c,d show the harmonic spectrum of the output voltage V_ab and the load current i_o in the frequency domain, respectively. As seen in Figure 7c, the main component appears around the frequency of 15 kHz and 30 kHz.

4.2. Experimental Results

A 350 W prototype based on TMS320F28335 DSP was built as shown in Figure 8. The input DC voltage is 24 V. The output voltage is 110 V_rms/50 Hz. The specifications of the experiment are given in

Table 3. Operating Parameters for the Proposed Inverter.

Parameter		Value
Power rating		350 W
Input voltage (Vdc)		24 V
Output voltage (Vab)		110 Vrms/50 Hz
Carrier ware frequency (fs)		15 kHz
Inductors	L1	2 mH
	Lf	1 mH
Capacitors	C1, C2, C3	2200 µF/200 V
	Cf	1 µF
Power switches	S1, S2, S3, S4	47N60C3
	S5	G40N60
	T1, T2, T3, T4	G40N120
Diodes (D0, D1, D2, D3)		DSEI60-06A
Gate drives		TLP250 (Photo-coupler)

. The switches S₁, S₂, S₃ and S₄ are 47N60C3 MOSFETs, whereas the other switches are G40N120 IGBTs. Note that the switch S₅ refers to MOSFET. Because the MOSFET without body diode is not available in the laboratory, a G40N60 IGBT without body diode is used in the experiment.

Figure 9 shows the experimental results of the NLBI when A_m = 3.4, d_S1 = 0.4. Figure 9a shows the waveforms of the output voltage V_ab and the load current i_o. As shown in Figure 9a, the output voltage has nine levels. As shown in Figure 9b, the capacitors C₁, C₂ and C₃ voltage are boosed to 52.2 V, 52.2 V and 92.5 V from the input voltage of 24 V, respectively. Figure 9c,d show the experiment results of switches S₁, S₂, S₃, S₅ voltage and switches T₁–T₄ voltage of the H-bridge circuit, respectively. Figure 9e,f shows the harmonic spectrum of the output voltage, V_ab and harmonic spectrum of output current.

Table 4. Comparison between Calculated, Simulated and Experimental Values.

Data from	Vab (V)	ΔVab (%)	B	VC1 and VC2 (V)	VC3 (V)
Theory	156.2	0	2.7	65	130
Simulation	152.2	2.56	2.7	64.6	122.3
Experiment	110	29.57	2.17	52.2	92.5

Here “ΔV_ab” is the percentage change between experiment and simulation versus theory.

lists the theoretical, simulation and experimental values of B, V_C1, V_C2 and V_C3 when d_S1 = 0.4, V_dc = 24 V, and A_m = 3.4. It can be seen from Table 4 that the simulation value is approximately equal to the theoretical value, which shows the correctness of the theoretical analysis. Moreover, the experimental value is less than that of corresponding theoretical value because the power losses are found in the experimental prototype. The voltage on capacitor C₃ is not equal to the sum of capacitors C₁ and C₂ because the discharge time of capacitor C₃ is longer associated with the losses on switches S₂, S₄, S₅ when charging capacitor C₃.

5. Conclusions

In this paper, a nine-level boost inverter which decreases the number of switching elements by switching the capacitor in series and in parallel has been suggested. The main advantage of the NLBI in comparison with the traditional topology is that the number of switches is reduced with using only a single DC voltage source. Therefore, the economic benefits from the proposed inverter come from the size and cost reduction of the inverter system. The output voltage expression and the parameter calculation are presented. Moreover, a control method based on the PWM technique is proposed for the proposed inverter. Finally, the simulation and experimental results of the NLBI are presented to validate its viability, well-performance, and effectiveness of suggested modulation strategy. The proposed inverter is suitable for low-power applications, where a low input voltage from renewable energy sources such as solar cell, fuel cell and battery needs to convert to a single-phase AC source.