A Single-Phase Nine-Level Boost Inverter

A novel single-phase nine-level boost inverter is proposed in this paper. The proposed inverter has an output voltage which is higher than the input voltage by switching capacitors in series and in parallel. The maximum output voltage of the proposed inverter is determined by using the boost converter circuit, which has been integrated into the circuit. The proposed topology is able to invert the multilevel voltage with the high step-up output voltage, simple structure and fewer power switches. In this paper, the circuit configuration, the operating principle, and the output voltage expression have been derived. The proposed converter has been verified by simulation and experiment with the help of PSIM software and a laboratory prototype. The experimental results match the theoretical calculation and the simulation results.


Introduction
Recently, multilevel inverters (MIs) have played important roles for high-power applications because of their advantages as better output voltage waveforms quality, a reduced rating of power semiconductor devices, and low electromagnetic interference [1].The traditional MI topologies are neutral-point-clamped (NPC), flying-capacitor (FC), and cascade H-Bridge (CHB) inverters [2][3][4][5].Diodes and capacitors are used to generate multilevel at the output voltage in NPC and FC inverters, respectively.On the other hand, to attain voltage levels, the direct current (DC) source must be increased.Nevertheless, both the circuit configurations and their controls become very complicated along with the increasing number of the output voltage levels.Furthermore, these topologies also make capacitors' imbalanced.Some in-depth studies for NPC's topologies have been presented in References [6][7][8].To operate at the higher voltage level, the CHB inverters are used thanks to easy modularization and facilitate to expansion extension [9,10].However, the topologies request more and more power devices with separate DC voltage sources.When the output voltage has more levels, the number of the required input DC sources is increased.Construction of a multilevel converter was introduced in Reference [11] with the use of multiple modules that made it easy to expand.However, this also increases the number of capacitors and switches required.
A seven-level inverter using series-connected DC voltage sources was presented in Reference [12] with the use of multiple DC voltage sources supplies to reduce switching losses.However, the number of output voltage levels depends on the number of DC voltage sources.A circuit of (4n + 3)-level inverter using voltage sources in serial/parallel operation was introduced in Reference [13] to increase the number of output voltage levels with the complex pattern and increase the conductive losses.By using an additional boost converter to create a multi-step output with capacitors, a seven-level Energies 2019, 12, 394 2 of 14 grid-connected inverter for photovoltaic systems was presented in Reference [14], but an imbalance between capacitors is very likely to occur.
Nowadays, the switched-capacitor (SC)-based MIs are a popular solution for single-phase systems because they have a simple topology and reduce the component count.In Reference [15], a serial/parallel connection-based MI was presented.The topology of a SCMI for high-frequency aternative current (AC) microgrids was proposed in Reference [16].SCMIs are recommended in Reference [17] with the ability to balance capacitor voltage and step-up voltage.The formerly SCMI topologies consist of SC elements with a high-voltage DC source.Then, they are divided into several floating DC sources [15][16][17][18][19] or a cascaded combination of multiple SC converters [20][21][22][23].However, in most of these topologies, the voltage across the capacitors is only equal to the supply voltage.Therefore, the output voltages are limited.To overcome this limitation, the topology of the single-phase step-up five-level inverter was introduced in Reference [24], which uses the switch-diode-capacitor (SDC) circuit [25] and an additional booster circuit to increase the input voltage.In summary, Table 1 shows the advantages and disadvantages of the multilevel inverters with reduced switch count.In this paper, a new nine-level boost inverter (NLBI) is suggested.The NLBI is an extension of the five-level inverter in Reference [24].The NLBI combines structure switched-diode-capacitor, switched-capacitor, a conventional boost converter, and an H-bridge circuit to be able to enhance boost ability of output voltage levels with the reduced circuit components.In Section 2, the topology, operating principles and circuit analysis of the proposed inverter are presented.Section 3 presents the selection of the inductor and the capacitor.Simulation and experimental results are shown in Section 4. Finally, the conclusion is summarized in Section 5.

Proposed Single-Phase Nine-Level Boost Inverter
Figure 1 shows the proposed single-phase NLBI.As shown in Figure 1, the proposed NLBI consists of a single DC source (V dc ), a conventional boost converter, a switched-diode-capacitor (SDC) circuit [25], a switched-capacitor (SC) circuit [17], an H-bridge circuit, a low-pass filter (L f -C f ) and a load (R).In the SDC circuit, two capacitors C 1 and C 2 are discharged in serial when the switch S 1 is switched ON.When the switch S 1 is switched OFF, two capacitors C 1 and C 2 are charging by the diodes D 1 and D 2 .In the SC circuit, the capacitor C 3 is charged through the body diode of switch S 4 Energies 2019, 12, 394 3 of 14 when the switch S 5 is switched ON and the switch S 3 is switched OFF.When the switch S 3 is switched ON and the switch S 5 is switched OFF, the capacitor C 3 is discharged.

Operating Principle of the Proposed Inverter
Figure 2 describes the level shift multicarrier-based pulse-width modulation (PWM) scheme for the proposed single-phase NLBI.A control waveform (ex) is compared to four carrier waveforms (e1-e4) which these waveforms have the identical phase and amplitude to handle the switches.A constant voltage, en is compared to the carrier voltage e1 to generate a control signal for S1, which works with duty cycle dS1 for each cycle Ts.In Figure 1, VB is the boost voltage value of the boost converter which equals to the collector-emitter voltage of the switch S2.Figures 3 and 4 show the operating states of the proposed NLBI.

Operating Principle of the Proposed Inverter
Figure 2 describes the level shift multicarrier-based pulse-width modulation (PWM) scheme for the proposed single-phase NLBI.A control waveform (e x ) is compared to four carrier waveforms (e 1 -e 4 ) which these waveforms have the identical phase and amplitude to handle the switches.A constant voltage, e n is compared to the carrier voltage e 1 to generate a control signal for S 1 , which works with duty cycle d S1 for each cycle T s .In Figure 1, V B is the boost voltage value of the boost converter which equals to the collector-emitter voltage of the switch S 2 .Figures 3 and 4 show the operating states of the proposed NLBI.

Operating Principle of the Proposed Inverter
Figure 2 describes the level shift multicarrier-based pulse-width modulation (PWM) scheme for the proposed single-phase NLBI.A control waveform (ex) is compared to four carrier waveforms (e1-e4) which these waveforms have the identical phase and amplitude to handle the switches.A constant voltage, en is compared to the carrier voltage e1 to generate a control signal for S1, which works with duty cycle dS1 for each cycle Ts.In Figure 1, VB is the boost voltage value of the boost converter which equals to the collector-emitter voltage of the switch S2.Figures 3 and 4 show the operating states of the proposed NLBI.The output voltage is positive from t0 to t7 with corresponding to Stages 1-7.Between t7 and t14, the output voltage is negative, corresponding to Stages 8-14.In the positive period from t0 to t7, the circuit operation includes seven stages and nine states (State 1 to State 9, Figures 3 and 4).
Stage 1 (t0-t1, Figure 3a-d): When S1 is switched ON, the inductor L1 stores energy from the DC source.If T1 is switched OFF, the output voltage is equal to zero (Vab = 0) as shown in Figure 3a  When S2 is switched OFF, while S1 is switched ON, the inductor L1 stores energy from Vdc.The capacitors C1 and C2 are working in parallel to feed the load.Although S5 is switched ON in this state, the current from the capacitors C1 and C2 cannot pass through the capacitor C3 because the capacitor C3 voltage is greater than the capacitor C1 and C2 voltages.Consequently, there is no current flow to S5 and the load is connected to the capacitors C1 and C2 in parallel.This state is the same as the State 3 as shown in Figure 3c, the output voltage equals the boost voltage (Vab = VB).The  The output voltage is positive from t0 to t7 with corresponding to Stages 1-7.Between t7 and t14, the output voltage is negative, corresponding to Stages 8-14.In the positive period from t0 to t7, the circuit operation includes seven stages and nine states (State 1 to State 9, Figures 3 and 4 When S2 is switched OFF, while S1 is switched ON, the inductor L1 stores energy from Vdc.The capacitors C1 and C2 are working in parallel to feed the load.Although S5 is switched ON in this state, the current from the capacitors C1 and C2 cannot pass through the capacitor C3 because the capacitor C3 voltage is greater than the capacitor C1 and C2 voltages.Consequently, there is no current flow to S5 and the load is connected to the capacitors C1 and C2 in parallel.This state is the same as the State 3 as shown in Figure 3c, the output voltage equals the boost voltage (Vab = VB).The The output voltage is positive from t 0 to t 7 with corresponding to Stages 1-7.Between t 7 and t 14 , the output voltage is negative, corresponding to Stages 8-14.In the positive period from t 0 to t 7 , the circuit operation includes seven stages and nine states (State 1 to State 9, Figures 3 and 4).
Stage 1 (t 0 -t 1 , Figure 3a-d): When S 1 is switched ON, the inductor L 1 stores energy from the DC source.If T 1 is switched OFF, the output voltage is equal to zero (V ab = 0) as shown in Figure 3a for State 1.If T 1 is switched ON, the output voltage is equal to the boost voltage (V ab = V B ) as shown in Figure 3c for State 3.
When S 1 is switched OFF, the diode D 0 is forward-biased, and the inductor L 1 is discharged to the capacitors C 1 and C 2 .If T 1 is switched OFF, the output voltage is zero (V ab = 0) as shown in Figure 3b for State 2. When T 1 is switched ON, the output voltage equals the boost voltage (V ab = V B ) as shown in Figure 3d for State 4. The operating duty cycle of the boost inductor in this stage is the duty cycle of switch S 1 , d S1 .
Stage 2 (t 1 -t 2 , Figures 3c,d and 4a): The switches S 5 and T 1 are fully switched ON.When S 2 is turned ON, whereas S 1 is switched OFF, the capacitors C 1 and C 2 are working in series supplying power to the load.The capacitor C 3 is charged by C 1 and C 2 through S 5 simultaneously.As shown in Figure 4a for State 5, the load voltage is equal to twice boost voltage (V ab = 2V B ).
When S 2 is switched OFF, while S 1 is switched ON, the inductor L 1 stores energy from V dc .The capacitors C 1 and C 2 are working in parallel to feed the load.Although S 5 is switched ON in this state, the current from the capacitors C 1 and C 2 cannot pass through the capacitor C 3 because the capacitor C 3 voltage is greater than the capacitor C 1 and C 2 voltages.Consequently, there is no current Energies 2019, 12, 394 5 of 14 flow to S 5 and the load is connected to the capacitors C 1 and C 2 in parallel.This state is the same as the State 3 as shown in Figure 3c, the output voltage equals the boost voltage (V ab = V B ).The control signal of S 5 during this stage can be changed in another way, which is similar to the control signal for S 2 .To reduce the switching losses, the control signal of S 5 is always controlled ON during this stage.
Similarly, when S 1 is switched OFF, whereas S 5 is turned ON, the output voltage is equal to the boost voltage (V ab = V B ), which is the same as the State 4 as shown in Figure 3d.
As shown in Figure 2, the duty cycle of S 2 in this stage is gradually increased, while the duty cycle of S 1 is fixed at d S1 .The time interval of Stage 2 is divided into two subintervals.In the first subinterval (t 1 -t 1m , see Figure 5a), the duty cycle of S 1 is greater than that of S 2 .The operating duty cycle of the boost inductor in the first subinterval is d S1 .In the second subinterval (t 1m -t 2 , see Figure 5a), the duty cycle of S 2 is more than that of S 1 .As a result, the operating duty cycle of the boost inductor in the second subinterval depends on the duty cycle of S 2 .The average duty cycle of the boost inductor in this sub-stage can be approximated as The time t 1m is calculated as where f out and A m are the frequency of the output voltage and the peak amplitude of control waveform e x , respectively.
The boost factor of the NLBI is determined as From the analysis of the proposed NLBI in Section 2. The operating duty cycle of the boost inductor is summarized as where The influence of the operating states of S1 and S2 on the duty cycle of the circuit is not the same in each operating state.However, the operation of S1 and S2 is repeated after a quarter cycle of the output cycle.In one-four time interval of the output voltage time period, the average duty cycle of the boost inductor is calculated as where Tout = 1/fout is the period of the output voltage.The voltage gain (G) is expressed as

Inductor and Capacitor Selections
Figure 6 shows the inductor current and capacitor voltage waveforms in the positive output voltage.In Figure 6, the voltage waveforms on capacitors C1 and C2 are the same and equal to VC. Stage 3 (t 2 -t 3 , Figure 4b-d): The switch S 3 is complementary to the switch S 2 .When S 3 is switched ON, the load voltage is equal to three times the boost voltage (V ab = 3V B ).If S 1 is switched ON, the inductor L 1 stores energy from V dc , while the capacitors C 1 and C 2 working in parallel are connected in series to the capacitor C 3 for supplying power to the load as shown in Figure 4c for State 7. When S 1 is switched OFF, the capacitors C 1 and C 2 are charged by the DC voltage source, while the capacitor C 3 is still connected in series with the capacitors C 1 and C 2 as shown in Figure 4d for State 8.
When the switch S 2 is switched ON and the switch S 3 is switched OFF, the inductor L 1 stores energy while the capacitors C 1 and C 2 are in series for supplying power to the load.From Figure 4b for State 6, it can be seen that the output voltage of the inverter equals to twice boost voltage (V ab = 2V B ).
As shown in Figure 2, the duty cycle of S 2 in this stage is gradually decreased, while the duty cycle of S 1 is fixed at d S1 .The time interval of Stage 3 is divided into two subintervals.In the first subinterval (t 2 -t 2m , see Figure 5b), the duty cycle of S 2 is more than that of S 1 .The inductor is almost charged during the first subinterval.Therefore, the operating duty cycle of the boost inductor is 1.
In the second subinterval (t 2m -t 3 , see Figure 5b), the duty cycle of S 1 is greater than that of S 2 .The operating duty cycle of the boost inductor in the second subinterval is total duty cycle of the switches S 1 and S 2 , we have Energies 2019, 12, 394 6 of 14 where d S2 is average duty cycle of the switch S 2 in the second subinterval and calculated approximately as (1).The time t 2m is defined as Stage 4 (t 3 -t 4 , Figure 4c-e): When the switches S 1 , S 2 and S 3 are switched ON, whereas the switch S 5 is switched OFF, the capacitors C 1 , C 2 and C 3 are working in series for supplying power to the load.The load voltage is equal to four times the boost voltage (V ab = 4V B ) as shown in Figure 4e for State 9. Other states in this stage to reach the output voltage at three times boost voltage are the same as those in Stage 3. In the control method as shown in Figure 2, the duty cycle of S 1 is always greater than S 2 in terms of time (t 3 -t 4 ) and (t 10 -t 11 ) so that the calculation becomes simpler.Therefore, the following condition is obtained as The In the negative period from t 7 to t 14 including seven stages and nine states, the switch T 2 is fully switched ON, while T 1 is fully switched OFF.The signal T 3 is obtained by comparing the carrier e 1 and the control waveform e x .The signal T 4 is the opposite.All the remaining switches have the same states as in the positive period.The load voltage of the proposed inverter is summarized in Table 2.

Circuit Analysis of the Proposed Inverter
The circuit analysis is begun with the following assumptions: the capacitors C 1 and C 2 are equal, the capacitance is large enough to the voltage across the capacitor is constant, and the pairs of diodes-capacitors (D 1 -C 1 and D 2 -C 2 ) are symmetrical and balanced.The operating states of the proposed NLBI simplify into two operating modes: charging inductor and discharging inductor.
The charging inductor modes are given in Figure 3a-e.These states are controlled by switch S 1 and S 2 , and the inductor L 1 is charged at this time.
Assuming that the T avg is the average time interval of the charging inductor mode during the period T s , and d avg = T avg /T s is the average duty cycle of the boost inductor in each period T s .When S 1 or S 2 is switched ON, the inductor stores energy as shown in Figure 3a-e for States 1, 3, 5, 6, 7 and 9, respectively.The inductor L 1 voltage is: When both S 1 and S 2 switches are switched OFF, the inductor is discharged as shown in Figure 3b,d and Figure 4d for States 2, 4 and 8, respectively.The average time of this mode is (1 − d avg )T s .The following equations are obtained as Because the average voltage crossing the inductor during a period of T s is zero, from ( 6) and ( 7), the boost voltage is calculated as The boost factor of the NLBI is determined as From the analysis of the proposed NLBI in Section 2. The operating duty cycle of the boost inductor is summarized as where The influence of the operating states of S 1 and S 2 on the duty cycle of the circuit is not the same in each operating state.However, the operation of S 1 and S 2 is repeated after a quarter cycle of the output cycle.In one-four time interval of the output voltage time period, the average duty cycle of the boost inductor is calculated as where T out = 1/f out is the period of the output voltage.The voltage gain (G) is expressed as

Inductor and Capacitor Selections
Figure 6 shows the inductor current and capacitor voltage waveforms in the positive output voltage.In Figure 6, the voltage waveforms on capacitors C 1 and C 2 are the same and equal to V C .Assuming that the output power (POUT) equals the input power, the average input current can be calculated as The current ripple of the inductor is defined as [ ] where The inductance is determined by the current ripple factor KL as The inductance is selected as The capacitance Ci (i = 1, 2 and 3) can be calculated based on the voltage ripple on the capacitors Ci.In this case, the capacitor Ci is determined by the maximum voltage ripple at k% of the maximum voltages of the capacitors.The capacitors C1 and C2 are charged when the switches S1 and S2 are switched OFF.The capacitors C1 and C2 are discharged in the remaining cases of the switches S1 and S2.The capacitor C3 is charged when the switch S5 is switched ON, whereas it is discharged when the switch S5 is switched OFF.
Assuming that the output load has the power factor (cosφ) of 1, the longest discharging term of the capacitor C3 in the proposed NLBI is between t2 and t5 as shown in the Figure 6.The maximum discharge amounts Q3 of the capacitor C3 is: where Io is the amplitude the output current.When the Q3 is less than k% of the maximum charge of C3, the capacitance C3 needs to meet the condition as: Assuming that the output power (P OUT ) equals the input power, the average input current can be calculated as The current ripple of the inductor is defined as where The inductance is determined by the current ripple factor K L as The inductance is selected as The capacitance C i (i = 1, 2 and 3) can be calculated based on the voltage ripple on the capacitors C i .In this case, the capacitor C i is determined by the maximum voltage ripple at k% of the maximum voltages of the capacitors.The capacitors C 1 and C 2 are charged when the switches S 1 and S 2 are switched OFF.The capacitors C 1 and C 2 are discharged in the remaining cases of the switches S 1 and S 2 .The capacitor C 3 is charged when the switch S 5 is switched ON, whereas it is discharged when the switch S 5 is switched OFF.
Assuming that the output load has the power factor (cosϕ) of 1, the longest discharging term of the capacitor C 3 in the proposed NLBI is between t 2 and t 5 as shown in the Figure 6.The maximum discharge amounts Q 3 of the capacitor C 3 is: where I o is the amplitude the output current.When the Q 3 is less than k% of the maximum charge of C 3 , the capacitance C 3 needs to meet the condition as: Energies 2019, 12, 394 9 of 14 The reduction of the capacitor C 1 or C 2 voltages is equal to the incensement of the capacitor C 3 voltage at times t 1 and t 5 as shown in Figure 6.At this time, the charging of capacitor C 3 affects the ripple of capacitors C 1 or C 2 .Because the capacitor C 3 voltage is twice the capacitor C 1 voltage, the ripple of capacitor C 1 will be larger than that of the capacitor C 3 .Therefore, the capacitance of selected capacitors C 1 and C 2 will be greater than or equal to the capacitance of capacitor C 3 .Figure 7 shows the simulation results of the NLBI when A m = 3.4, d S1 = 0.4.Figure 7a shows the nine-level output voltage V ab , the load current i o and the ripple voltage of the capacitors (V C1 , V C2 , V C3 ). Figure 7b shows the voltage waveform of the switches S 1 , S 2 , S 3 , S 5 and the voltage waveform of the H-bridge switches T 1 -T 4 .The capacitor voltages V C1 , V C2 and V C3 are boosted to 65 V from the input voltage of 24 V.The maximum voltage of the switches S 1 and S 2 is 65 V, while the maximum voltage of the switches S 3 and S 5 is 130 V.The maximum voltage on the switches T 1 -T 4 is 260 V. Figure 7c,d show the harmonic spectrum of the output voltage V ab and the load current i o in the frequency domain, respectively.As seen in Figure 7c, the main component appears around the frequency of 15 kHz and 30 kHz.The reduction of the capacitor C1 or C2 voltages is equal to the incensement of the capacitor C3 voltage at times t1 and t5 as shown in Figure 6.At this time, the charging of capacitor C3 affects the ripple of capacitors C1 or C2.Because the capacitor C3 voltage is twice the capacitor C1 voltage, the ripple of capacitor C1 will be larger than that of the capacitor C3.Therefore, the capacitance of selected capacitors C1 and C2 will be greater than or equal to the capacitance of capacitor C3. Figure 7 shows the simulation results of the NLBI when Am = 3.4, dS1 = 0.4.Figure 7a shows the nine-level output voltage Vab, the load current io and the ripple voltage of the capacitors (VC1, VC2, VC3). Figure 7b shows the voltage waveform of the switches S1, S2, S3, S5 and the voltage waveform of the H-bridge switches T1-T4.The capacitor voltages VC1, VC2 and VC3 are boosted to 65 V from the input voltage of 24 V.The maximum voltage of the switches S1 and S2 is 65 V, while the maximum voltage of the switches S3 and S5 is 130 V.The maximum voltage on the switches T1-T4 is 260 V. Figure 7c,d show the harmonic spectrum of the output voltage Vab and the load current io in the frequency domain, respectively.As seen in Figure 7c, the main component appears around the frequency of 15 kHz and 30 kHz.

Experimental Results
A 350 W prototype based on TMS320F28335 DSP was built as shown in Figure 8.The input DC voltage is 24 V.The output voltage is 110 V rms /50 Hz.The specifications of the experiment are given in Table 3.The switches S 1 , S 2 , S 3 and S 4 are 47N60C3 MOSFETs, whereas the other switches are G40N120 IGBTs.Note that the switch S 5 refers to MOSFET.Because the MOSFET without body diode is not available in the laboratory, a G40N60 IGBT without body diode is used in the experiment.
A 350 W prototype based on TMS320F28335 DSP was built as shown in Figure 8.The input DC voltage is 24 V.The output voltage is 110 Vrms/50 Hz.The specifications of the experiment are given in Table 3.The switches S1, S2, S3 and S4 are 47N60C3 MOSFETs, whereas the other switches are G40N120 IGBTs.Note that the switch S5 refers to MOSFET.Because the MOSFET without body diode is not available in the laboratory, a G40N60 IGBT without body diode is used in the experiment.
Figure 9 shows the experimental results of the NLBI when Am = 3.4, dS1 = 0.4.Figure 9a shows the waveforms of the output voltage Vab and the load current io.As shown in Figure 9a, the output voltage has nine levels.As shown in Figure 9b, the capacitors C1, C2 and C3 voltage are boosed to 52.2 V, 52.2 V and 92.5 V from the input voltage of 24 V, respectively.Figure 9c,d show the experiment results of switches S1, S2, S3, S5 voltage and switches T1-T4 voltage of the H-bridge circuit, respectively.Figure 9e,f shows the harmonic spectrum of the output voltage, Vab and harmonic spectrum of output current.
Gate drives TLP250 (Photo-coupler) Figure 9 shows the experimental results of the NLBI when A m = 3.4, d S1 = 0.4.Figure 9a shows the waveforms of the output voltage V ab and the load current i o .As shown in Figure 9a, the output voltage has nine levels.As shown in Figure 9b, the capacitors C 1 , C 2 and C 3 voltage are boosed to 52.2 V, 52.2 V and 92.5 V from the input voltage of 24 V, respectively.Figure 9c,d show the experiment results of switches S 1 , S 2 , S 3 , S 5 voltage and switches T 1 -T 4 voltage of the H-bridge circuit, respectively.Figure 9e,f shows the harmonic spectrum of the output voltage, V ab and harmonic spectrum of output current.Table 4 lists the theoretical, simulation and experimental values of B, VC1, VC2 and VC3 when dS1 = 0.4, Vdc = 24 V, and Am = 3.4.It can be seen from Table 4 that the simulation value is approximately equal to the theoretical value, which shows the correctness of the theoretical analysis.Moreover, the experimental value is less than that of corresponding theoretical value because the power losses are found in the experimental prototype.The voltage on capacitor C3 is not equal to the sum of capacitors C1 and C2 because the discharge time of capacitor C3 is longer associated with the losses on switches S2, S4, S5 when charging capacitor C3.Here "ΔVab" is the percentage change between experiment and simulation versus theory.

Conclusions
In this paper, a nine-level boost inverter which decreases the number of switching elements by switching the capacitor in series and in parallel has been suggested.The main advantage of the NLBI in comparison with the traditional topology is that the number of switches is reduced with using  4 that the simulation value is approximately equal to the theoretical value, which shows the correctness of the theoretical analysis.Moreover, the experimental value is less than that of corresponding theoretical value because the power losses are found in the experimental prototype.The voltage on capacitor C 3 is not equal to the sum of capacitors C 1 and C 2 because the discharge time of capacitor C 3 is longer associated with the losses on switches S 2 , S 4 , S 5 when charging capacitor C 3 .Here "∆V ab " is the percentage change between experiment and simulation versus theory.

Conclusions
In this paper, a nine-level boost inverter which decreases the number of switching elements by switching the capacitor in series and in parallel has been suggested.The main advantage of the NLBI in comparison with the traditional topology is that the number of switches is reduced with using only a single DC voltage source.Therefore, the economic benefits from the proposed inverter come from the size and cost reduction of the inverter system.The output voltage expression and the parameter calculation are presented.Moreover, a control method based on the PWM technique is proposed for the proposed inverter.Finally, the simulation and experimental results of the NLBI are presented to validate its viability, well-performance, and effectiveness of suggested modulation strategy.The proposed inverter is suitable for low-power applications, where a low input voltage from renewable energy sources such as solar cell, fuel cell and battery needs to convert to a single-phase AC source.

Figure 2 .
Figure 2. Modulation method for the proposed single-phase NLBI.

Figure 2 .
Figure 2. Modulation method for the proposed single-phase NLBI.Figure 2. Modulation method for the proposed single-phase NLBI.

Figure 2 .
Figure 2. Modulation method for the proposed single-phase NLBI.Figure 2. Modulation method for the proposed single-phase NLBI.

Figure 3 .
Figure 3. Operation states in the positive output voltage period of the proposed NLBI.(a) State 1, (b) State 2, (c) State 3 and (d) State 4.
for State 1.If T1 is switched ON, the output voltage is equal to the boost voltage (Vab = VB) as shown in Figure 3c for State 3. When S1 is switched OFF, the diode D0 is forward-biased, and the inductor L1 is discharged to the capacitors C1 and C2.If T1 is switched OFF, the output voltage is zero (Vab = 0) as shown in Figure 3b for State 2. When T1 is switched ON, the output voltage equals the boost voltage (Vab = VB) as shown in Figure 3d for State 4. The operating duty cycle of the boost inductor in this stage is the duty cycle of switch S1, dS1.Stage 2 (t1-t2, Figure 3c,d and Figure 4a): The switches S5 and T1 are fully switched ON.When S2 is turned ON, whereas S1 is switched OFF, the capacitors C1 and C2 are working in series supplying power to the load.The capacitor C3 is charged by C1 and C2 through S5 simultaneously.As shown in Figure 4a for State 5, the load voltage is equal to twice boost voltage (Vab = 2VB).
). Stage 1 (t0-t1, Figure3a-d): When S1 is switched ON, the inductor L1 stores energy from the DC source.If T1 is switched OFF, the output voltage is equal to zero (Vab = 0) as shown in Figure3afor State 1.If T1 is switched ON, the output voltage is equal to the boost voltage (Vab = VB) as shown in Figure 3c for State 3. When S1 is switched OFF, the diode D0 is forward-biased, and the inductor L1 is discharged to the capacitors C1 and C2.If T1 is switched OFF, the output voltage is zero (Vab = 0) as shown in Figure 3b for State 2. When T1 is switched ON, the output voltage equals the boost voltage (Vab = VB) as shown in Figure 3d for State 4. The operating duty cycle of the boost inductor in this stage is the duty cycle of switch S1, dS1.Stage 2 (t1-t2, Figure 3c,d and Figure 4a): The switches S5 and T1 are fully switched ON.When S2 is turned ON, whereas S1 is switched OFF, the capacitors C1 and C2 are working in series supplying power to the load.The capacitor C3 is charged by C1 and C2 through S5 simultaneously.As shown in Figure 4a for State 5, the load voltage is equal to twice boost voltage (Vab = 2VB).

Figure 5 .
Figure 5. Operational analysis of switches S1 and S2 in the interval of (a) Stage 2 and (b) Stage 3.

Figure 5 .
Figure 5. Operational analysis of switches S 1 and S 2 in the interval of (a) Stage 2 and (b) Stage 3.

PSIM 9 .
1.1 software was studied to verify the operational principle of NLBI.The input voltage is set at V dc = 24 V and the simulation power is 680 W. The inductor L 1 = 2 mH.The capacitors C 1 = C 2 = C 3 = 2200 µF.The switching frequency is 15 kHz.Connect the resistor R = 36 Ω and use the inductor capacitor (LC) filter L f = 2.5 mH, C f = 1 µF.

PSIM 9 .
1.1 software was studied to verify the operational principle of NLBI.The input voltage is set at Vdc = 24 V and the simulation power is 680 W. The inductor L1 = 2 mH.The capacitors C1 = C2 = C3 = 2200 µF.The switching frequency is 15 kHz.Connect the resistor R = 36 Ω and use the inductor capacitor (LC) filter Lf = 2.5 mH, Cf = 1 µF.

Figure 7 .Figure 7 .
Figure 7. Simulation results of the proposed NLBI when dS1 = 0.4.The waveforms from top to bottom: (a) nine-level output voltage Vab, load current io, capacitors C3-C1 voltage; (b) switches S1, S2, S3, S5 Figure 7. Simulation results of the proposed NLBI when d S1 = 0.4.The waveforms from top to bottom: (a) nine-level output voltage V ab , load current i o , capacitors C 3 -C 1 voltage; (b) switches S 1 , S 2 , S 3 , S 5 voltage and switches T 1 -T 4 voltage of H-bridge circuit, (c) harmonic spectrum of nine-level output voltage and (d) harmonic spectrum of load current.

Figure 9 .
Figure 9. Experimental results of NLBI when A m = 3.4, d S1 = 0.4 and V dc = 24 V.The waveforms from top to bottom: (a) Output voltage V ab , output current i o inverter; (b) capacitors C 3 , C 2 , C 1 voltages; (c) voltage of switches V S1 , V S2 , V S3 , V S5 ; (d) voltage of switches V T1 , V T2 , V T3 , V T4 ; (e) harmonic spectrum of the nine-level output voltage; and (f) harmonic spectrum of output current.Table 4 lists the theoretical, simulation and experimental values of B, V C1 , V C2 and V C3 when d S1 = 0.4, V dc = 24 V, and A m = 3.4.It can be seen from Table4that the simulation value is approximately equal to the theoretical value, which shows the correctness of the theoretical analysis.Moreover, the experimental value is less than that of corresponding theoretical value because the power losses are found in the experimental prototype.The voltage on capacitor C 3 is not equal to the sum of capacitors C 1 and C 2 because the discharge time of capacitor C 3 is longer associated with the losses on switches S 2 , S 4 , S 5 when charging capacitor C 3 .

Table 1 .
Advantages and disadvantages of multilevel inverters with reduced switch count.
S1 is switched ON.When the switch S1 is switched OFF, two capacitors C1 and C2 are charging by the diodes D1 and D2.In the SC circuit, the capacitor C3 is charged through the body diode of switch S4 when the switch S5 is switched ON and the switch S3 is switched OFF.When the switch S3 is switched ON and the switch S5 is switched OFF, the capacitor C3 is discharged.
S1 is switched ON.When the switch S1 is switched OFF, two capacitors C1 and C2 are charging by the diodes D1 and D2.In the SC circuit, the capacitor C3 is charged through the body diode of switch S4 when the switch S5 is switched ON and the switch S3 is switched OFF.When the switch S3 is switched ON and the switch S5 is switched OFF, the capacitor C3 is discharged.
operating duty cycle of the boost inductor in Stage 4 is d S1 .

Table 2 .
Different Switching, Capacitor, and Inductor States of the Proposed NLBI.

Table 3 .
Operating Parameters for the Proposed Inverter.

Table 3 .
Operating Parameters for the Proposed Inverter.

Table 4 .
Comparison between Calculated, Simulated and Experimental Values.

Table 4 .
Comparison between Calculated, Simulated and Experimental Values.