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Sensors 2016, 16(12), 2084;

A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search

Department of Computer Science and Information Engineering, National Taiwan Normal University, Taipei 117, Taiwan
These authors contributed equally to this work.
Author to whom correspondence should be addressed.
Academic Editors: Andrew J. Mason, Haitao Li and Yuning Yang
Received: 3 October 2016 / Revised: 10 November 2016 / Accepted: 2 December 2016 / Published: 7 December 2016
(This article belongs to the Special Issue Integrated Sensor Arrays and Array Signal Processing)
Full-Text   |   PDF [5360 KB, uploaded 7 December 2016]   |  


The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO). The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy. View Full-Text
Keywords: spike sorting; VLSI; brain machine interface spike sorting; VLSI; brain machine interface

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Chang, Y.-J.; Hwang, W.-J.; Chen, C.-C. A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search. Sensors 2016, 16, 2084.

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