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10 pages, 2618 KB

Open AccessEditor’s ChoiceArticle

Effects of Carrier Trapping and Noise in Triangular-Shaped GaN Nanowire Wrap-Gate Transistor

by Siva Pratap Reddy Mallem, Peddathimula Puneetha, Yeojin Choi, Mikiyas Mekete Mesheha, Manal Zafer, Kab-Seok Kang, Dong-Yeon Lee, Jaesool Shim, Ki-Sik Im and Sung Jin An

Nanomaterials 2025, 15(17), 1336; https://doi.org/10.3390/nano15171336 - 30 Aug 2025

Viewed by 1010

Abstract

The most widely used nanowire channel architecture for creating state-of-the-art high-performance transistors is the nanowire wrap-gate transistor, which offers low power consumption, high carrier mobility, large electrostatic control, and high-speed switching. The frequency-dependent capacitance and conductance measurements of triangular-shaped GaN nanowire wrap-gate transistors are measured in the frequency range of 1 kHz–1 MHz at room temperature to investigate carrier trapping effects in the core and at the surface. The performance of such a low-dimensional device is greatly influenced by its surface traps. With increasing applied frequency, the calculated trap density promptly decreases, from 1.01 × 10¹³ cm⁻² eV⁻¹ at 1 kHz to 8.56 × 10¹² cm⁻²eV⁻¹ at 1 MHz, respectively. The 1/f-noise features show that the noise spectral density rises with applied gate bias and shows 1/f-noise behavior in the accumulation regime. The fabricated device is controlled by 1/f-noise at lower frequencies and 1/f²-noise at frequencies greater than ~ 0.2 kHz in the surface depletion regime. Further generation–recombination (G-R) is responsible for the 1/f²-noise characteristics. This process is primarily brought on by electron trapping and detrapping via deep traps situated on the nanowire’s surface depletion regime. When the device works in the deep-subthreshold regime, the cut-off frequency for the 1/f²-noise characteristics further drops to a lower frequency of 30 Hz–10⁴ Hz. Full article

(This article belongs to the Section Nanophotonics Materials and Devices)

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8 pages, 1488 KB

Open AccessEditor’s ChoiceArticle

Wrapping Amorphous Indium-Gallium-Zinc-Oxide Transistors with High Current Density

by Jiaxin Liu, Shan Huang, Zhenyuan Xiao, Ning Li, Jaekyun Kim, Jidong Jin and Jiawei Zhang

Electron. Mater. 2025, 6(1), 2; https://doi.org/10.3390/electronicmat6010002 - 23 Jan 2025

Cited by 2 | Viewed by 4048

Abstract

Amorphous oxide semiconductor transistors with a high current density output are highly desirable for large-area electronics. In this study, wrapping amorphous indium-gallium-zinc-oxide (a-IGZO) transistors are proposed to enhance the current density output relative to a-IGZO source-gated transistors (SGTs). Device performances are analyzed using technology computer-aided design (TCAD) simulations. The TCAD simulation results reveal that, with an optimized device structure, the current density of the wrapping a-IGZO transistor can reach 7.34 μA/μm, representing an approximate two-fold enhancement compared to that of the a-IGZO SGT. Furthermore, the optimized wrapping a-IGZO transistor exhibits clear flat saturation and pinch-off behavior. The proposed wrapping a-IGZO transistors show significant potential for applications in large-area electronics. Full article

(This article belongs to the Special Issue Metal Oxide Semiconductors for Electronic Applications)

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26 pages, 7311 KB

Open AccessArticle

Reducing Off-State and Leakage Currents by Dielectric Permittivity-Graded Stacked Gate Oxides on Trigate FinFETs: A TCAD Study

by Alper Ülkü, Esin Uçar, Ramis Berkay Serin, Rifat Kaçar, Murat Artuç, Ebru Menşur and Ahmet Yavuz Oral

Micromachines 2024, 15(6), 726; https://doi.org/10.3390/mi15060726 - 30 May 2024

Cited by 2 | Viewed by 2453

Abstract

Since its invention in the 1960s, one of the most significant evolutions of metal-oxide semiconductor field effect transistors (MOSFETs) would be the 3D version that makes the semiconducting channel vertically wrapped by conformal gate electrodes, also recognized as FinFET. During recent decades, the width of fin (W_fin) and the neighboring gate oxide width (t_ox) in FinFETs has shrunk from about 150 nm to a few nanometers. However, both widths seem to have been leveling off in recent years, owing to the limitation of lithography precision. Here, we show that by adapting the Penn model and Maxwell–Garnett mixing formula for a dielectric constant (κ) calculation for nanolaminate structures, FinFETs with two- and three-stage κ-graded stacked combinations of gate dielectrics with SiO₂, Si₃N₄, Al₂O₃, HfO₂, La₂O₃, and TiO₂ perform better against the same structures with their single-layer dielectrics counterparts. Based on this, FinFETs simulated with κ-graded gate oxides achieved an off-state drain current (I_OFF) reduced down to 6.45 × 10⁻¹⁵ A for the Al₂O₃: TiO₂ combination and a gate leakage current (I_G) reaching down to 2.04 × 10⁻¹¹ A for the Al₂O₃: HfO₂: La₂O₃ combination. While our findings push the individual dielectric laminates to the sub 1 nm limit, the effects of dielectric permittivity matching and κ-grading for gate oxides remain to have the potential to shed light on the next generation of nanoelectronics for higher integration and lower power consumption opportunities. Full article

(This article belongs to the Special Issue Multifunctional-Nanomaterials-Based Semiconductor Devices and Sensors)

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9 pages, 1784 KB

Open AccessCommunication

Barrier Height, Ideality Factor and Role of Inhomogeneities at the AlGaN/GaN Interface in GaN Nanowire Wrap-Gate Transistor

by Siva Pratap Reddy Mallem, Peddathimula Puneetha, Yeojin Choi, Seung Mun Baek, Dong-Yeon Lee, Ki-Sik Im and Sung Jin An

Nanomaterials 2023, 13(24), 3159; https://doi.org/10.3390/nano13243159 - 17 Dec 2023

Cited by 5 | Viewed by 2157

Abstract

It is essential to understand the barrier height, ideality factor, and role of inhomogeneities at the metal/semiconductor interfaces in nanowires for the development of next generation nanoscale devices. Here, we investigate the drain current (I_ds)–gate voltage (V_gs) characteristics of GaN nanowire wrap-gate transistors (WGTs) for various gate potentials in the wide temperature range of 130–310 K. An anomalous reduction in the experimental barrier height and rise in the ideality factor with reducing the temperature have been perceived. It is noteworthy that the variations in barrier height and ideality factor are attributed to the spatial barrier inhomogeneities at the AlGaN/GaN interface in the GaN nanowire WGTs by assuming a double Gaussian distribution of barrier heights at 310–190 K (distribution 1) and 190–130 K (distribution 2). The standard deviation for distribution 2 is lower than that of distribution 1, which suggests that distribution 2 reflects more homogeneity at the AlGaN/GaN interface in the transistor’s source/drain regions than distribution 1. Full article

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9 pages, 2164 KB

Open AccessCommunication

Carrier Trap and Their Effects on the Surface and Core of AlGaN/GaN Nanowire Wrap-Gate Transistor

by Siva Pratap Reddy Mallem, Peddathimula Puneetha, Dong-Yeon Lee, Yoonkap Kim, Han-Jung Kim, Ki-Sik Im and Sung-Jin An

Nanomaterials 2023, 13(14), 2132; https://doi.org/10.3390/nano13142132 - 22 Jul 2023

Cited by 2 | Viewed by 1876

Abstract

We used capacitance–voltage (C–V), conductance–voltage (G–V), and noise measurements to examine the carrier trap mechanisms at the surface/core of an AlGaN/GaN nanowire wrap-gate transistor (WGT). When the frequency is increased, the predicted surface trap density promptly drops, with values ranging from 9.1 × 10¹³ eV⁻¹∙cm⁻² at 1 kHz to 1.2 × 10¹¹ eV⁻¹∙cm⁻² at 1 MHz. The power spectral density exhibits 1/f-noise behavior in the barrier accumulation area and rises with gate bias, according to the 1/f-noise features. At lower frequencies, the device exhibits 1/f-noise behavior, while beyond 1 kHz, it exhibits 1/f²-noise behavior. Additionally, when the fabricated device governs in the deep-subthreshold regime, the cutoff frequency for the 1/f²-noise features moves to the subordinated frequency (~10² Hz) side. Full article

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8 pages, 1576 KB

Open AccessCommunication

Temperature-Dependent Carrier Transport in GaN Nanowire Wrap-Gate Transistor

by Siva Pratap Reddy Mallem, Peddathimula Puneetha, Yeojin Choi, Seung Mun Baek, Sung Jin An and Ki-Sik Im

Nanomaterials 2023, 13(10), 1629; https://doi.org/10.3390/nano13101629 - 12 May 2023

Cited by 5 | Viewed by 1993

Abstract

For the creation of next-generation nanoscale devices, it is crucial to comprehend the carrier transport mechanisms in nanowires. Here, we examine how temperature affects the properties of GaN nanowire wrap-gate transistors (WGTs), which are made via a top-down technique. The predicted conductance in this transistor remains essentially unaltered up to a temperature of 240 K and then increases after that as the temperature rises. This is true for increasing temperature at gate voltages less than threshold voltage (V_gs < V_th). Sharp fluctuations happen when the temperature rises with a gate voltage of V_th < V_gs < V_FB. The conductance steadily decreases with increasing temperature after increasing the gate bias to V_gs > V_FB. These phenomena are possibly attributed to phonon and impurity scattering processes occurring on the surface or core of GaN nanowires. Full article

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11 pages, 1601 KB

Open AccessCommunication

Comparison of Fitting Current–Voltage Characteristics Curves of FinFET Transistors with Various Fixed Parameters

by Hsin-Chia Yang, Sung-Ching Chi and Wen-Shiang Liao

Appl. Sci. 2022, 12(20), 10519; https://doi.org/10.3390/app122010519 - 18 Oct 2022

Cited by 7 | Viewed by 3392

Abstract

In the deep submicron regime, FinFET successfully suppresses the leakage current using a 3D fin-like channel substrate, which gets depleted and blocks possible leakage as the gate is applied with a bias wholly wrapping the channel. Fortunately, a scanning photo-lithography using extensive ultraviolet (EUV) and multi-mask task carefully resolves critical dimension issues. The ensuing anisotropic plasma dry etching is somehow a subsequent challenging process, which consumes the edge of original ‘I’-shape epitaxial silicon and causes dimension loss, and thus produces fin-like bodies as prepared channels. In order to protect the transistors from malfunction due to dimension over-etching, fin width is taken to be 120 nanometers, while the channel lengths vary. The prepared transistors are measured and characteristic curves are fitted for analysis. Measured current versus voltage characteristic curves are fitted with three parameters (transistor geometry constant, threshold voltage, and Early voltage) in the conventional current-voltage formula, which are allowed to vary as the short channel effects or process-related issues are taken into account. In this paper, one of the three is deliberately set to be fixed for a transistor, and the others are freely chosen and determined to reach minimum variation. Various conclusions through comparisons and analysis may give important feasible applications in the future. Full article

(This article belongs to the Section Nanotechnology and Applied Nanosciences)

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