Search Results (61)

Incremental energy demand, environmental constraints, restrictions in the availability of energy resources, economic conditions, and political impact prompt the power sector toward deregulation. In addition to these impediments, electric power competition for power quality, reliability, availability, and cost forces utilities to maximize utilization of the existing infrastructure by flowing power on transmission lines near to their thermal limits. All these factors introduce problems related to power network stability, reliability, quality, congestion management, and security in restructured power systems. To overcome these problems, power-electronics-based FACTS devices are one of the beneficial solutions at present. In this review paper, the significant role of FACTS devices in restructured power networks and their technical benefits against various power system problems such as load frequency control, voltage stability, and congestion management will be presented. In addition, an extensive discussion about the comparison between different FACTS devices (series, shunt, and their combination) and comparison between various optimization techniques (classical, analytical, hybrid, and meta-heuristics) that support FACTS devices to achieve their respective benefits is presented in this paper. Generally, it is concluded that third-generation FACTS controllers are more popular to mitigate various power system problems (i.e., load frequency control, voltage stability, and congestion management). Moreover, a combination of multiple FACTS devices, with or without energy storage devices, is more beneficial compared to their individual usage. However, this is not commonly adopted in small power systems due to high installation or maintenance costs. Therefore, there is a trade-off between the selection and cost of FACTS devices to minimize the power system problems. Likewise, meta-heuristics and hybrid optimization techniques are commonly adopted to optimize FACTS devices due to their fast convergence, robustness, higher accuracy, and flexibility. Full article

This paper presents a wideband low-power/low-voltage 60-GHz low-noise amplifier (LNA) in a 28-nm bulk CMOS technology. The LNA has been designed for high-speed millimeter-wave (mm-wave) communications. It consists of two pseudo-differential amplifying stages and a buffer stage included for 50-Ohm on-wafer measurements. Two integrated input/output baluns guarantee both simultaneous 50-ohm input–noise/output matching at input/output radio frequency (RF) pads. A power-efficient design strategy is adopted to make the LNA suitable for low-power applications, while minimizing the noise figure (NF). Thanks to the adopted design strategy, the post-layout simulation results show an excellent trade-off between power gain and 3-dB bandwidth (BW_3dB) with 13.5 dB and 7 GHz centered at 60 GHz, respectively. The proposed LNA consumes only 11.6 mA from a 0.9-V supply voltage with an NF of 8.4 dB at 60 GHz, including the input transformer loss. The input 1 dB compression point (IP_1dB) of −15 dBm at 60 GHz confirms the first-rate linearity of the proposed amplifier. Human body model (HBM) electrostatic discharge (ESD) protection is guaranteed up to 2 kV at the RF input/output pads thanks to the input/output integrated transformers. Full article

The recent advancements in high-frequency, high-power switching devices require the development of non-invasive, cost-effective sensors for signal diagnostics. In this context, planar sensors have emerged as promising candidates for voltage and current sensing due to their compatibility with printed circuit boards (PCBs). However, previously proposed voltage planar sensors exhibit trade-offs between high bandwidths and responsivity, limiting their usage to sub-GHz applications. This study introduces a planar voltage sensor that leverages geometric optimization using software-assisted design to enhance bandwidth without compromising sensitivity. The optimized sensors demonstrate an extended bandwidth response up to 4 GHz and accurate recovery of fast transient signals validated through experimental measurements, which represents a significant step forward in broadband sensing for high-power applications. Full article

The increasing integration of renewable energy, electric vehicles, and industrial applications demands efficient power converter control strategies that reduce switching losses while maintaining high waveform quality. This paper presents a Finite-Control-Set Model Predictive Control (FCS-MPC) strategy for three-phase, two-level voltage source inverters (VSIs), incorporating a secondary objective for switching frequency minimization. Unlike conventional MPC approaches, the proposed method optimally balances control performance and efficiency trade-offs by adjusting the weighting factor (${\lambda }_{min}$). Real-time implementation using the OPAL-RT platform validates the effectiveness of the approach under both linear and non-linear load conditions. Results demonstrate a significant reduction in switching losses, accompanied by improved waveform tracking; however, trade-offs in distortion are observed under non-linear load scenarios. These findings provide insights into the practical implementation of real-time predictive control strategies for high-performance power converters. Full article

This work presents a current-controlled CMOS ring oscillator (CCRO) optimized for ultra-low-voltage applications in next-generation energy-constrained systems. Leveraging bulk voltage tuning in 22 nm FDSOI differential inverter stages, the topology enables frequency adjustment while operating MOSFETs in the subthreshold region—critical for minimizing power in sub-1 V environments. Simulations at 0.4 V supply demonstrate robust performance: a three-stage oscillator achieves a 537–800 MHz tuning range with bias current (I_BIAS) modulation from 30–130 nA, while a four-stage configuration spans 388–587 MHz. At 70 nA I_BIAS, the three-stage design delivers a nominal frequency of 666.8 MHz with just 10.23 µW power dissipation, underscoring its suitability for ultra-low-power IoT and biomedical applications. The oscillator’s linear frequency sensitivity (2.63 MHz/nA) allows precise, dynamic control over performance–power tradeoffs. To address diverse application needs, the design integrates three tunability mechanisms: programmable capacitor arrays for coarse frequency adjustments, configurable stage counts (three- or four-stage topologies), and supply voltage scaling. This multi-modal approach extends the operational range to 1 MHz–1 GHz, ensuring compatibility with low-speed sensor interfaces and high-speed edge-computing tasks. The CCRO’s subthreshold operation at 0.4 V—coupled with nanoampere-level current consumption—makes it uniquely suited for battery-less systems, wearable health monitors, and implantable medical devices where energy efficiency and adaptive clocking are paramount. By eliminating traditional voltage-controlled oscillators’ complexity, this topology offers a compact, scalable solution for emerging ultra-low-power technologies. Full article

One of the most important challenges in modern digital systems, especially regarding autonomous embedded systems, is energy efficiency. This work studies an energy consumption optimization approach on a microcontroller that implements IoT-like applications, featuring Dynamic Voltage and Frequency Scaling (DVFS) capabilities, by dynamically changing the supply voltage and clock frequency. The proposed approach categorizes tasks according to their demands on timing requirements and analyzes speed–energy efficiency trade-offs. Results strongly indicate that energy performance is improved due to the proper adjustment of configurations towards required tasks. The findings are verified within a set of scenarios that highlight the potential balance between energy economy and operational demands for specialized IoT contexts. Full article

Recent advancements in Electrowetting on Dielectric (EWOD) systems, such as simplified fabrication, low-voltage actuation, and the development of more reliable materials, are expanding the potential applications of electrowetting actuators. One application of EWOD actuators is in RF devices to enable dynamic reconfiguration and allow real-time adjustments to frequency and bandwidth. In this paper, a method is introduced to actuate a panel using EWOD forces. In the EWOD system, the velocity of the plate increases by maximizing the actuation force, minimizing the moving mass (droplets and metalized plate), and reducing resistance (contact line drag, fluid drag). However, some of these are competing factors. For instance, the actuation force can be increased by increasing the number of droplets, but this also increases the inertia and the drag force. An analytical model of EWOD actuation is presented to understand system performance tradeoffs. The model is validated with an EWOD experiment, and the data demonstrate less than a 7.8% error between the measured and predicted maximum plate velocities for different voltage inputs. In addition, this study presents a 3D numerical FEM model to analyze the velocity profile and viscous force in the thin droplets, focusing on variations along the droplet’s height, which cannot be captured experimentally. The main advantage of the proposed system over previous works is the simple 2D manufacturing process, which allows embedding metalized plates and RF circuit boards, in addition to being compact, portable, and low-cost. In addition, the proposed method does not have any mechanical components, which can increase the system’s reliability in a harsh environment. Full article

This paper presents a low-power 60 GHz low-noise amplifier (LNA) designed for Gbit/s applications using 28 nm CMOS technology. The LNA exploits a single-stage pseudo-differential architecture with integrated input transformer for both electrostatic discharge (ESD) protection and simultaneous noise/impedance matching. An effective power-constrained design strategy is adopted to pursue the lowest current consumption at the minimum noise figure (NF), with the best tradeoff between gain and frequency bandwidth. The LNA, which has been designed to drive an on–off keying (OOK) demodulator, is operated at a supply voltage as low as 0.9 V and achieves a voltage gain of about 21 dB with a 3 dB bandwidth of 2 GHz around 60 GHz. Thanks to the proper impedance transformation at the 60 GHz input, the amplifier exhibits an NF of 6.3 dB, also including the input transformer loss with a very low power consumption of about 5 mW. The adoption of a single-stage topology also allows an excellent input 1 dB compression point (IP_1dB) of −4.7 dBm. The input transformer guarantees up to 2 kV human body model (HBM) ESD protection. Full article

Global efforts aiming to shift towards renewable energy and smart grid configurations require accurate unit commitment schedules to guarantee power balance and ensure feasible operation under different complex constraints. Intelligent systems utilizing hybrid and high-level techniques have arisen as promising solutions to provide optimum exploration–exploitation trade-offs at the expense of computational complexity. To ameliorate this requirement, which is extremely expensive in non-interconnected renewable systems, radically different approaches based on enhanced priority schemes and Boolean encoding/decoding have to take place. This compilation encompasses various mappings that convert multi-valued clausal forms into Boolean expressions with equivalent satisfiability. Avoiding any need to introduce prior parameter settings, the solution utilizes state-of-the-art advancements in the field of artificial intelligence models, namely Boolean mapping. It allows for the efficient identification of the optimal configuration of a non-convex system with binary and discontinuous dynamics in the fewest possible trials, providing impressive performance. In this way, Boolean mapping becomes capable of providing global optimum solutions to unit commitment utilizing fully tractable procedures without deteriorating the computational time. The results, considering a non-interconnected power system, show that the proposed model based on artificial intelligence presents advantageous performance in terms of generating cost and complexity. This is particularly important in isolated networks, where even a-not-so great deviation between production and consumption may reflect as a major disturbance in terms of frequency and voltage. Full article

This paper proposes an adaptive acceleration lock compensation technology for phase-locked loops (PLLs) based on a novel dual-mode programmable ring voltage-controlled oscillator (ring-VCO). In addition, a time-to-digital converter (TDC) is designed to accurately quantify the phase difference from the phase frequency detector (PFD) in order to optimize the dead-zone effect while dynamically switching an auxiliary charge pump (CP) module to realize fast phase locking. Furthermore, a TDC-controlled three/five-stage dual-mode adaptively continuously switched VCO is proposed to optimize the phase noise (PN) and power efficiency, leading to an optimal performance tradeoff of the PLL. Based on the 180 nm/1.8 V standard CMOS technology, the complete PLL design and a corresponding simulation analysis are implemented. The results show that, with a 1 GHz reference signal as the input, the output frequency is 50–324 MHz, with a wide tuning range of 260 MHz and a low phase noise of −98.07 dBc/Hz@1 MHz. The key phase-locking time is reduced to 1.11 μs, and the power dissipation is lowered to 1.86 mW with a layout area of 66 μm × 128 μm. A significantly remarkable multiobjective performance tradeoff with topology optimization is realized, which is in contrast to several similar design cases of PLLs. Full article

This study investigates the operational characteristics of AlGaN/GaN high-electron-mobility transistors (HEMTs) by employing various passivation materials with different dielectric constants and passivation structures. To ensure the simulation reliability, the parameters were calibrated based on the measured data from the fabricated basic Si₃N₄ passivation structure of the HEMT. The Si₃N₄ passivation material was replaced with high-k materials, such as Al₂O₃ and HfO₂, to improve the breakdown voltage. The Al₂O₃ and HfO₂ passivation structures achieved breakdown voltage improvements of 6.62% and 17.45%, respectively, compared to the basic Si₃N₄ passivation structure. However, the increased parasitic capacitances reduced the cut-off frequency. To mitigate this reduction, the operational characteristics of hybrid and partial passivation structures were analyzed. Compared with the HfO₂ passivation structure, the HfO₂ partial passivation structure exhibited a 7.6% reduction in breakdown voltage but a substantial 82.76% increase in cut-off frequency. In addition, the HfO₂ partial passivation structure exhibited the highest Johnson’s figure of merit. Consequently, considering the trade-off relationship between breakdown voltage and frequency characteristics, the HfO₂ partial passivation structure emerged as a promising candidate for high-power and high-frequency AlGaN/GaN HEMT applications. Full article

Inductive power transfer (IPT) systems often encounter limitations in efficiency and transmission distance due to near-field magnetic coupling characteristics. Increasing the inductance can enhance the transmission distance, but it also raises the system’s Q factor, leading to several issues. This study aimed to optimize the magnetic core design of helical coils to enhance magnetic coupling in IPT systems while minimizing the increase in self-inductance. Through finite element analysis, various core placements were evaluated, leading to a proposed core design process that integrates inner and lower cores at optimal angles. The proposed design was compared with conventional cores, and its performance was validated in an IPT system. The results demonstrate that the proposed core design significantly enhances the coupling coefficient (k) and extends power transmission distance compared with conventional planar and U-shaped core structures without substantially increasing self-inductance (L). This design effectively balances the trade-off between increasing inductance and maintaining system stability, thereby improving transmission efficiency while minimizing frequency instability and voltage stress. Full article

The seafloor E-field signal is extremely weak and difficult to measured, even with a high signal-to-noise ratio. The preamplifier for electrodes is a key technology for ocean-bottom electromagnetic receivers. In this study, a chopper amplifier was proposed and developed to measure the seafloor E-field signal in the nanovolt to millivolt range at significantly low frequencies. It included a modulator, transformer, AC amplifier, high-impedance (hi-Z) module, demodulator, low-pass filter, and chopper clock generator. The injected charge in complementary metal-oxide semiconductor (CMOS) switches that form the modulator is the main source of 1/f noise. Combined with the principles of peak filtering and dead bands, a hi-Z module was designed to effectively reduce low-frequency noise. The chopper amplifier achieved an ultralow voltage noise of 0.6 nV/rt (Hz) at 1 Hz and 1.2 nV/rt (Hz) at 0.001 Hz. The corner frequency was less than 100 mHz, and there were few 1/f noises in the effective observation frequency band used for detecting electric fields. Each component is described with relevant tradeoffs that realize low noise in the low-frequency range. The amplifier was compact, measuring Ø 68 mm × H 12 mm, and had a low power consumption of approximately 23 mW (two channels). The fixed gain was 1500 with an input voltage range of 2.7 mV_PP. The chopper amplifiers demonstrated stable performance in offshore geophysical prospecting applications. Full article

This paper presents the design of a low-noise amplifier (LNA) with a bypass mode for the n77/79 bands in 5G New Radio (NR). The proposed LNA integrates internal matching networks for both input and output, combining two LNAs for the n77 and n79 bands into a single chip. Additionally, a bypass mode is integrated to accommodate the flexible operation of the receiving system in response to varying input signal levels. For each frequency band, we designed a low-noise amplifier for the n77 band to expand the bandwidth to 900 MHz (3.3 GHz to 4.2 GHz) using resistive–capacitance (RC) feedback and series inductive-peaking techniques. For the n79 band, only the RC feedback technique was employed to optimize the performance of the LNA for its 600 MHz bandwidth (4.4 GHz to 5.0 GHz). Because wideband techniques can lead to a trade-off between gain and noise, causing potential degradation in noise performance, appropriate bandwidth design becomes crucial. The designed n77 band low-noise amplifier achieved a simulated gain of 22.6 dB and a noise figure of 1.7 dB. Similarly, the n79 band exhibited a gain of 21.1 dB and a noise figure of 1.5 dB with a current consumption of 10 mA at a 1.2 supply voltage. The bypass mode was designed with S₂₁ of −3.7 dB and −5.0 dB for n77 and n79, respectively. Full article

This paper presents a low-voltage CMOS four-stage amplifier operating in the subthreshold region. The first design technique includes the cross-feedforward positive feedback frequency compensation (CFPFC) for obtaining better bandwidth efficiency in a low-voltage multi-stage amplifier. The second design technique incorporates both the bulk-drain-driven input stage topology in conjunction with a low-voltage attenuator to permit operation at a low voltage, and improves the input common-mode range (ICMR). The proposed circuit is implemented using TSMC-40 nm process technology. It consumes 0.866 μW at a supply voltage of 0.5 V. With a capacitive load of 50 pF, this four-stage amplifier can achieve 84.59 dB in gain, 161.00 kHz in unity-gain bandwidth, 96 deg in phase margin, and 5.7 dB in gain margin whilst offering an input-referred noise of 213.63 $\mathrm{n}\mathrm{V}/\sqrt{\mathrm{H}\mathrm{z}}$ @1 kHz, small-signal power-bandwidth FoM_ss of 9.31 (MHz∙pF/μW), and noise-power per bandwidth-based FoM_npb of 1.15 × 10⁻⁶ (($\mathrm{\mu }\mathrm{V}/\sqrt{\mathrm{H}\mathrm{z}}$)·µW/Hz). Compared to the conventional bulk-driven input stage design technique, it offers improved multi-parameter performance metrics in terms of noise, power, and bandwidth at a compromising tradeoff on ICMR with respect to bulk-driven amplifier design. Compared with conventional gate-source input stage design, it offers improved ICMR. The amplifier is useful for low-voltage analog signal-processing applications. Full article