Search Results (47)

This study examined the correlation between the number of delay flip-flops (D-FFs) connected after each ring oscillator (RO) and the bit distribution of random number sequences in an RO-based random number generator (RNG). In our previous research, unstable input signals to the XOR gate contributed to differences in bit distribution. Based on these results, we simulated how combining signals with biased distributions through XOR gates affects the overall bit distribution. Beyond this, we also conducted simulations where the inputs to the XOR gate included not just {0, 1} signals, but also three-state signals incorporating metastable states. We then proposed using multi-D-FFs as synchronization circuits for RO signals and performed analyses on RO-based RNG implementations by estimating metastable output conditions and conducting NIST Special Publication 800-22 tests regarding bit distributions. These results confirm that inserting two or more D-FFs after RO signals improves the bit distribution of RO-based RNG implementations. Full article

Traditional cryptographic systems face critical vulnerabilities posed by the rapid advancement of quantum computing, particularly concerning key exchange mechanisms and the quality of entropy sources for random number generation. To address these challenges, this paper proposes a multi-layered, quantum-resistant hybrid cryptographic architecture. First, to ensure robust data confidentiality and secure key establishment, the architecture employs AES-256 (Advanced Encryption Standard-256) for data encryption and utilizes the Kyber Key Encapsulation Mechanism (KEM), which is based on the Learning With Errors (LWE) problem, for secure key exchange. Second, to further bolster overall security by establishing a high-quality cryptographic foundation, we design a TRNG (true random number generator) system based on a multi-level Ring Oscillator (RO) architecture (employing 5, 7, 9, and 11 inverter stages), which provides a reliable and high-quality entropy source. Third, to enable intelligent and adaptive security management, we introduce FA-Kyber (Flow-Adaptive Kyber), a dual-trigger key exchange framework facilitating dynamic key management strategies. Experimental evaluations demonstrate that our implementation exhibits robust performance, achieving an encrypted data transmission throughput of over 550 Mbps with an average end-to-end latency of only 3.14 ms and a key exchange success rate of 99.99% under various network conditions. The system exhibits excellent stability under network congestion, maintaining 86% of baseline throughput under moderate stress, while adaptively increasing the key rotation frequency to enhance security. This comprehensive approach strikes an optimal balance between performance and post-quantum resilience for sensitive communications. Full article

The Ring Oscillator Physical Unclonable Function (RO-PUF) is a hardware security innovation that creates a secure and distinct identifier by utilizing the special physical properties of ring oscillators. Their unique response, low hardware overhead, and difficulty of reproduction are some of the security benefits that make them valuable in safe authentication systems. Numerous developments, such as temperature adjustment methods, aging mitigation, and better architecture and layout, have been created to increase its security, dependability, and efficiency. However, achieving the sacrifice metric makes it challenging to implement with additional complex circuits. This work focuses on stability improvement in terms of the reliability of the RO-PUF in enhanced challenge and response (CRP) by exploiting existing on-chip hard processors. This work establishes only ROs and their counters inside the chip. The built-in microprocessor performs the remaining process using the intermediary process of a Q factor and new frequency mapping. As a result, the reliability improves significantly to 95.8% compared to previous methods. The proper use of resources due to the limitation of on-chip resources has been emphasized by considering that a hard processor exists inside the new FPGA chip. Full article

This work presents a current-controlled CMOS ring oscillator (CCRO) optimized for ultra-low-voltage applications in next-generation energy-constrained systems. Leveraging bulk voltage tuning in 22 nm FDSOI differential inverter stages, the topology enables frequency adjustment while operating MOSFETs in the subthreshold region—critical for minimizing power in sub-1 V environments. Simulations at 0.4 V supply demonstrate robust performance: a three-stage oscillator achieves a 537–800 MHz tuning range with bias current (I_BIAS) modulation from 30–130 nA, while a four-stage configuration spans 388–587 MHz. At 70 nA I_BIAS, the three-stage design delivers a nominal frequency of 666.8 MHz with just 10.23 µW power dissipation, underscoring its suitability for ultra-low-power IoT and biomedical applications. The oscillator’s linear frequency sensitivity (2.63 MHz/nA) allows precise, dynamic control over performance–power tradeoffs. To address diverse application needs, the design integrates three tunability mechanisms: programmable capacitor arrays for coarse frequency adjustments, configurable stage counts (three- or four-stage topologies), and supply voltage scaling. This multi-modal approach extends the operational range to 1 MHz–1 GHz, ensuring compatibility with low-speed sensor interfaces and high-speed edge-computing tasks. The CCRO’s subthreshold operation at 0.4 V—coupled with nanoampere-level current consumption—makes it uniquely suited for battery-less systems, wearable health monitors, and implantable medical devices where energy efficiency and adaptive clocking are paramount. By eliminating traditional voltage-controlled oscillators’ complexity, this topology offers a compact, scalable solution for emerging ultra-low-power technologies. Full article

In this paper, a novel approach to symbolic regression using Kolmogorov–Arnold Networks (KAN) for developing gray-box Simulation Program with Integrated Circuit Emphasis models of generic transistors is proposed. Unlike traditional black-box models, such as artificial neural networks, (ANN), the developed KAN-based model enhances interpretability by generating explicit mathematical expressions while maintaining high accuracy in device modeling. By combining the computational efficiency of neural network approaches with the transparency of formula-based modeling, the SPICE model generation is significantly accelerated, thereby improving the efficiency of the design technology co-optimization (DTCO) process. The experimental results demonstrate that the expressions derived from the KAN model accurately represent the current–voltage (I–V) characteristics of the BSIM–CMG compact model and provide nearly symmetric results. To further validate the effectiveness and versatility of the approach, we embedded the trained I–V KAN model into a 12 nm FinFET SPICE model and performed 11-stage ring oscillator (RO) simulations. The results indicate that the KAN-based SPICE model achieves accuracy comparable to the original 12 nm FinFET SPICE model, demonstrating its potential to streamline device modeling for advanced technology nodes. Full article

In this paper, we study the performance of second-order compensated measurement to generate a multi-bit response in physically unclonable functions (PUFs). The proposed technique is based on a novel second-order compensated measurement generating multiple bits instead of a single bit provided by the conventional compensated measurement. A PUF based on this technique has been proposed and implemented in 40 Artix-7 FPGAs, and its uniqueness and reproducibility have been compared to those of another PUF using the compensated measurement technique. In addition, we demonstrate that the best trade-off between identifiability and computation time performance is obtained when using only two bits. At the same time, the good performance of the technique has been demonstrated, improving the identifiability of a ring oscillator PUF (RO-PUF) between 70 and 90% compared to a RO-PUF that uses conventional compensated measurement. In particular, equal error rates (EER) of the order of EER∼${10}^{-16}$ can be achieved by combining the sign bit with another bit extracted using the proposed technique; and up to EER∼${10}^{-19}$ by using one more extra bit. In addition, the high reliability of the responses generated by this technique against possible temperature and voltage variations has been proved. These results show how this new technique improves the performance of the PUF in terms of identifiability, so it can be effectively used for device identification purposes. Full article

In this paper, we propose a method to enhance the performance of a random number generator (RNG) that exploits ring oscillators (ROs). Our approach employs additional phase detectors to extract more entropy; thus, RNG uses fewer resources to produce bit sequences that pass all statistical tests proposed by National Institute of Standards and Technology (NIST). Generating a specified number of bits is on-demand, eliminating the need for continuous RNG operation. This feature enhances the security of the produced sequences, as eavesdroppers are unable to observe the continuous random bit generation process, such as through monitoring power lines. Furthermore, our research demonstrates that the proposed RNG’s perfect properties remain unaffected by the manufacturer of the field-programmable gate arrays (FPGAs) used for implementation. This independence ensures the RNG’s reliability and consistency across various FPGA manufacturers. Additionally, we highlight that the tests recommended by the NIST may prove insufficient in assessing the randomness of the output bit streams produced by RO-based RNGs. Full article

One of the challenges that wireless sensor networks (WSNs) need to address is achieving security and privacy while keeping low power consumption at sensor nodes. Physically unclonable functions (PUFs) offer a challenge–response functionality that leverages the inherent variations in the manufacturing process of a device, making them an optimal solution for sensor node authentication in WSNs. Thus, identifiability is the fundamental property of any PUF. Consequently, it is necessary to design structures that optimize the PUF in terms of identifiability. This work studies different architectures of oscillators to analyze which ones exhibit the best properties to construct a RO-based PUF. For this purpose, Generalized Galois Ring Oscillators (GenGAROs) are used. A GenGARO is a novel type of oscillator formed by a combination of up to two input logical operations connected in cascade, where one input is the output of the previous operation and the other is the feedback signal. GenGAROs include some previously proposed oscillators as well as many new oscillator designs. Thus, the architecture of GenGAROs is analyzed to implement a GenGARO-PUF on an Artix-FPGA. With this purpose, an exhaustive study of logical operation combinations that optimize PUF performance in terms of identifiability has been conducted. From this, it has been observed that certain logic gates in specific positions within the oscillator contribute to constructing a PUF with good properties, and by applying certain constraints, any oscillator generated with these constraints can be used to construct a PUF with an equal error rate on the order of or below ${10}^{-11}$ using 100-bit responses. As a result, a design methodology for FPGA-based RO-PUFs has been developed, enabling the generation of multiple PUF primitives with high identifiability that other designers could exploit to implement RO-based PUFs with good properties. Full article

Portable and wearable sensor systems implemented in the paradigm of the Internet of Things (IoT) are part of our daily activities as well as commercial and industrial products. The connection of measurement devices has led to not only a sharp increase in information sharing, but also to the frequency of cyber-attacks, in which system vulnerabilities are exploited to steal confidential information, corrupt data, or even make the system unavailable. Physical unclonable function (PUF)-based devices exploit the inherent randomness introduced during device manufacturing to create a unique fingerprint. They are widely used to generate passwords and cryptographic keys to mitigate security issues in IoT applications. Among the existing different PUF structures, ring oscillator (RO)-based PUF devices are very popular due to their simple structure and their potential easy integration onto chips. In this paper, the possibility of increasing the number of challenge–response pairs (CRPs) of RO-based PUF devices by measuring two different parameters (the oscillation frequency and the duty cycle) is investigated. The results achieved by the performed circuit level simulations and experimental measurements show that these two parameters feature a weak correlation. The proposed PUF device can be used to increase the number of CRPs to improve device security while achieving a high uniqueness value (49.77%). Full article

This paper introduces a novel TRNG architecture that employs a wave converter to generate random outputs from the jitter noise in a customized ring oscillator (RO). Using a current-starved inverter, the proposed RO offers the option of operating three different oscillation frequencies from a single oscillator. To assess its performance, the core TRNG proposed in this work was designed with multiple samples, employing various transistor sizes for 28 nm CMOS processes. The measurements show that only a small number of measured TRNG samples passed the randomness NIST SP 800-22 tests, which is a common problem, not only with the proposed TRNG but also with other TRNG structures. To solve this issue, a lightweight post-processing algorithm using the Photon hash function was newly applied to the proposed TRNGs topology. The lightweight Photon hash function-based post-processing was implemented with the proposed TRNG topology in a 28 nm CMOS process. The design occupies 16,498 µm², with a throughput of 0.0142 Mbps and power consumption of 31.12 mW. Measurements showed significant improvement, with a 50% increase in chips passing the NIST SP 800-22 tests. Compared with the conventional DRBG post-processing method, the proposed lightweight Photon post-processing reduces area occupation by five times and power consumption by 65%. Full article

The use of physical unclonable functions (PUFs) linked to the manufacturing process of the electronic devices supporting applications that exchange critical data over the Internet has made these elements essential to guarantee the authenticity of said devices, as well as the confidentiality and integrity of the information they process or transmit. This paper describes the development of a configurable PUF/TRNG module based on ring oscillators (ROs) that takes full advantage of the structure of modern programmable devices offered by Xilinx 7 Series families. The proposed architecture improves the hardware efficiency with two main objectives. On the one hand, we perform an exhaustive statistical characterization of the results derived from the exploitation of RO configurability. On the other hand, we undertake the development of a new version of the module that requires a smaller amount of resources while considerably increasing the number of output bits compared to other proposals previously reported in the literature. The design as a highly parameterized intellectual property (IP) module connectable through a standard interface to a soft- or hard-core general-purpose processor greatly facilitates its integration into embedded solutions while accelerating the validation and characterization of this element on the same electronic device that implements it. The studies carried out reveal adequate values of reliability, uniqueness, and unpredictability when the module acts as a PUF, as well as acceptable levels of randomness and entropy when it acts as a true random number generator (TRNG). They also illustrate the ability to obfuscate and recover identifiers or cryptographic keys of up to 4096 bits using an implementation of the PUF/TRNG module that requires only an array of $4\times 4$ configurable logic blocks (CLBs) to accommodate the RO bank. Full article

This paper introduces a low-complexity start–stop true random number generator (TRNG) utilizing jitter in ring oscillators (ROs). Incorporating phase detectors enhances entropy extraction from the same number of ROs. The raw bits undergo online post-processing using the SHA-1 algorithm, which is widely supported by many programming languages. The output bit streams pass all NIST statistical tests (SP 800-22 and SP-90B). Bits are generated on demand, enhancing security by preventing eavesdropping during continuous bit production. The TRNG maintains its performance regardless of the FPGA manufacturer. Full article

The reliability and durability of integrated circuits (ICs), present in almost every electronic system, from consumer electronics to the automotive or aerospace industries, have been and will continue to be critical concerns for IC chip makers, especially in scaled nanometer technologies. In this context, ICs are expected to deliver optimal performance and reliability throughout their projected lifetime. However, real-time reliability assessment and remaining lifetime projections during in-field IC operation remain unknown due to the absence of trustworthy on-chip reliability monitors. The integration of such on-chip monitors has recently gained significant importance because they can provide real-time IC reliability extraction by exploiting the fundamental physics of two of the major reliability degradation phenomena: bias temperature instability (BTI) and hot carrier degradation (HCD). In this work, we present an extensive study of ring oscillator (RO)-based degradation and annealing monitors designed on our latest 28 nm versatile array chip. This test vehicle, along with a dedicated test setup, enabled the reliable statistical characterization of BTI- and HCD-stressed as well as annealed RO monitor circuits. The versatility of the test vehicle presented in this work permits the execution of accelerated degradation tests together with annealing experiments conducted on RO-based reliability monitor circuits. From these experiments, we have constructed precise annealing maps that provide detailed insights into the annealing behavior of our monitors as a function of temperature and time, ultimately revealing the usage history of the IC. Full article

Most of the latest generation of integrated circuits use FinFET transistors for their performance, but what about their reliability? Does the architectural evolution from planar MOSFET to FinFET transistor have any effect on the integrated circuit reliability? In this article, we present a test bench we have developed to age and measure the degradation of 5103 ring oscillators (ROs) implemented in nine FPGAs with 16nm FinFET under different temperature and voltage conditions ($V_{nom}\le V_{stress}\le 1.3V_{nom}$ and $25{}^{°}\mathrm{C}\le T_{stress}\le 115{}^{°}\mathrm{C}$) close to operational conditions in order to predict reliability regarding degradation mechanisms at the transistor scale (BTI, HCI and TDDB) as realistically as possible. By comparing our initial RO measurements and the data extracted from Vivado, we will show that the performance of the nine FPGAs is between $50\%$ and $70\%$ of the best performance expected by Vivado. After 8000 h of ageing, we will see that the relative degradations of the RO are a maximum of $1\%$, which is a first indicator proving the FPGAs’ good reliability. By comparing our results with similar studies on 28 nm MOSFET FPGAs, we will reveal that 16 nm FinFET FPGAs are more reliable. To be implemented in an FPGA, an RO uses logic resources (LUT) and routing resources. We will show that degradation in the two types of resources is different. For this reason, we will present a method for separating degradations in logical and routing resources based on RO degradation measures. Finally, we will model rising and falling edge propagation time degradations in an FPGA as a function of time, temperature, voltage, signal duty cycle and resources used in the FPGA. Full article

With the combined call for increased network throughput and security comes the need for high-bandwidth, unconditionally secure systems. Through the combination of true random number generators (TRNGs) for unique seed values, and four-dimensional Lorenz hyperchaotic systems implemented on a Stratix 10 Intel FPGA, we are able to implement 60 MB/s encryption/decryption schemes with 0% data loss on an unconditionally secure system with the NIST standard using less than 400 mW. Further, the TRNG implementation allows for unique encryption outputs for similar images while still enabling proper decryption. Histogram and adjacent pixel analysis on sample images demonstrate that without the key, it is not possible to extract the plain text from the encrypted image. This encryption scheme was implemented via PCIe for testing and analysis. Full article