Search Results (7)

Nanoscale oxides grown in c-silicon, implanted with low-energy (2 keV) H⁺ ions and fluences ranging from 10¹³ cm⁻² to 10¹⁵ cm⁻² by RF plasma immersion implantation (PII), have been investigated. The oxidation of the implanted Si layers proceeded in dry O₂ at temperatures of 700 °C, 750 °C and 800 °C. The optical characterization of the formed Si/SiO_x structures was conducted by electroreflectance (ER) and spectroscopic ellipsometric (SE) measurements. From the ER and SE spectra analysis, the characteristic energy bands of direct electron transitions in Si are elaborated. The stress in dependence on hydrogenation conditions is considered and related to the energy shifts of the Si interband transitions around 3.4 eV. Silicon oxides, grown on PII Si at a low H⁺ fluence, have a non-stoichiometric nature, as revealed by IR-SE spectra analysis, while with an increasing H⁺ fluence in the PII Si substrates and/or the subsequent oxidation temperature the stoichiometric Si-O₄ units in the oxides become predominant. The development of surface morphology is studied by atomic force microscopy (AFM) imaging. Oxidation of the H⁺-implanted Si surface region flattens out the surface pits created on the Si surface by H⁺ implants. Based on the evaluation of the texture index and mean fractal dimension, the isotropic and self-similar character of the studied surfaces is emphasized. Full article

Memristive devices have garnered significant attention in the field of electronics over the past few decades. The reason behind this immense interest lies in the ubiquitous nature of memristive dynamics within nanoscale devices, offering the potential for revolutionary applications. These applications span from energy-efficient memories to the development of physical neural networks and neuromorphic computing platforms. In this research article, the angle toppling technique (ATT) was employed to fabricate titanium dioxide (TiO₂) nanoparticles with an estimated size of around 10 nm. The nanoparticles were deposited onto a 50 nm SiO_x thin film (TF), which was situated on an n-type Si substrate. Subsequently, the samples underwent annealing processes at temperatures of 550 °C and 950 °C. The structural studies of the sample were done by field emission gun-scanning electron microscope (FEG-SEM) (JEOL, JSM-7600F). The as-fabricated sample exhibited noticeable clusters of nanoparticles, which were less prominent in the samples annealed at 550 °C and 950 °C. The element composition revealed the presence of titanium (Ti), oxygen (O₂), and silicon (Si) from the substrate within the samples. X-ray diffraction (XRD) analysis revealed that the as-fabricated sample predominantly consisted of the rutile phase. The comparative studies of charge storage and endurance measurements of as-deposited, 550 °C, and 950 °C annealed devices were carried out, where as-grown device showed promising responses towards brain computing applications. Furthermore, the teaching–learning-based optimization (TLBO) technique was used to conduct further comparisons of results. Full article

In this study, Pt₁Sn₁ intermetallic nanoparticles (NPs) on SiO₂/CeO₂@SiO₂ composites were located either on SiO₂ or on CeO₂@SiO₂, thereby varying the average distance (intimacy) between metal sites and CeO_x sites from “closest” to “nanoscale”. The catalytic performance of these catalysts was compared to dual-bed mixtures of Pt₁Sn₁@SiO₂ and CeO₂@SiO₂ powders, which provided a “milliscale” distance between sites. Several beneficial effects on the catalytic performance of CO₂-assisted oxidative dehydrogenation of C₅-paraffins were observed when Pt₁Sn₁ nanoparticles were located on SiO₂ in nanoscale proximity to the CeO₂ sites, as opposed to Pt and Sn species located on CeO₂@SiO₂ with the closest proximity and milliscale intimacy between Pt₁Sn₁ and CeO₂. The former catalysts exhibited the highest C₅-paraffin conversion of 32.8%, with a C₅ total olefin selectivity of 68.7%, while the closest-proximity sample had a lower conversion of 17.4%, with a C₅ total olefin selectivity of 20.9%. The FT-IR (Fourier transform infrared spectroscopy) spectroscopic study of the CO adsorption and X-ray photoelectron spectroscopy results revealed that the closest proximity between Pt and Ce inhibited PtSn alloy formation due to their strong interaction. However, for the nanoscale-proximity sample, neighboring CeO₂@SiO₂ did not disturb Pt₁Sn₁ intermetallic formation. This strategy can be applied to other CO₂ activation catalysts, instead of CeO₂@SiO₂. This paper aims to provide insights into the influence of metal–CeO_x intimacy in bi-functional catalysts. Full article

Chemical modification is usually utilized for preparing superhydrophobic SiC surfaces, which has the problems of long processing time, high environmental contamination risk, and high cost. To enhance the condensation heat transfer efficiency of SiC, the superhydrophobic SiC surface was fabricated through laser texturing and heat treatment. In this study, the SiC surface was processed by laser texturing with a nanosecond laser, followed by heat treatment. Surface microstructures and compositions were investigated with SEM and XPS, and the heat transfer coefficient of the superhydrophobic SiC surface was tested. The results indicated that the laser-textured SiC surface had a super hydrophilic contact angle of 0°; after heat treatment, SiC ceramic became superhydrophobic (surface contact angle reaches 164°) because organic contamination on the original SiC surface could be cleaned by using laser texturing, which caused a chemical reaction and the formation of SiO₂ on the surface. Moreover, the distribution of relatively low-energy SiO_X was formed after heat treatment; then, SiC ceramic became superhydrophobic. Due to the formation of nanoscale sheet-like protrusion structures by heat treatment, the SiC superhydrophobic surface exhibited typical dropwise condensation, and the condensation heat transfer coefficient reached 331.8 W/(m²·K), which was 2.3 times higher than that of the original surface. Full article

In addition to the different technologies of silicon solar cells in crystalline form, TOPCon solar cells have an exceptionally great efficiency of 26%, accomplished by the manufacturing scale technique for industrialization, and have inordinate cell values of 732.3 mV open-circuit voltage (V_oc) and a fill factor (FF) of 84.3%. The thickness of tunnel oxide, which is less than 2 nm in the TOPCon cell, primarily affects the electrical properties and efficiency of the cell. In this review, various techniques of deposition were utilized for the layer of SiO_x tunnel oxide, such as thermal oxidation, ozone oxidation, chemical oxidation, and plasma-enhanced chemical vapor deposition (PECVD). To monitor the morphology of the surface, configuration of annealing, and rate of acceleration, a tunnel junction structure of oxide through a passivation quality of better V_oc on a wafer of n-type cell might be accomplished. The passivation condition of experiments exposed to rapid thermal processing (RTP) annealing at temperatures more than 900 °C dropped precipitously. A silicon solar cell with TOPCon technology has a front emitter with boron diffusion, a tunnel-SiO_x/n⁺-poly-Si/ SiN_x:H configuration on the back surface, and electrodes on both sides with screen printing technology. The saturation current density (J₀) for such a configuration on a refined face remains at 1.4 fA/cm² and is 3.8 fA/cm² when textured surfaces of the cell are considered, instead of printing with silver contacts. Following the printing of contacts with Ag, the J₀ of the current configuration improves to 50.8 fA/cm² on textured surface of silicon, which is moderately lesser for the metal contact. Tunnel oxide layers were deposited using many methods such as chemical, ozone, thermal, and PECVD oxidation are often utilized to deposit the thin SiO_x layer in TOPCon solar cells. The benefits and downsides of each approach for developing a SiO_x thin layer depend on the experiment. Thin SiO_x layers may be produced using HNO₃:H₂SO₄ at 60 °C. Environmentally safe ozone oxidation may create thermally stable SiO_x layers. Thermal oxidation may build a tunnel oxide layer with low surface recombination velocity (10 cm/s). PECVD oxidation can develop SiO_x on several substrates at once, making it cost-effective. Full article

The reduction of substrate temperature is important in view of the integration of III–V materials with a Si platform. Here, we show the way to significantly decrease substrate temperature by introducing a procedure to create nanoscale holes in the native-SiO_x layer on Si(111) substrate via In-induced drilling. Using the fabricated template, we successfully grew self-catalyzed GaAs nanowires by molecular-beam epitaxy. Energy-dispersive X-ray analysis reveals no indium atoms inside the nanowires. This unambiguously manifests that the procedure proposed can be used for the growth of ultra-pure GaAs nanowires. Full article

This paper gives an overview on some state-of-the-art characterization methods of SiO₂/4H-SiC interfaces in metal oxide semiconductor field effect transistors (MOSFETs). In particular, the work compares the benefits and drawbacks of different techniques to assess the physical parameters describing the electronic properties and the current transport at the SiO₂/SiC interfaces (interface states, channel mobility, trapping phenomena, etc.). First, the most common electrical characterization techniques of SiO₂/SiC interfaces are presented (e.g., capacitance- and current-voltage techniques, transient capacitance, and current measurements). Then, examples of electrical characterizations at the nanoscale (by scanning probe microscopy techniques) are given, to get insights on the homogeneity of the SiO₂/SiC interface and the local interfacial doping effects occurring upon annealing. The trapping effects occurring in SiO₂/4H-SiC MOS systems are elucidated using advanced capacitance and current measurements as a function of time. In particular, these measurements give information on the density (~10¹¹ cm⁻²) of near interface oxide traps (NIOTs) present inside the SiO₂ layer and their position with respect to the interface with SiC (at about 1–2 nm). Finally, it will be shown that a comparison of the electrical data with advanced structural and chemical characterization methods makes it possible to ascribe the NIOTs to the presence of a sub-stoichiometric SiO_x layer at the interface. Full article