Search Results (21)

A novel cell topology for a vertical 1200 V SiC planar double-implanted MOSFET (DMOSFET) is proposed in this work. Based on the conventional linear cell topology and the calibrated two-dimensional (2D) technology computer-aided design (TCAD) model parameters, a novel cell topology with the insertion of P+ body implanted regions over a fractional part of the channel and junction field effect transistor (JFET) regions was designed and optimized to achieve a low high-frequency figure of merit (HF-FOM, R_on × C_gd). Utilizing three-dimensional (3D) TCAD simulations, the new proposed cell topology with optimized selected structure parameters exhibits an HF-FOM of 328.748 mΩ·pF, which is 10.02% lower than the conventional linear topology. It also shows an improvement in the switching performance, with an 11.73% reduction in switching loss. Moreover, the impact of source ohmic contact resistivity on the performance of the proposed cell topology was highlighted, indicating the dependency of the source ohmic contact resistivity on the switching performance. This research provides a new perspective for enhancing the switching performance of SiC MOSFETs in high-frequency applications, considering practical factors such as contact resistivity. Full article

Recently, two-dimensional materials have gained significant attention due to their outstanding properties such as high charge mobility, mechanical strength, and electrical characteristics. These materials are considered one of the most promising solutions to overcome the limitations of semiconductor technology and are being utilized in various semiconductor device research. In particular, molybdenum diselenide (MoSe₂) and tungsten diselenide (WSe₂) are actively being developed for device applications due to their high electron mobility, optical properties, and electrical characteristics. In this study, we fabricated MoSe₂ and WSe₂-based junction field-effect transistors (JFET) and further deposited two-dimensional materials on the same device to fabricate and compare JFETs with a gate-all-around (GAA) structure. The research results showed that the GAA-structure JFET exhibited performance improvements in drain current, subthreshold swing (SS) transconductance (gm), and mobility, achieving enhancements ranging from a minimum of 1.2 times to a maximum of 10 times compared to conventional JFET. Full article

Newly introduced Photovoltaic (PV) devices, featuring a built-in chip with an illuminating Light Emitting Diode (LED), have emerged in the commercial market. These devices are touted for their utility as both low- and high-side power switch drivers and for data acquisition coupling. However, comprehensive knowledge and experimentation regarding the limitations of these Photovoltaic Drivers in both switching and signal processing applications remain underexplored. This paper presents a detailed characterization of a Photovoltaic Driver, focusing on its performance under resistive and capacitive loads. Additionally, it delineates the device’s constraints when employed in signal processing. Through the analysis of switching losses across various power switches (Silicon and Silicon Carbide) in both series and parallel driver configurations, this study assesses the driver’s efficacy in operating Junction Field-Effect Transistors (JFETs). Findings suggest that Photovoltaic Drivers offer a low-cost, compact solution for specific applications, such as high-voltage, low-bandwidth measurements, and low-speed turn-on with fast turn-off power switching scenarios, including solid-state switches and hot-swap circuits. Moreover, they present a straightforward, cost-effective method for driving JFETs, simplifying the circuit design and eliminating the need for an additional negative power source. Full article

A novel 4H-SiC trench metal-oxide-semiconductor field-effect transistor (TMOS) with depletion-mode pMOS (D-pMOS) is proposed and investigated via TCAD simulation. It has an auxiliary gate electrode that controls the electrical connections of P-shield layers under the trench bottom through the D-pMOS. In linear operation, the D-pMOS is turned off and then the potential of the P-shield layers is raised with the auxiliary gate, which shrinks the width of the depletion region of the P-shield/N-drift junction to reduce the resistance of the JFET region. In the saturation operation, the saturation current density of the proposed TMOS is reduced, benefiting from its relatively large cell pitch. The design concept eases the tension between specific on-resistance and short circuit capabilities. Numerical simulation results show that the proposed TMOS exhibits a short circuit withstand time that is 1.92 times longer than that of the conventional TMOS. In addition, a drive tactic is introduced and optimized for the proposed TMOS, which requires only one set of gate drivers. Compared with the conventional TMOS, the switching performance is improved and the switching loss is reduced by 40%. Full article

Silicon carbide junction field-effect transistors (SiC JFETs) are promising candidates as devices applicable to radiation conditions, such as the decommissioning of nuclear facilities or the space environment. We investigate the origin of the threshold volage (V_th) shift and hysteresis of differently structured SiC JFETs. A large positive V_th shift and hysteresis are observed for a depletion-type JFET with a larger depletion layer width. With changing the sweep range of the gate voltage and depletion width, the V_th shift was positively proportional to the difference between the channel depth and depletion width (channel depth–gate depletion width). By illuminating the sub-band gap light, the V_th of the irradiated depletion JFETs recovers close to nonirradiated ones, while a smaller shift and hysteresis are observed for the enhancement type with a narrower width. It can be interpreted that positive charges generated in a gate depletion layer cause a positive V_th shift. When they are swept out from the depletion layer and trapped in the channel, this gives rise to a further V_th shift and hysteresis in gamma-irradiated SiC JFETs. Full article

This paper presents a variable-gain low-noise amplifier (VGLNA) based on an adaptive bias (ADB) circuit for the radar receiver front end. The ADB circuit processes the signal separated by a coupler at the LNA output port. First, the ADB circuit rectifies the coupled signal into positive DC voltage through a rectifier, which is then inverted to control a junction-gate field-effect transistor (JFET). The voltage-controlled current of JFET flows through a voltage-divider network and finally produces the DC biasing voltage for the BJT base termination, which decreases with the increase in the input RF power. The proposed VGLNA operates automatically in high gain at low input power and low gain at high input power, providing a wider dynamic range as compared to the constant-bias counterpart. For validation, a prototype is fabricated and measured at 6 GHz. As observed, the base biasing voltage generated by the ADB circuit is changed from 858 mV to 798 mV as the input power increases from −50 dBm to 0 dBm. As a result, the dynamic range represented by the input P1dB point (IP1dB) has an increase of 6.5 dB, while LNA still maintains a high gain of 15.15 dB at low input power. Full article

This article presents a gate driver circuit with all-magnetic isolation for driving silicon carbide (SiC) power devices in a three-level T-type bridge-leg. Gate driver circuitry for SiC devices has to be tolerant of rapid common-mode voltage changes. With respect to the resultant potentially problematic common-mode current paths, an arrangement of transformers is proposed for supplying the power devices with drive signals and power for their local floating gate driver circuits. The high-frequency carrier phase-switching technique is used to reduce the number of transformers. Signal timing and other implementation issues are addressed when using this arrangement with the T-type converter. The circuit is demonstrated in a 540 V bridge-leg constructed around 650 V and 1200 V cascode-connected normally-on SiC junction field effect transistors (JFETs). Full article

Built-in freewheeling diode metal–oxide–semiconductor field-effect transistors (MOSFETs) that ensure high performance and reliability at high voltages are crucial for chip integration. In this study, a 4H–SiC built-in MOS-channel diode MOSFET with a center P+ implanted structure (CIMCD–MOSFET) is proposed and simulated via technology computer-aided design (TCAD). The CIMCD–MOSFET contains a P+ center implant region, which protects the gate oxide edge from high electric field crowding. Moreover, the region also makes it possible to increase the junction FET (JFET) and N-drift doping concentration of the device by dispersing the high electric field. Consequently, the CIMCD–MOSFET is stable even at a high voltage of 3.3 kV without static degradation and gate oxide reliability issues. The CIMCD–MOSFET also has higher short-circuit withstanding capability owing to the low saturation current and improved switching characteristics due to the low gate-drain capacitance, compared to the conventional MOSFET (C–DMOSFET) and the built-in Schottky barrier diode MOSFET (SBD–MOSFET). The total switching time of a CIMCD–MOSFET is reduced by 52.2% and 42.2%, and the total switching loss is reduced by 67.8% and 41.8%, respectively, compared to the C–DMOSFET and SBD–MOSFET. Full article

The effect of displacement defect on SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) due to radiation is investigated using technology computer-aided design (TCAD) simulation. The position, energy level, and concentration of the displacement defect are considered as variables. The transfer characteristics, breakdown voltage, and energy loss of a double-pulse switching test circuit are analyzed. Compared with the shallow defect energy level, the deepest defect energy level with E_C − 1.55 eV exhibits considerable degradation. The on-current decreases by 54% and on-resistance increases by 293% due to the displacement defect generated at the parasitic junction field-effect transistor (JFET) region next to the P-well. Due to the existence of a defect in the drift region, the breakdown voltage increased up to 21 V. In the double-pulse switching test, the impact of displacement defect on the power loss of SiC MOSFETs is negligible. Full article

This paper presents a new field-effect sensor called open-gate junction gate field-effect transistor (OG-JFET) for biosensing applications. The OG-JFET consists of a p-type channel on top of an n-type layer in which the p-type serves as the sensing conductive layer between two ohmic contacted sources and drain electrodes. The structure is novel as it is based on a junction field-effect transistor with a subtle difference in that the top gate (n-type contact) has been removed to open the space for introducing the biomaterial and solution. The channel can be controlled through a back gate, enabling the sensor’s operation without a bulky electrode inside the solution. In this research, in order to demonstrate the sensor’s functionality for chemical and biosensing, we tested OG-JFET with varying pH solutions, cell adhesion (human oral neutrophils), human exhalation, and DNA molecules. Moreover, the sensor was simulated with COMSOL Multiphysics to gain insight into the sensor operation and its ion-sensitive capability. The complete simulation procedures and the physics of pH modeling is presented here, being numerically solved in COMSOL Multiphysics software. The outcome of the current study puts forward OG-JFET as a new platform for biosensing applications. Full article

4H-SiC Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) with embedded Schottky barrier diodes are widely known to improve switching energy loss by reducing reverse recovery characteristics. However, it weakens the static characteristics such as specific on-resistance and breakdown voltage. To solve this problem, in this paper, an Asymmetric 4H-SiC Split Gate MOSFET with embedded Schottky barrier diode (ASG-MOSFET) is proposed and analyzed by conducting a numerical TCAD simulation. Due to the asymmetric structure of ASG-MOSFET, it has a relatively narrow junction field-effect transistor width. Therefore, despite using the split gate structure, it effectively protects the gate oxide by dispersing the high drain voltage. The Schottky barrier diode (SBD) is also embedded next to the gate and above the Junction Field Effect transistor (JFET) region. Accordingly, since the SBD and the MOSFET share a current path, the embedded SBD does not increase in R_ON,SP of MOSFET. Therefore, ASG-MOSFET improves both static and switching characteristics at the same time. As a result, compared to the conventional 4H-SiC MOSFET with embedded SBD, Baliga′s Figure of Merit is improved by 17%, and the total energy loss is reduced by 30.5%, respectively. Full article

A split-gate metal–oxide–semiconductor field-effect transistor (SG-DMOSFET) is a well-known structure used for reducing the gate–drain capacitance (C_GD) to improve switching characteristics. However, SG-DMOSFETs have problems such as the degradation of static characteristics and a high gate-oxide electric field. To solve these problems, we developed a SG-DMOSFET with floating p+ polysilicon (FPS-DMOSFET) and compared it with a conventional planar DMOSFET (C-DMOSFET) and a SG-DMOSFET through Technology Computer-Aided Design (TCAD) simulations. In the FPS-DMOSFET, floating p+ polysilicon (FPS) is inserted between the active gates to disperse the high drain voltage in the off state and form an accumulation layer over the entire junction field effect transistor (JFET) region, similar to a C-DMOSFET, in the on state. Therefore, the FPS-DMOSFET can minimize the degradation of static characteristics such as the breakdown voltage (BV) and specific on resistance (R_ON,SP) in the split-gate structure. Consequently, the FPS-DMOSFET can shorten the active gate length and achieve a gate-to-drain capacitance (C_GD) that is less than those of the C-DMOSFET and SG-DMOSFET by 48% and 41%, respectively. Moreover, the high-frequency figure of merit (HF-FOM = R_ON,SP × C_GD) of the FPS-DMOSFET is lower than those of the C-DMOSFET and SG-DMOSFET by 61% and 49%, respectively. In addition, the FPS-DMOSFET shows an E_MOX of 2.1 MV/cm, which guarantees a gate oxide reliability limit of 3 MV/cm. Therefore, the proposed FPS-DMOSFET is the most appropriate device to be used in high-voltage and high-frequency electronic applications. Full article

This paper presents the design and testing of a low-noise programmable voltage source. Such a piece of instrumentation is often required as part of the measurement setup needed to test electronic devices without introducing noise from the power supply (such as photodetectors, resistors or transistors). Although its construction is based on known configurations, here the discussion is focused on the characterization and the minimization of the output noise, especially at very low frequencies. The design relies on a digital-to-analog converter, proper lowpass filters, and a low-noise Junction Field-Effect Transistors (JFET) based voltage follower. Because of the very low level of output noise, in some cases we had to resort to cross-correlation in order to reduce the background noise of the amplifiers used for the characterization of the programmable source. Indeed, when two paralleled IF9030 JFETs are used in the voltage follower, the output noise can be as low as 3 nV/√Hz, 0.6 nV/√Hz and 0.4 nV/√Hz at 1 Hz, 10 Hz and 100 Hz, respectively. The output voltage drift was also characterized and a stability of ±25 µV over 3 h was obtained. In order to better appreciate the performance of the low-noise voltage source that we have designed, its noise performances were compared with those of a set-up based on one of the best low-noise solid-state voltage regulators available on the market. Actual measurements of the current noise in a type-II superlattice photodetector are reported in which the programmable source was used to provide the voltage bias to the device. Full article

The paper deals with the problem of modelling and analyzing the dynamic properties of a Junction Field Effect Transistor (JFET) made of silicon carbide. An examination of the usefulness of the built-in JFET Simulation Program with Integrated Circuit Emphasis (SPICE) model was performed. A modified model of silicon carbide JFET was proposed to increase modelling accuracy. An evaluation of the accuracy of the modified model was performed by comparison of the measured and calculated capacitance–voltage characteristics as well as the switching characteristics of JFETs. Full article

Silicon shows very high detection efficiency for low-energy photons, and the silicon pixel sensor provides high spatial resolution. Pixelated silicon sensors facilitate the direct detection of low-energy X-ray radiation. In this study, we developed junction field effect transistors (JFETs) that can be integrated into a pixelated silicon sensor to effectively handle many signal readout channels due to the pixelated structure without any change in the sensor resolution; this capability of the integrated system arises from the pixelated structure of the sensor. We focused on optimizing the JFET’s switching function, and simulated JFETs with different fabrication parameters. Furthermore, prototype JFET switches were designed and fabricated on the basis of the simulated results. It is important not only to keep the low leakage currents in the JFET but also reduce the current flow as much as possible by providing a high resistance when the JFET switch is off. We determined the optimal fabrication conditions for the effective switching of the JFETs. In this paper, we present the results of the measurement of the switching capability of the fabricated JFETs for various design variables and fabrication conditions. Full article