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Article

High Performance 3.3 kV SiC MOSFET Structure with Built-In MOS-Channel Diode

by
Jaeyeop Na
,
Minju Kim
and
Kwangsoo Kim
*
Department of Electronic Engineering, Sogang University, Seoul 04107, Korea
*
Author to whom correspondence should be addressed.
Energies 2022, 15(19), 6960; https://doi.org/10.3390/en15196960
Submission received: 29 August 2022 / Revised: 16 September 2022 / Accepted: 20 September 2022 / Published: 22 September 2022
(This article belongs to the Special Issue Analysis of SiC MOSFETs for Advanced Energy-Conversion Systems)
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Abstract

:
Built-in freewheeling diode metal–oxide–semiconductor field-effect transistors (MOSFETs) that ensure high performance and reliability at high voltages are crucial for chip integration. In this study, a 4H–SiC built-in MOS-channel diode MOSFET with a center P+ implanted structure (CIMCD–MOSFET) is proposed and simulated via technology computer-aided design (TCAD). The CIMCD–MOSFET contains a P+ center implant region, which protects the gate oxide edge from high electric field crowding. Moreover, the region also makes it possible to increase the junction FET (JFET) and N-drift doping concentration of the device by dispersing the high electric field. Consequently, the CIMCD–MOSFET is stable even at a high voltage of 3.3 kV without static degradation and gate oxide reliability issues. The CIMCD–MOSFET also has higher short-circuit withstanding capability owing to the low saturation current and improved switching characteristics due to the low gate-drain capacitance, compared to the conventional MOSFET (C–DMOSFET) and the built-in Schottky barrier diode MOSFET (SBD–MOSFET). The total switching time of a CIMCD–MOSFET is reduced by 52.2% and 42.2%, and the total switching loss is reduced by 67.8% and 41.8%, respectively, compared to the C–DMOSFET and SBD–MOSFET.

1. Introduction

Silicon carbide (SiC) is receiving considerable attention as an alternative to silicon for use in next-generation power semiconductors owing to its high thermal conductivity and breakdown voltage resulting from its wide bandgap [1,2,3]. SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) enable faster switching operations than Si insulated-gate bipolar transistors (IGBTs) [4]. Therefore, several power modules using SiC MOSFET devices that can withstand voltages in the range of 650 V to 1.7 kV have been proposed [5,6,7]. Research on SiC MOSFETs for applications with a high voltage of 3.3 kV and higher is also being actively pursued [8,9].
SiC Schottky barrier diodes (SBDs) are the most widely used external anti-parallel diodes in power module systems. An SBD has a low diode turn-on voltage, which can reduce the dead time loss; moreover, its unipolar device operation significantly reduces the reverse recovery charge [10,11,12]. In addition, the switching loss is small even at high temperatures because the reverse recovery charge of the SiC SBD does not depend on temperature [13,14]. However, an additional external SBD requires a large assembly area, which increases the size of the power module system [15]. In addition, an increase in the operating voltage increases the size of the SBD, thus requiring a larger active area [16]. The built-in PiN body diode can be used to reduce the size of the power-module system. However, the high turn-on voltage and bipolar degradation cause conduction loss. Additionally, the high reverse recovery charge and temperature-dependent bipolar operation cause a large switching loss in high-temperature and high-speed switching operations [17,18].
Several methods for embedding a unipolar diode in a MOSFET have been developed to address these limitations. The best-known approach is to embed an SBD within a MOSFET [19,20,21,22,23]. Through this approach, the size of the power module system was reduced using the built-in SBD MOSFET while reducing the energy loss through a low turn-on voltage and small reverse recovery charge. However, barrier lowering occurs in the Schottky junction owing to image force, and additionally, the thermionic emission and tunneling process at the lower energy barrier increases the off-state leakage current at high voltage and high temperature conditions of the built-in SBD MOSFETs [24,25,26].
Embedded polySi/SiC heterojunction diode MOSFETs (HJD–MOSFETs) are designed to reduce the reverse recovery charge of the body diode [27,28,29]. The HJD–MOSFET operates as a unipolar body diode and the reverse recovery charge can be reduced to a level that is similar to that of the SBD. However, it is not suitable for use at high voltages because of the low critical electric field of polysilicon and the large off-state leakage current due to the interfacial trap charge at the polySi/SiC interface [30,31].
A built-in MOS-channel diode MOSFETs (MCD–MOSFETs) have also been proposed to reduce the diode turn-on voltage and reverse recovery charge of the body diode [32,33,34]. However, because only one channel is formed in the on state of the MCD–MOSFET, the static characteristics deteriorate, and the low P-base doping concentration causes a reach-through problem at high voltages [35]. In addition, the split gate structure and thin gate oxide film create a large electric field at the oxide edge due to electric field crowding and impair the reliability of the gate oxide film [32,36]. This reduces the stability of the MCD–MOSFET at high voltages.
In this study, a 3.3 kV center-implanted embedded MOS-channel diode MOSFET (CIMCD–MOSFET) was proposed and analyzed via technology computer-aided design (TCAD) simulations. The proposed structure has P+ doping in the center region, which distributes the electric field and reduces electric field crowding at the oxide edge of the MCD–MOSFET. Therefore, the CIMCD–MOSFET operation is stable even at a high voltage of 3.3 kV without the reliability issues resulting from the oxide film. Moreover, the diode turn-on voltage can be further reduced by reducing the oxide thickness of the MOS-channel diode. In addition, the doping concentration of the junction FET (JFET) and drift region can be increased owing to the shielding effect of the central P+ doping region, thereby minimizing the degradation of static characteristics. The simulation results demonstrate that the CIMCD–MOSFET has improved static characteristics, switching characteristics, and short-circuit capability compared with conventional diffusion MOSFETs (C–DMOSFET) and built-in Schottky barrier diode MOSFETs (SBD–MOSFET).

2. Device Optimizations and Methods

Figure 1 shows the cross-sectional views of the C–DMOSFET, SBD–MOSFET, and CIMCD–MOSFET. To prevent the reach-through problem, P+ doping was applied to the P-base region of the MCD–MOSFET, except for the channel region [37]. As shown in Figure 1b, it is possible to use the built-in Schottky barrier diode through the Schottky contact in the mesa region of the SBD–MOSFET, compared to the C–DMOSFET. The work function of the SBD–MOSFET was set to 4.33 eV, which is the same as that of titanium [38,39].
As shown in Figure 1c, the CIMCD–MOSFET has a split-gate structure. The right-side split dummy gate is in contact with the source while the left-side split gate is in contact with the gate. When the MOSFET is turned on, a channel is formed in the left P-base and current flows. When the MOSFET is turned off and the diode is turned on, a channel is formed in the right P-base due to the voltage difference between the source and drain and current flows. To reduce the turn-on voltage of the MOS-channel diode, the thickness of Tox2 should be 5 nm, which is much smaller than that of Tox1.
A shielding region was also formed by the P+ doping in the center region of the MCD–MOSFET structure, as shown in Figure 1c. The central P+ shielding region overlaps with the oxide edge below the split gate to directly protect the oxide from the high electric field and prevent field crowding at the oxide edge. In addition, the center-implanted P+ region improves the breakdown capability of the MOSFET by dispersing the high electric field in the P+ base region, thereby increasing the doping concentration of the JFET and N-drift region. Table 1 summarizes the parameters of the device structure. Figure 2a shows Baliga’s figure of merit (B–FOM) of the CIMCD–MOSFET according to the N-drift doping concentration (ND) and JFET width (WJFET). The B–FOM is defined as the square of the breakdown voltage (BV) divided by the specific on-resistance (Ron-sp) [40]. The WJFET and ND are important parameters that affect the Ron-sp and BV. The longer the WJFET, the lower the JFET resistance. However, the BV decreases and the cell pitch increases. This decreases the device integration in the active area. Also, the doping concentration of the N-drift increases, and the Ron-sp and BV decrease. As shown in Figure 2a, the CIMCD–MOFSET has the highest B–FOM value when WJFET = 1.8 μm and the doping concentration of N-drift is 3.5 × 1015 cm−3. Figure 2b shows the body diode turn-on voltage VF that is based on the width of the WD. A longer WD improves the diode current flow, decreases the VF, and decreases the cell density because the cell pitch increases. As the VF does not change significantly for a WD length of 1 μm or more, it is reasonable to maintain the WD length at 1 μm.
The simulation results of each device were obtained using the Sentaurus TCAD simulation package. The electron/hole continuity equations and Poisson equations were solved by considering mobility degradation and recombination in the simulation. The Lombardi interface charge model and high-field saturation were applied to the mobility model [41]. The Shockley–Read–Hall recombination and Auger recombination models were considered and the Hatakeyama model was applied [42]. In addition, we applied an incomplete ionization model, anisotropic mobility, and bandgap narrowing. Barrier lowering, barrier tunneling, and thermionic emission were considered for the Schottky contacts [43]. Furthermore, the channel mobility was estimated to be 15–20 cm2/V·s through the SiC/SiO2 interface charge and a thermodynamic model was considered for a high-temperature simulation [44,45].

3. Simulation Results and Analysis

3.1. Static Performances

Figure 3 shows the off-state characteristics of the C–DMOSFET, SBD–MOSFET, and CIMCD–MOSFET. They have a breakdown voltage of over 3.3 kV at T = 300 K. At T = 450 K, additionally, the off-state leakage current is high in the SBD–MOSFET compared to the C–DMOSFET and CIMCD–MOSFET. Due to the tunneling effect of electrons in a thermally excited metal, called thermionic-field emission, the reverse leakage current of SBD–MOSFET is highly temperature-dependent [46]. Figure 4 shows the electric field distribution of each device. For improved reliability of the gate oxide film, the maximum electric field EMOX of the gate oxide is preferably ≤3 MV/cm [47]. In Figure 4a,b, the EMOX of the C–DMOSFET and SBD–MOSFET is approximately 3 MV/cm at VDS = 3 kV. The MCD–MOSFET without the center implant region applies a large electric field of 7.45 MV/cm to the oxide edge, even at VDS = 2 kV (Figure 4d). A large electric field across the thin gate oxide causes a large off-state leakage current due to tunneling and causes premature breakdown at low voltages. Conversely in Figure 4c, the center implant region of the CIMCD–MOSFET overlaps with the oxide edge to block the electric field. Moreover, by dispersing the electric field, a lower electric field is applied to the oxide film compared to the C–DMOSFET and SBD–MOSFET, even at a high voltage of VDS = 3 kV.
Figure 5 shows the on-state characteristics of each device. The CIMCD–MOSFET uses only a single channel in the on state, resulting in static degradation. Its saturation current is also smaller compared to the C–DMOSFET and SBD–MOSFET. However, owing to the increase in the breakdown voltage capability of the center implant region, the doping concentration of the JFET and N-drift can be increased and the static degradation can be minimized. As a result, the CIMCD–MOSFET has the highest B–FOM compared to the C–DMOSFET and SBD–MOSFET, despite being a single-channel MOSFET.
Figure 6a shows the third quadrant characteristics of the C–DMOSFET, SBD–MOSFET, and CIMCD–MOSFET. Owing to the Schottky barrier, the SBD–MOSFET has the lowest VF. The VF of the CIMCD–MOSFET is proportional to Tox2. In Figure 6b, the VF decreases as Tox2 decreases, but the electric field crowding at the oxide edge increases. Owing to the center implant shielding region, reducing the thickness of Tox2 to 5 nm does not cause oxide film reliability issues, resulting in a lower VF than the C–DMOSFET’s PiN body diode. Table 2 summarizes the static characteristics of the C–DMOSFET, SBD–MOSFET, and CIMCD–MOSFET. The CIMCD–MOSFET shows the highest oxide reliability characteristics among the three devices owing to the center implant area. The B–FOM is improved by 2.05% and 11.17% compared to the CMOSFET and SBD–MOSFET, respectively, by minimizing static degradation.

3.2. Dynamic Performances

Next, we simulated the dynamic characteristics of the device via mixed-mode simulation in TCAD. The short-circuit reliability, parasitic gate capacitance, reverse recovery characteristics, and switching performances of the device were simulated. Figure 7a shows the short-circuit (SC) test circuit diagram. The short-circuit roughness was tested at VDS = 1700 V and VGS = 15 V. The thermal runaway time in the short- circuit condition was observed by applying a pulse voltage to the gate for a fixed duration. Figure 7b–d show the SC withstanding capabilities of the C–DMOSFET, SBD–MOSFET, and CIMCD–MOSFET. The temperature represents the highest temperature of the device. In the SBD–MOSFET, when the SC time is 3 µs, the leakage current and the internal temperature of the device rapidly increase in thermal runaway. The SBD–MOSFET has a very short SC withstand time (TSC) of approximately less than 3 µs and the lowest SC reliability. Conversely, the CIMCD–MOSFET has the longest TSC compared to the C–DMOSFET and SBD–MOSFET, where device failure occurred at TSC = 23 µs. TSC is generally inversely proportional to the device’s drain saturation current (IDsat) [48]. Since CIMCD–MOSFETs have a smaller IDsat than C–DMOSFETs, they have the longest SC withstand time and consequently, the highest SC capability. Figure 8 shows the total current density and lattice temperature of the device at the SC thermal runaway point after the gate is turned off. As is evident from Figure 8a,c, the thermal runaway mechanism of the C–DMOSFET and CIMCD–MOSFET results in device failure owing to the drain leakage current that is caused by the parasitic npn transistor turn-on [49]. However, as shown in Figure 8b, the off-state leakage current of the SBD–MOSFET occurs at the Schottky contact. The elevated lattice temperature near the Schottky contact enhances the thermionic-field emission there and moves many electrons, generating a large off-state leakage current even in the gate-off state [50,51]. Consequently, the SBD–MOSFET undergoes early thermal runaway and has a very poor short-circuit capability compared to the CIMCD–MOSFET.
Figure 9 compares the parasitic capacitances Crss (CGD), Ciss (CGD + CGS), and Coss (CGD + CDS) of the C–DMOSFET, SBD–MOSFET, and CIMCD–MOSFET. Crss is an important parameter that has high correlation with the switching time. In general, because the values of Crss are proportional to the switching time, it is advantageous to minimize the values of Crss. As the CIMCD–MOSFET has a split gate structure, the overlap area between the gate-drain can be minimized, thereby reducing the parasitic capacitance that is generated from the gate-drain coupling [52]. Consequently, the CIMCD–MOSFET has a low Crss value that is reduced by 71.06% for the C–DMOSFET and 61.98% for the SBD–MOSFET.
Figure 10a compares the body diode reverse recovery characteristics of the C–DMOSFET, SBD–MOSFET, and CIMCD–MOSFET. Figure 10b shows a double pulsed test circuit to check the reverse recovery and switching characteristics of the device. In Figure 10a, the IRM is the reverse peak current, and the reverse recovery time Trr is the time that is taken by the reverse recovery current to reduce from zero to −IRM and subsequently recover to −0.1 IRM [53]. The reverse recovery charge Qrr can be calculated by integrating the IDS over Trr. As the body diode of the C–DMOSFET operates as a bipolar device, several remaining minority carriers in the N-drift have to be recombined when it is turned off, resulting in a large Qrr. Conversely, in the SBD–MOSFET and CIMCD–MOSFET, because the body diode operates as a unipolar device, a few minority carriers remain in the N-drift, and the Qrr is much smaller than that of the C–DMOSFET. The Qrr of the CIMCD–MOSFET is similar to that of the SBD–MOSFET and is reduced 89.1% from that of C–DMOSFET.
Figure 11 shows the switching transients of the C–DMOSFET, SBD–MOSFET, and CIMCD–MOSFET. Figure 12 compares the power dissipation of each device. The switching-on time TON is defined as the sum of the time from 10% VGS to 90% VDS (Td-on) and the rise time from 90% to 10% VDS (Tr). Similarly, the switching-off time TOFF is defined as the sum of the time from 90% VGS to 10% VDS (Td-off) and the fall time from 10% to 90% VDS (Tf) [54]. As the Crss decreases due to the split gate structure, the CIMCD–MOSFET has a shorter switching time than the C–DMOSFET and SBD–MOSFET. With a short switching time and small Qrr, the switching on and off energy losses (EON, EOFF) of the CIMCD–MOSFET are greatly reduced, and the total switching energy loss (ET) is reduced by 67.8% and 41.8%, respectively, compared to the C–DMOSFET and SBD–MOSFET. Table 3 lists the dynamic characteristics of the C–DMOSFET, SBD–MOSFET, and CIMCD–MOSFET devices.

3.3. Proposed Fabrication Process

Figure 13 shows the proposed fabrication process of CIMCD-MOSFET through Sprocess simulation. Figure 13a illustrates the formation of the drift region by SiC epitaxial growth on the N+ substrate, and the formation of the P+ shielding region, p-base region, and source region through multi-ion implantation [55,56]. Next, an oxide film is formed by dry thermal oxidation and doped polysilicon is deposited as shown in Figure 13b [57]. Then, in Figure 13c, the polysilicon is etched by anisotropic etching, leaving only the gate region. After making the thin oxide film (Tox2) of the MOS-channel diode through anisotropic oxide etching in Figure 13d, polysilicon is deposited again as shown in Figure 13e [58]. Subsequently, excluding the gate part and the dummy gate part, the remaining polysilicon region is anisotropically etched as shown in Figure 13f. After that, N inter-level dielectric (ILD) oxide film is deposited through CVD in Figure 13g, and finally, the source contact is completed through metal deposition after etching the source region of the ILD oxide as shown in Figure 13h [59].

4. Conclusions

In this study, a built-in MOS-channel diode MOSFET with a center-doped P+ region was investigated via TCAD simulation. The CIMCD–MOSFET effectively protects the gate oxide owing to the center P+ shielding region that overlaps with the oxide edge. Moreover, this region minimizes static degradation by increasing the doping concentration of the JFET and N-drift via electric field dispersion. In addition, the low saturation current allows CIMCD–MOSFET to exhibit better short-circuit withstanding capability than the C–DMOSFET and the SBD–MOSFET. The reverse recovery charge, similar to that of the SBD and the split gate structure of the device, greatly reduces the switching time and loss of the CIMCD–MOSFET. Consequently, the B–FOM of the CIMCD–MOSFET is improved by 2.05% and 11.17%, and the switching loss is improved by 67.8% and 41.8%, respectively, compared to those of the C–DMOSFET and SBD–MOSFET. These results demonstrate that the CIMCD–MOSFET can be effectively used as a 3.3 kV high-voltage power module system with a body diode configuration owing to its high reliability and improved switching characteristics.

Author Contributions

All authors contributed to this work. Conceptualization, J.N.; methodology, J.N., M.K. and K.K.; software, J.N. and M.K.; validation, J.N., M.K. and K.K.; formal analysis, J.N., M.K. and K.K.; investigation, J.N.; resources, J.N., M.K. and K.K.; writing—original draft preparation, J.N.; writing—review and editing, K.K.; visualization, J.N.; supervision, K.K.; project administration, J.N. and K.K.; All authors have read and agreed to the published version of the manuscript.

Funding

This research received no external funding.

Institutional Review Board Statement

Not applicable.

Informed Consent Statement

Not applicable.

Data Availability Statement

Data are not available on a publicly accessible repository and they cannot be shared under request.

Acknowledgments

This paper was supported by a Korea Institute for Advancement of Technology (KIAT) grant funded by the Korea Government (MOTIE) (P0017011, HRD Program for Industrial Innovation), and then Samsung Electronics.

Conflicts of Interest

The authors declare no conflict of interest.

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Figure 1. Cross–sectional view of (a) C–DMOSFET, (b) SBD–MOSFET, and (c) CIMCD–MOSFET.
Figure 1. Cross–sectional view of (a) C–DMOSFET, (b) SBD–MOSFET, and (c) CIMCD–MOSFET.
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Figure 2. Comparison of the (a) B–FOM characteristics for WJFET and ND variation of CIMCD–MOSFET (b) third-quadrant characteristics for different WD of CIMCD–MOSFET.
Figure 2. Comparison of the (a) B–FOM characteristics for WJFET and ND variation of CIMCD–MOSFET (b) third-quadrant characteristics for different WD of CIMCD–MOSFET.
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Figure 3. Off-state characteristics of C–DMOSFET, SBD–MOSFET, and CIMCD–MOSFET at T = 300 K and 450 K.
Figure 3. Off-state characteristics of C–DMOSFET, SBD–MOSFET, and CIMCD–MOSFET at T = 300 K and 450 K.
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Figure 4. Electric field distribution of (a) C–DMOSFET, (b) SBD–MOSFET, (c) CIMCD–MOSFET, and (d) MCD–MOSFET without the center implant region.
Figure 4. Electric field distribution of (a) C–DMOSFET, (b) SBD–MOSFET, (c) CIMCD–MOSFET, and (d) MCD–MOSFET without the center implant region.
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Figure 5. On-state characteristics of C–DMOSFET, SBD–MOSFET, and CIMCD–MOSFET.
Figure 5. On-state characteristics of C–DMOSFET, SBD–MOSFET, and CIMCD–MOSFET.
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Figure 6. (a) Third quadrants characteristics of C–DMOSFET, SBD–MOSFET, and CIMCD–MOSFET. (b) Variation of diode turn-on voltage (VF) and oxide edge maximum electric field of CIMCD-MOSFET with Tox2.
Figure 6. (a) Third quadrants characteristics of C–DMOSFET, SBD–MOSFET, and CIMCD–MOSFET. (b) Variation of diode turn-on voltage (VF) and oxide edge maximum electric field of CIMCD-MOSFET with Tox2.
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Figure 7. (a) Equivalent circuit diagram of short-circuit test. Short-circuit waveforms of (b) C–DMOSFET, (c) SBD–MOSFET, and (d) CIMCD–MOSFET.
Figure 7. (a) Equivalent circuit diagram of short-circuit test. Short-circuit waveforms of (b) C–DMOSFET, (c) SBD–MOSFET, and (d) CIMCD–MOSFET.
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Figure 8. Total current density distribution and lattice temperature distribution at the SC thermal runaway point (@IDS = 1 kA/cm2) of (a) C–DMOSFET (b) SBD–MOSFET, and (c) CIMCD–MOSFET.
Figure 8. Total current density distribution and lattice temperature distribution at the SC thermal runaway point (@IDS = 1 kA/cm2) of (a) C–DMOSFET (b) SBD–MOSFET, and (c) CIMCD–MOSFET.
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Figure 9. Comparison of the parasitic gate capacitance of the C–DMOSFET, SBD–MOSFET, and CIMCD–MOSFET.
Figure 9. Comparison of the parasitic gate capacitance of the C–DMOSFET, SBD–MOSFET, and CIMCD–MOSFET.
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Figure 10. (a) Comparison of the reverse recovery characteristics of the C–DMOSFET, SBD–MOSFET, and CIMCD–MOSFET. (b) Double pulsed test circuit diagram.
Figure 10. (a) Comparison of the reverse recovery characteristics of the C–DMOSFET, SBD–MOSFET, and CIMCD–MOSFET. (b) Double pulsed test circuit diagram.
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Figure 11. (a) Comparison of the (a) drain voltage switching waveforms and (b) drain current switching waveforms of C–DMOSFET, SBD–MOSFET, and CIMCD–MOSFET.
Figure 11. (a) Comparison of the (a) drain voltage switching waveforms and (b) drain current switching waveforms of C–DMOSFET, SBD–MOSFET, and CIMCD–MOSFET.
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Figure 12. Comparison of the (a) power dissipation and (b) total switching energy loss of C–DMOSFET, SBD–MOSFET, and CIMCD–MOSFET that were obtained via the double pulsed test.
Figure 12. Comparison of the (a) power dissipation and (b) total switching energy loss of C–DMOSFET, SBD–MOSFET, and CIMCD–MOSFET that were obtained via the double pulsed test.
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Figure 13. Proposed fabrication process of CIMCD–MOSFET. (a) The drift region is formed through epitaxyial growth on an N+ SiC substrate, and P+ shielding, P base, and N+ source are formed through multi-implantation. (b) An oxide film is formed through dry oxidation and doped polysilicon is deposited by CVD. (c) Anisotropic polysilicon etching to form a gate region. (d) Anisotropic etching of SiO2 to form a thin oxide film. (Tox2) (e) Deposition of polysilicon through CVD. (f) Anisotropic etch polysilicon to form a dummy gate. (g) Deposition of inter-level dielectric (ILD) oxide through CVD. (h) Etching the oxide and metallization.
Figure 13. Proposed fabrication process of CIMCD–MOSFET. (a) The drift region is formed through epitaxyial growth on an N+ SiC substrate, and P+ shielding, P base, and N+ source are formed through multi-implantation. (b) An oxide film is formed through dry oxidation and doped polysilicon is deposited by CVD. (c) Anisotropic polysilicon etching to form a gate region. (d) Anisotropic etching of SiO2 to form a thin oxide film. (Tox2) (e) Deposition of polysilicon through CVD. (f) Anisotropic etch polysilicon to form a dummy gate. (g) Deposition of inter-level dielectric (ILD) oxide through CVD. (h) Etching the oxide and metallization.
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Table
Table 1. Device parameters.
Table 1. Device parameters.
ParameterC–SBD–CIMCD–
Cell pitch [μm]910.810.55
Gate oxide thickness Tox1 [nm]505050
Gate oxide thickness Tox2 [nm]--5
P channel width [μm]0.50.50.5
P+ base width [μm]333
P+ base depth [μm]111
N-drift thickness [μm]303030
N+ substrate thickness [μm]100100100
WJFET [μm]32.81.8
WD [μm]-11
WF [μm]--1.75
N-drift doping ND [cm−3]2.8 × 10153 × 10153.5 × 1015
JFET doping [cm−3]--2 × 1016
P+ doping [cm−3]2 × 10182 × 10182 × 1018
P channel doping [cm−3]2 × 10172 × 10172 × 1017
N+ substrate doping [cm−3]1 × 10191 × 10191 × 1019
Table
Table 2. Static characteristics of devices.
Table 2. Static characteristics of devices.
ParameterC–SBD–CIMCD–
BV [V]408939264045
RON-SP [mΩ·cm2]9.810.619.4
EMOX (@VDS = 3 kV) [MV/cm]33.072.34
B–FOM [kV2/mΩ·cm2]1.7061.5661.741
VF (@IDS = −80 A·cm2) [μm]3.271.812.44
Table
Table 3. Dynamic characteristics of devices.
Table 3. Dynamic characteristics of devices.
ParameterC–SBD–CIMCD–
TSC [µs]<10<3<23
Crss [pF·cm−2]37.9428.8810.98
Trr [ns]11470.442.2
IRM [A/cm−2]1673545
Qrr [µC·cm−2]10.691.021.17
TON [ns]13912292
TOFF [ns]1206991551
EON [mJ·cm−2]25.4811.449.28
EOFF [mJ·cm−2]17.2612.224.48
ET [mJ·cm−2]42.7423.6613.76
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Na, J.; Kim, M.; Kim, K. High Performance 3.3 kV SiC MOSFET Structure with Built-In MOS-Channel Diode. Energies 2022, 15, 6960. https://doi.org/10.3390/en15196960

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Na J, Kim M, Kim K. High Performance 3.3 kV SiC MOSFET Structure with Built-In MOS-Channel Diode. Energies. 2022; 15(19):6960. https://doi.org/10.3390/en15196960

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Na, Jaeyeop, Minju Kim, and Kwangsoo Kim. 2022. "High Performance 3.3 kV SiC MOSFET Structure with Built-In MOS-Channel Diode" Energies 15, no. 19: 6960. https://doi.org/10.3390/en15196960

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