Search Results (503)

To address the issues of high customization, long development cycles, and excessive power/volume in radio frequency (RF) transceiver modules for Synthetic Aperture Radar (SAR) and radar systems, this paper presents an ultra-compact universal RF transceiver module design based on a full application-specific integrated circuit (ASIC) architecture. Centered on a wideband RF System-on-chip (SoC) and a reconfigurable digital SoC, the module integrates the complete RF transceiver chain—including filtering, amplification, mixing, Analog-to-Digital/Digital-to-Analog Converter (ADC/DAC) conversion, digital preprocessing, and high-speed data transmission. Test results demonstrate that the 8-channel module achieves a 53.1% area reduction and 55.1% lower power consumption (only 40.9 W) compared with conventional architectures, while all key RF specifications meet system requirements. The proposed solution improves upon existing limitations in high integration, low power, and generality, offering a low-cost, rapid-development technical route for transceiver modules in radar and communication applications. Full article

As digital beauty filters have become widespread among young people, their links with self-image cognition and behavioral responses have attracted growing attention. However, existing studies largely focus on Western samples or linear approaches, leaving Chinese youth underexplored in their cultural context. Using mixed methods combining grounded theory and fsQCA, this study examines the mechanisms shaping self-image cognition and behavioral responses among Chinese youth in the context of digital beauty filter use. Semi-structured interviews and three-stage coding identified four core categories: Beauty Filter Use Habits, Beauty Filter Use Motivations, Beauty Filter Use Preferences, and Psychological Responses to Beauty Filter Use. Building on this, fsQCA identified five configurational pathways. The psychological-response–motivation and psychological-response–preference core coexistence configurations were linked to high Self-Image Cognition; the three non-high Self-Image Cognition pathways formed two patterns: dual absence of psychological responses and motivations, and motivational-core absence with coexisting habits and preferences. Different self-image cognition outcomes may relate to adaptive behaviors, such as moderate retouching and naturalized self-presentation, or risk-related behaviors, such as avoidance of original images and overdependence on beauty filters. This study offers a new perspective on youth authentic self-construction and technological adaptation in the digital visual era, with implications for media literacy education, platform design, and mental health intervention. Full article

Implantable medical device (IMD) and Internet of Medical Things (IoMT) environments need intrusion detection systems that learn across distributed hospitals without centralizing sensitive data, while controlling admission, protecting shared model artifacts, filtering unreliable contributors, and supporting post-run auditability. However, many secure federated learning designs treat identity, privacy, robustness, and evidence verification as separate layers, leaving a gap between privacy-preserving execution and public accountability. This paper presents an implemented zero-trust hierarchical federated learning-based intrusion detection system (FL-IDS) framework for IMD/IoMT security analytics. Hospital clients train eXtreme Gradient Boosting (XGBoost) detectors; self-sovereign identity gates participation; contribution-level differential privacy (DP) perturbs exported booster leaf weights; country aggregators apply adaptive Krum-inspired selection; and the global server performs trust-weighted prediction-level fusion. The evidence layer binds artifacts using Module-Lattice-Based Digital Signature Algorithm signatures, canonical hashes, Merkle roots, decentralized publication, Ethereum Sepolia anchoring, and standalone auditor verification. The framework is evaluated on WUSTL-EHMS-2020, ECU-IoHT, and CICIoMT2024 under paired DP-disabled and DP-enabled modes. Under DP-enabled execution, CICIoMT2024 achieved an F1-score of 0.998789 and area under the receiver operating characteristic curve (AUROC) of 0.999814, ECU-IoHT achieved an AUROC of 0.999337, and WUSTL-EHMS-2020 remained DP-sensitive with an F1-score of 0.422880 and AUROC of 0.776685. All paired evidence runs passed standalone auditor verification, demonstrating that privacy-preserving learning and public accountability can be integrated within a single experimental FL-IDS pipeline. Full article

Flooding poses a serious challenge in rapidly growing mountain cities, where steep relief, wadi networks, and expanding urban surfaces concentrate runoff along narrow drainage pathways. This study applies a terrain-based Height Above Nearest Drainage (HAND) workflow within a GIS environment to map flood susceptibility and infrastructure exposure across the Abha, Khamis Mushait, and Ahad Rafidah catchment in the Aseer Region of Saudi Arabia. A 30 m digital elevation model was processed in PCRaster to derive flow direction, flow accumulation, stream networks, subcatchments, and HAND surfaces under four contributing-area thresholds of 1, 5, 10, and 20 km². The scenario design evaluates how drainage-representation uncertainty affects susceptibility and exposure estimates. Susceptibility was summarized for cumulative HAND classes of ≤5, ≤10, ≤20, and ≤30 m, then intersected with filtered building footprints and the road network to estimate infrastructure exposure. The analysis shows that mapped susceptibility varies with drainage representation, but the most critical building and road exposure remains concentrated within the same low-lying urban–wadi zone across all scenarios. The mapped extent of the HAND ≤ 5 m class declined from 367 km² under the 1 km² scenario to 99 km² under the 20 km² scenario. Buildings within HAND ≤ 5 m decreased from 26,449 to 5633, while road segments within the same class declined from 8758 to 1393. Even under more conservative stream thresholds, exposure remains focused within this same urbanized drainage belt, indicating persistent localized susceptibility. The findings show that HAND can be used as a practical first-pass screening tool for identifying flood-susceptible terrain and prioritizing exposed infrastructure in data-scarce environments, while the scenario-based threshold testing improves confidence in identifying robust hotspots for follow-up hydraulic modeling and urban risk management. Full article

Floating-point arithmetic provides the dynamic range that fixed-point lacks for digital signal processing (DSP) algorithms with widely varying operand magnitudes. This work presents a parameterizable floating-point unit set for field programmable gate array (FPGA)-based DSP. The set consists of five units: adder/subtractor, multiplier, multiply–accumulate (MAC), fixed-to-float and float-to-fixed converters. Two architectural choices distinguish the proposed format from IEEE-754: configurable exponent and mantissa widths during synthesis and a $0.f$ significand encoding that reduces corner-case logic at the cost of one additional mantissa bit. The format is therefore IEEE-754-inspired rather than fully compliant: special values (NaN, ±∞) are not implemented, and overflow and underflow are handled through saturation to predefined constants. The design is implemented in standard VHDL-2008 without relying on high-level synthesis (HLS) tools or vendor-specific primitives, ensuring portability across different FPGA families and application-specific integrated circuits (ASICs). The multiplier and MAC are evaluated in two configurations: inferring DSP blocks or look-up table (LUT)-only, both close timing at 300MHz on Artix-7 and Kintex Ultrascale devices. The proposed blocks outperform vendor IP Cores and recent academic designs in terms of area-throughput-power (ATP), achieving improvements from 10% to 108%, except for the adder/subtractor, which does not outperform two optimized Xilinx IP cores (HS-R and HS-P) and is therefore included for design coherence rather than as a strict resource improvement over all vendor IPs. All these blocks meet the theoretical error bound, and a representative 200-tap finite impulse response (FIR) filter built from them closes timing at 300MHz with 76% LUT utilization. Full article

Reliable indoor localization is required for automated guided vehicles (AGVs), robot validation, and industrial digital-twin applications, but ultrasonic positioning can degrade sharply when acoustic visibility changes. This paper evaluates Marvelmind Super-Beacon localization in controlled laboratory experiments involving both AGV tracking and UR10 robot-arm positioning. The non-inverse architecture (NIA) and inverse architecture (IA) configurations are included as parallel validation scenarios to assess the robustness of the proposed mitigation framework across different Marvelmind deployment modes. The baseline analysis identifies the dominant acoustic failure modes, including multipath-induced scatter, crossover-zone handover jumps, update-rate degradation, complete non-line-of-sight (NLoS) outages, and height-dependent 3D jitter. To mitigate these effects, an embedded ultrasonic–inertial pipeline is implemented on an ESP32-S3-WROOM-1 module. The system combines UART packet validation, interrupt-driven ICM-20948 inertial acquisition at 500 Hz, sliding-window kinematic outlier rejection, and a 15-state error-state Kalman filter (ESKF). The embedded estimator logic is designed to maintain motion continuity during intermittent or corrupted acoustic positioning while reintroducing validated ultrasonic absolute corrections. Using recorded AGV and UR10 datasets, mitigation performance was quantitatively assessed through a firmware-consistent replay of the recorded measurements, using the same gating, inertial propagation, and measurement-update logic as the real-time ESP32-S3 implementation. Across ten trials per configuration, the replay-based trial-mean RMSE in the 2D AGV scenarios decreased from 101.2–104.1 mm for raw ultrasonic data to 47.2–48.7 mm after fusion, while peak failure-interval errors were reduced by 64.2–65.7%. In the 3D UR10 scenarios, replay-based trial-mean RMSE decreased from 157.6–158.4 mm to 80.2–80.5 mm, and peak height-sensitive 3D errors were reduced by 58.8–60.0%. The results demonstrate the feasibility of embedded ultrasonic–inertial robustness enhancement for localization in controlled laboratory AGV and robot-arm scenarios. While the proposed approach shows promising performance under the investigated conditions, further validation is required before extending the conclusions to larger-scale and dynamically changing industrial environments. Full closed-loop online robot localization and control based directly on the fused localization output remain subjects for future investigation. Full article

The purpose of this article is to conduct a systematic literature review on the role of deep learning in credit risk prediction for fintech lending, with particular emphasis on model architectures, imbalanced data handling techniques, and the mathematical foundations underpinning these methods. Open-access scientific publications retrieved from three complementary databases (Scopus, IEEE Xplore Digital Library, and Web of Science Core Collection) were used to conduct the systematic literature review. Following the PRISMA 2020 protocol, 30 publications were selected after a rigorous multi-stage screening process involving deduplication across databases, temporal filtering (2015–2026), and thematic eligibility assessment. Data for analysis were processed using Python-based bibliometric tools and network analysis (replicating R Bibliometrix and VOSviewer functionalities). The results of the analysis indicate a sustained growth in research on deep learning applications for fintech credit risk, with a compound annual growth rate (CAGR) of approximately 29.2% and an average of 27.17 citations per document. The segmentation of the studied conceptual landscape made it possible to identify four interconnected thematic clusters: (1) peer-to-peer lending and default prediction architectures; (2) explainability and XAI-based methods for credit scoring; (3) imbalanced data and hybrid deep-learning frameworks; and (4) credit risk assessment combining deep learning and statistical approaches. The following research areas on the deep learning-based transformation of fintech credit risk prediction have been identified: (1) feedforward deep neural networks and attention-based architectures (LSTM, CNN) as dominant predictive engines; (2) hybrid deep ensemble and deep-boosting frameworks (e.g., LightGBM-Attention, GBDT-Deep FFM) as emerging high-performance paradigms; (3) specialized techniques for imbalanced data handling—including ADASYN, SMOTE, cost-sensitive learning, and balanced stratified prioritized experience replay—as critical methodological frontiers; and (4) transformer-based and XAI-integrated architectures as the emerging frontier. The originality of this article lies in its explicit focus on the mathematical and methodological challenges of deep learning-based credit risk prediction in fintech lending, providing an actionable research agenda that addresses class imbalance, uncertainty quantification, loss function design, concept drift, and regulatory compliance. The findings provide valuable insights for scholars, practitioners, and policymakers, and outline a concrete roadmap for developing more accurate, robust, and explainable credit risk models in the rapidly evolving fintech ecosystem. Full article

As global populations grow and technology advances, daily life is increasingly shaped by digital systems such as computers and smart devices. However, prolonged device use has contributed to increasing physical and mental health concerns, particularly those associated with poor sitting posture. Posture-related strain is frequently overlooked and contributes to musculoskeletal discomfort, including back, neck, shoulder, and wrist pain, and may also be associated with sleep disturbances and elevated stress levels. To the best of our knowledge and based on the existing literature, this is the first study to introduce a machine learning-based framework for advanced muscle strain severity classification using Internet of Things (IoT) devices that integrates posture monitoring and muscle strain detection into a unified low-cost framework ($23 hardware cost). The primary objective of this work is accurate classification of muscle strain severity, while real-time alerts serve as a secondary ergonomic feedback mechanism. Specifically, this study makes four major contributions. First, we created a novel dataset through real-time acquisition of electromyography (EMG) and posture signals from participants in hospital and industrial environments, capturing diverse muscle strain patterns validated against clinical assessment procedures. Second, we designed a two-part hardware architecture consisting of posture detection (PD) and strain detection (SD) modules using a NodeMCU ESP8266, HC-SR04 ultrasonic sensor, EMG sensor, and buzzer for real-time physiological monitoring, incorporating EMG-specific preprocessing including band-pass filtering, rectification, and RMS smoothing. Third, we proposed and evaluated a hybrid machine learning framework integrating Vision Transformer (ViT) and XGBoost to classify strain severity into three study-specific categories: baseline (EMG RMS < 40 µV), compensatory strain (40–59 µV), and overload (≥60 µV). These categories were used as reproducible severity proxies for machine learning annotation and should not be interpreted as universal biomarkers of structural tissue damage. Finally, the proposed framework achieved a classification accuracy of 99.0% (95% CI: 98.5–99.5%) with an inference latency of 15.2 ms. Full article

This paper presents a time-domain analysis of an N-bit pulse-width-modulated digital-to-analog converter (PWM DAC) employing a first-order passive resistor-capacitor (RC) filter. Exact analytical expressions are derived for the output settling time in both rising and decreasing digital-code transition modes. The worst-case condition is identified, and the settling-time criterion is expressed as a function of the DAC resolution N, tolerance ε, and normalized filter parameter k = T/RC. The derived criterion is compared with a commonly used first-order RC settling approximation. For N = 8 and ε = 1/4, the proposed worst-case criterion gives a discrete settling interval of 823 PWM periods, whereas the literature-based estimate gives 355 periods. The analytical results are confirmed by numerical evaluation and LTspice transient simulations and are further supported by experimental measurements obtained using a microcontroller-based PWM generator and a passive RC filter. The results confirm the duty-cycle dependence of the steady-state ripple and demonstrate that the proposed criterion provides a conservative design rule for selecting PWM DAC parameters while balancing accuracy, ripple, and settling speed. Full article

Urban environments increasingly rely on interconnected digital infrastructures like IoT devices, SDN-enabled networks, and cloud platforms to support essential municipal services. Ensuring the resilience of these systems requires advanced, data-driven mechanisms capable of detecting and mitigating cyber disruptions. This study presents Persian Eagle, a hybrid machine learning and deep learning framework designed to enhance the cyber-resilience of urban digital infrastructures by providing high-precision detection of Distributed Denial of Service (DDoS) attacks. DDoS attacks disrupt service availability by flooding targets with massive malicious traffic orchestrated through botnets, and in critical infrastructures, disruptions can be life-threatening. The proposed framework integrates multi-stage data preprocessing, SMOTE-based class balancing, and a four-phase feature-selection pipeline combining filtering, statistical ranking, PCA, and XGBoost. Seven complementary classifiers, including Random Forest, SVM, Gaussian Naive Bayes, XGBoost, MLP, LSTM, and Autoencoder, are bonded through a stacking cooperative with a Gradient Boosting meta-learner. The framework was evaluated on CICDDoS2019 and CICIDS2017 datasets, and achieved near-perfect performance up to 99.9998% accuracy, demonstrating strong generalization across diverse attack scenarios. By offering a scalable, transparent, and data-driven detection mechanism, Persian Eagle maintains urban digital-risk management and supports the continuity and resilience of critical smart-city services. Full article

Consolidated bioprocessing (CBP) is difficult to monitor because enzyme production, lignocellulose degradation, sugar release, and fermentation occur simultaneously under sparse measurement, feedstock variability, and plant–model mismatch conditions. This study proposes a computational sensor-set design framework for digital-twin-assisted CBP monitoring. A five-state virtual plant, consisting of active biomass, cellulolytic enzyme activity, residual insoluble substrate, soluble sugar, and ethanol, was used to evaluate all 16 ethanol-mandatory measurement packages formed from ethanol, sugar, biomass, enzyme, and residual-substrate proxy channels. Candidate sensor sets were assessed using finite-difference output sensitivities, Fisher-information-based state-observability and parameter-identifiability analyses, eigenvalue and parameter-correlation diagnostics, and paired Monte Carlo unscented Kalman filter soft-sensing reconstruction. Within the tested five-state virtual-plant benchmark and with the specified excitation schedule, noise assumptions, burden indices, and scoring objective, ethanol-only sensing provided the weakest support for state-aware CBP digital-twin reconstruction. At a $6\mathrm{h}$ sampling interval, the state-observability log-pseudodeterminant increased from 4.18 with ethanol-only sensing to 8.56 after adding soluble sugar and to 16.42 with full-proxy monitoring. The ethanol–sugar–biomass–substrate package also gave strong reduced state-observability performance, with log-pseudodeterminants of 15.12, 13.76, and 12.51 at 6, 12, and $24\mathrm{h}$, respectively. Biomass and enzyme proxies contributed strongly to parameter learning, and the ethanol–sugar–biomass–enzyme package gave the strongest active parameter-identifiability performance, with log-pseudodeterminants of 10.82, 9.06, and 6.67 at 6, 12, and $24\mathrm{h}$, respectively. In the paired soft-sensing analysis, full-proxy monitoring reduced the mean latent-state RMSE from 1.1899 to 0.3756, followed by ethanol–biomass–enzyme–substrate with 0.3843 and ethanol–sugar–biomass–substrate with 0.4121. The primary aggregate ranking identified ethanol–sugar–biomass–substrate as the best overall package, with a sensor-value score of 0.8432 and a burden index of 7.0, followed by full-proxy monitoring with a score of 0.8173 and a burden index of 10.0. Robustness tests showed that ethanol–sugar–biomass–substrate remained top-ranked under uniform noise scaling, full UKF missingness, delay and bias stress test conditions, most scoring-weight scenarios, and all tested sensor-specific burden workflows. Full-proxy monitoring remained a close competitor under independent sensor-specific noise variation conditions and became top-ranked for some alternative operating trajectories. The proposed framework provides a simulation-based method for prioritizing informative measurement packages before implementing CBP digital twins in laboratory and pilot-plant settings. Full article

Wearable technologies offer practical opportunities for assistive communication and educational support in introductory sign language learning. This paper presents an IoT-enabled smart glove for deterministic static sign language recognition over a bounded vocabulary of 15 isolated static gestures, comprising digits (0–9) and five vowel handshapes (A, E, I, O, U). The system is intended for foundational static gesture and posture practice and is not designed or validated for dynamic gestures, coarticulated signing, continuous sign language recognition, or sentence-level translation. The prototype integrates five 2.2-inch (55.9 mm) resistive flex sensors and an MPU6050 3-axis accelerometer, performs acquisition, exponential moving average filtering, user-specific calibration, normalization, and deterministic classification on a NodeMCU ESP32 board, and transmits selected processed variables to Arduino Cloud through MQTT for remote monitoring. A 10 s calibration routine maps user-specific open-hand and closed-fist responses into normalized flex-sensor ranges, allowing the same deterministic rule structure to operate across participants without model retraining. Experimental evaluation with 10 healthy adult participants aged 20–41 years (mean age: 27 years), all familiar with sign language and all providing written informed consent, produced a balanced dataset of 1500 labeled steady-state sensor vectors. The class-averaged recognition rate was 92.8%, and leave-one-subject-out validation produced a subject-wise accuracy of $92.80\pm 2.03\%$, with individual participant accuracies ranging from 90.00% to 96.00%. The local embedded processing pipeline required less than 2 ms per cycle, the complete path including MQTT visualization produced approximately 150 ms end-to-end latency, and the device operated for up to 14 h using a 3.7 V, 1000 mAh Li-Po battery. The results indicate that calibrated deterministic sensor fusion can provide a low-cost, low-latency, edge-executed solution for bounded static sign-language gesture learning tasks while maintaining stable short-term subject-wise performance under controlled experimental conditions. Full article

Sweep-field operation in a single-beam spin-exchange relaxation-free (SERF) magnetometer requires stable extraction of the dispersion zero-crossing. A frequency mismatch between the modulation signal and the demodulation references, or an unsuitable low-pass filter, can shift this zero-crossing and affect working-point determination. This paper presents a zero-crossing-stability-oriented FPGA quadrature lock-in module for SERF sweep-field demodulation. The module is designed around two requirements of sweep-field operation: maintaining a common frequency basis between the modulation output and the demodulation references, and preserving the dispersion zero-crossing when the low-pass-filter cutoff frequency is adjusted. A shared direct digital synthesizer generates both the sinusoidal modulation output and the I/Q references, keeping the excitation and demodulation signals on the same frequency basis. After quadrature multiplication, CIC decimation and a reloadable Kaiser-window FIR filter are used for low-pass processing. Board-level tests show a 1000.054 Hz spectral peak for a 1000 Hz setting and a loopback amplitude of 0.496 V, close to the ideal 0.500 V baseband amplitude. On the SERF platform, I/Q rotation reduces the quadrature residual ratio from 32.1% to 0.10%. When the FIR cutoff frequency is changed from 3 to 15 Hz, the maximum zero-crossing difference is about 0.58 ms, corresponding to 0.12% of the 2 Hz sweep period. These results show that the module supports stable zero-crossing extraction and working-point determination during sweep-field operation in a single-beam SERF magnetometer. Full article

This paper presents the design, modeling, and hardware implementation of a 1 MHz Gallium Nitride (GaN) quadratic boost converter. Developed as a versatile experimental shield for an STM32 microcontroller development board, the proposed hardware enables direct measurement of all state variables to facilitate the experimental evaluation of advanced control algorithms. Based on a comprehensively derived state-space model, discrete-time Voltage Mode Control (VMC) is initially analyzed, highlighting the difficulties arising from the nature of the cascaded system. During large-signal operation at 1 MHz, this simple control strategy is highly vulnerable to dangerous current surges and oscillatory transients. To mitigate these instabilities, a hybrid Peak Current Mode Control (PCMC) strategy is proposed and implemented. An inner high-speed analog loop provides cycle-by-cycle current limiting, operating the power stage as a voltage-controlled current source to provide an input current limit as protection, even during inter-sample periods, where a slower digital controller remains “blind”. The shield architecture is especially useful here, since it allows the usage of built-in high-speed comparators of the microcontroller. Furthermore, this study investigates the complications arising from executing the outer digital control loop at sampling frequencies (100 kHz and 10 kHz) substantially lower than the switching frequency. Non-linear simulations reveal that at lower sampling rates, the control effort becomes too aggressive, causing the output to oscillate around a setpoint rather than stabilize. Applying a digital filter—specifically, Exponential Moving Averaging (EMA) to the controller output—is implemented to stabilize the reference signal. Both non-linear Simulink simulations and hardware experiments validate the proposed filtered PCMC architecture. Full article

In single-phase PWM rectifiers, due to the inherent time-varying characteristics of the source voltage and current as well as the periodic operation of the converter bridge, the instantaneous input power on the AC side inevitably exhibits a twice-fundamental-frequency pulsation. This phenomenon consequently generates a double-line-frequency (100 Hz) voltage ripple on the DC-link capacitor, which causes an inherent contradiction in conventional voltage outer-loop control between steady-state ripple suppression and dynamic response speed. To address this issue, this paper proposes a control strategy based on an Adaptive Time-Delayed Feedforward Neural Network (Adaptive TD-FNN). The proposed method explicitly introduces the delayed voltage error of half a ripple period into the network state input, thereby achieving time-domain decoupling of the 100 Hz low-frequency disturbance. In addition, a physics-driven training framework is constructed by integrating the rectifier’s discrete difference equation, thereby strengthening the network’s capacity to learn the dynamic characteristics of the system. On this basis, a dynamic adaptive smoothness-weight penalty mechanism is designed to adjust the weighting factor of the current command smoothness constraint in the loss function according to the system operating state. Specifically, the penalty weight is increased under steady-state conditions to suppress command oscillations caused by ripple disturbances, while it is rapidly reduced during load or grid-voltage transients to release the network’s transient optimization capability. Simulation and experimental results show that the proposed Adaptive TD-FNN controller can simultaneously achieve smooth steady-state current command output and fast dynamic voltage regulation without introducing additional complex digital notch-filtering algorithms. Compared with conventional dual-loop control, the proposed strategy reduces the total harmonic distortion (THD) of the grid-side input current from 8.45% to 3.42%, satisfying grid-connected power quality requirements. Meanwhile, under large load transients and grid-voltage disturbance conditions, the DC-link voltage recovery time is about 40 ms, verifying the comprehensive advantages of the proposed method in ripple suppression, dynamic response, and operating-condition adaptability. Full article