Search Results (12)

The main function of triangulation-based laser profile sensors—also referred to as laser profilometers or profilers—is the three-dimensional scanning of moving objects using laser triangulation. In addition to capturing 3D data, these profilometers simultaneously generate grayscale images of the scanned objects. However, the quality of these images is often degraded due to interference of the laser light, manifesting as speckle noise. In profilometer images, this noise typically appears as vertical stripes. Unlike the column fixed pattern noise commonly observed in TDI CMOS cameras, the positions of these stripes are not stationary. Consequently, conventional algorithms for removing fixed pattern noise yield unsatisfactory results when applied to profilometer images. In this article, we propose an effective method for suppressing speckle noise in profilometer images of flat surfaces, based on local column median vectors. The method was evaluated across a variety of surface types and compared against existing approaches using several metrics, including the standard deviation of the column mean vector (SDCMV), frequency spectrum analysis, and standard image quality assessment measures. Our results demonstrate a substantial improvement in reducing column speckle noise: the SDCMV value achieved with our method is 2.5 to 5 times lower than that obtained using global column median values, and the root mean square (RMS) of the frequency spectrum in the noise-relevant region is reduced by nearly an order of magnitude. General image quality metrics also indicate moderate enhancement: peak signal-to-noise ratio (PSNR) increased by 2.12 dB, and the structural similarity index (SSIM) improved from 0.929 to 0.953. The primary limitation of the proposed method is its applicability only to flat surfaces. Nonetheless, we successfully implemented it in an optical inspection system for the furniture industry, where the post-processed image quality was sufficient to detect surface defects as small as 0.1 mm. Full article

Uncooled infrared imaging systems have significant potential in industrial hazardous gas leak detection. However, the use of narrowband filters to match gas spectral absorption peaks leads to a low level of incident energy captured by uncooled infrared cameras. This results in a mixture of fixed pattern noise and Gaussian noise, while existing denoising methods for uncooled infrared images struggle to effectively address this mixed noise, severely hindering the extraction and identification of actual gas leak plumes. This paper presents a UNet-structured dual-encoder denoising network specifically designed for narrowband uncooled infrared images. Based on the distinct characteristics of Gaussian random noise and row–column stripe noise, we developed a basic scale residual attention (BSRA) encoder and an enlarged scale residual attention (ESRA) encoder. These two encoder branches perform noise perception and encoding across different receptive fields, allowing for the fusion of noise features from both scales. The combined features are then input into the decoder for reconstruction, resulting in high-quality infrared images. Experimental results demonstrate that our method effectively denoises composite noise, achieving the best results according to both objective metrics and subjective evaluations. This research method significantly enhances the signal-to-noise ratio of narrowband uncooled infrared images, demonstrating substantial application potential in fields such as industrial hazardous gas detection, remote sensing imaging, and medical imaging. Full article

As an extension of non-negative matrix factorization (NMF), graph-regularized non-negative matrix factorization (GNMF) has been widely applied in data mining and machine learning, particularly for tasks such as clustering and feature selection. Traditional GNMF methods typically rely on predefined graph structures to guide the decomposition process, using fixed data graphs and feature graphs to capture relationships between data points and features. However, these fixed graphs may limit the model’s expressiveness. Additionally, many NMF variants face challenges when dealing with complex data distributions and are vulnerable to noise and outliers. To overcome these challenges, we propose a novel method called sparse feature-weighted double Laplacian rank constraint non-negative matrix factorization (SFLRNMF), along with its extended version, SFLRNMTF. These methods adaptively construct more accurate data similarity and feature similarity graphs, while imposing rank constraints on the Laplacian matrices of these graphs. This rank constraint ensures that the resulting matrix ranks reflect the true number of clusters, thereby improving clustering performance. Moreover, we introduce a feature weighting matrix into the original data matrix to reduce the influence of irrelevant features and apply an $L_{\mathrm{2,1}/2}$ norm sparsity constraint in the basis matrix to encourage sparse representations. An orthogonal constraint is also enforced on the coefficient matrix to ensure interpretability of the dimensionality reduction results. In the extended model (SFLRNMTF), we introduce a double orthogonal constraint on the basis matrix and coefficient matrix to enhance the uniqueness and interpretability of the decomposition, thereby facilitating clearer clustering results for both rows and columns. However, enforcing double orthogonal constraints can reduce approximation accuracy, especially with low-rank matrices, as it restricts the model’s flexibility. To address this limitation, we introduce an additional factor matrix R, which acts as an adaptive component that balances the trade-off between constraint enforcement and approximation accuracy. This adjustment allows the model to achieve greater representational flexibility, improving reconstruction accuracy while preserving the interpretability and clustering clarity provided by the double orthogonality constraints. Consequently, the SFLRNMTF approach becomes more robust in capturing data patterns and achieving high-quality clustering results in complex datasets. We also propose an efficient alternating iterative update algorithm to optimize the proposed model and provide a theoretical analysis of its performance. Clustering results on four benchmark datasets demonstrate that our method outperforms competing approaches. Full article

In order to address the inconsistency problem caused by parasitic backend wiring among multiple ramp generators and among multiple columns in large-array CMOS image sensors (CIS), this paper proposes a high-precision compensation technology combining average voltage technology, adaptive negative feedback dynamic adjustment technology, and digital correlation double sampling technology to complete the design of an adaptive ramp signals inconsistency calibration scheme. The method proposed in this article has been successfully applied to a CIS with a pixel array of 8192(H) × 8192(V), based on the 55 nm 1P4M CMOS process, with a pixel size of $10\times 10\mathsf{\mu }{\mathrm{m}}^2$. The chip area is 88(H) × 89(V) ${\mathrm{mm}}^2$, and the frame rate is 10 fps. The column-level analog-to-digital converter is a 12-bit single-slope analog-to-digital converter (SS ADC). The experimental results show that the ramp generation circuit proposed in this paper can reduce the inconsistency among the ramp signals to 0.4% LSB, decreases the column fixed pattern noise (CFPN) caused by inconsistent ramps of each column to 0.000037% (0.15 $e^{-}$), and increases the overall chip area and power consumption by only 0.6% and 0.5%, respectively. This method provides an effective solution to the influence of non-ideal factors on the consistency of ramp signals in large area array CIS. Full article

In semiconductor manufacturing, defect inspection in non-patterned wafer production lines is essential to ensure high-quality integrated circuits. However, in actual production lines, achieving both high efficiency and high sensitivity at the same time is a significant challenge due to their mutual constraints. To achieve a reasonable trade-off between detection efficiency and sensitivity, this paper integrates the time delay integration (TDI) technology into dark-field microscopy. The TDI image sensor is utilized instead of a photomultiplier tube to realize multi-point simultaneous scanning. Experiments illustrate that the increase in the number of TDI stages and reduction in the column fixed pattern noise effectively improve the signal-to-noise ratio of particle defects without sacrificing the detecting efficiency. Full article

This paper presents a comprehensive timing optimization methodology for power-efficient high-resolution image sensors with column-parallel single-slope analog-to-digital converters (ADCs). The aim of the method is to optimize the read-out timing for each period in the image sensor’s operation, while considering various factors such as ADC decision time, slew rate, and settling time. By adjusting the ramp reference offset and optimizing the amplifier bandwidth of the comparator, the proposed methodology minimizes the power consumption of the amplifier array, which is one of the most power-hungry circuits in the system, while maintaining a small color linearity error and ensuring optimal performance. To demonstrate the effectiveness of the proposed method, a power-efficient 108 MP 3-D stacked CMOS image sensor with a 10-bit column-parallel single-slope ADC array was implemented and verified. The image sensor achieved a random noise of 1.4 e⁻rms, a column fixed-pattern noise of 66 ppm at an analog gain of 16, and a remarkable figure-of-merit (FoM) of 0.71 e⁻·nJ. This timing optimization methodology enhances energy efficiency in high-resolution image sensors, enabling higher frame rates and improved system performance. It could be adapted for various imaging applications requiring optimized performance and reduced power consumption, making it a valuable tool for designers aiming to achieve optimal performance in power-sensitive applications. Full article

As the demand for thermal information increases in industrial fields, numerous studies have focused on enhancing the quality of infrared images. Previous studies have attempted to independently overcome one of the two main degradations of infrared images, fixed pattern noise (FPN) and blurring artifacts, neglecting the other problems, to reduce the complexity of the problems. However, this is infeasible for real-world infrared images, where two degradations coexist and influence each other. Herein, we propose an infrared image deconvolution algorithm that jointly considers FPN and blurring artifacts in a single framework. First, an infrared linear degradation model that incorporates a series of degradations of the thermal information acquisition system is derived. Subsequently, based on the investigation of the visual characteristics of the column FPN, a strategy to precisely estimate FPN components is developed, even in the presence of random noise. Finally, a non-blind image deconvolution scheme is proposed by analyzing the distinctive gradient statistics of infrared images compared with those of visible-band images. The superiority of the proposed algorithm is experimentally verified by removing both artifacts. Based on the results, the derived infrared image deconvolution framework successfully reflects a real infrared imaging system. Full article

With the improvement of semiconductor technology, the performance of CMOS Image Sensor has been greatly improved, reaching the same level as that of CCD in dark current, linearity and readout noise. However, due to the production process, CMOS has higher fix pattern noise than CCD at present. Therefore, the removal of CMOS fixed pattern noise has become the research content of many scholars. For current fixed pattern noise (FPN) removal methods, the most effective one is based on optimization. Therefore, the optimization method has become the focus of many scholars. However, most optimization models only consider the image itself, and rarely consider the structural characteristics of FPN. The proposed sparse unidirectional hybrid total variation (SUTV) algorithm takes into account both the sparse structure of column fix pattern noise (CFPN) and the random properties of pixel fix pattern noise (PFPN), and uses adaptive adjustment strategies for some parameters. From the experimental values of PSNR and SSM as well as the rate of change, the SUTV model meets the design expectations with effective noise reduction and robustness. Full article

For a complementary metal-oxide-semiconductor image sensor with highly linear, low noise and high frame rate, the nonlinear correction and frame rate improvement techniques are becoming very important. The in-pixel source follower transistor and the integration capacitor on the floating diffusion node cause linearity degradation. In order to address this problem, this paper proposes an adaptive nonlinear ramp generator circuit based on dummy pixels used in single-slope analog-to-digital converter topology for a complementary metal-oxide-semiconductor (CMOS) image sensor. In the proposed approach, the traditional linear ramp generator circuit is replaced with the new proposed adaptive nonlinear ramp generator circuit that can mitigate the nonlinearity of the pixel unit circuit, especially the gain nonlinearity of the source follower transistor and the integration capacitor nonlinearity of the floating diffusion node. Moreover, in order to enhance the frame rate and address the issue of high column fixed pattern noise, a new readout scheme of fully differential pipeline sampling quantization with a double auto-zeroing technique is proposed. Compared with the conventional readout structure without a fully differential pipeline sampling quantization technique and double auto-zeroing technique, the proposed readout scheme cannot only enhance the frame rate but can also improve the consistency of the offset and delay information of different column comparators and significantly reduce the column fixed pattern noise. The proposed techniques are simulated and verified with a prototype chip fabricated using typical 180 nm CMOS process technology. The obtained measurement results demonstrate that the overall nonlinearity of the CMOS image sensor is reduced from 1.03% to 0.047%, the efficiency of the comparator is improved from 85.3% to 100%, and the column fixed pattern noise is reduced from 0.43% to 0.019%. Full article

In this paper, we present a multi-resolution mode CMOS image sensor (CIS) for intelligent surveillance system (ISS) applications. A low column fixed-pattern noise (CFPN) comparator is proposed in 8-bit two-step single-slope analog-to-digital converter (TSSS ADC) for the CIS that supports normal, 1/2, 1/4, 1/8, 1/16, 1/32, and 1/64 mode of pixel resolution. We show that the scaled-resolution images enable CIS to reduce total power consumption while images hold steady without events. A prototype sensor of 176 × 144 pixels has been fabricated with a 0.18 μm 1-poly 4-metal CMOS process. The area of 4-shared 4T-active pixel sensor (APS) is 4.4 μm × 4.4 μm and the total chip size is 2.35 mm × 2.35 mm. The maximum power consumption is 10 mW (with full resolution) with supply voltages of 3.3 V (analog) and 1.8 V (digital) and 14 frame/s of frame rates. Full article

In order to eliminate the fixed-pattern noise (FPN) in the output image of time-delay-integration CMOS image sensor (TDI-CIS), a FPN correction method based on gray value compensation is proposed. One hundred images are first captured under uniform illumination. Then, row FPN (RFPN) and column FPN (CFPN) are estimated based on the row-mean vector and column-mean vector of all collected images, respectively. Finally, RFPN are corrected by adding the estimated RFPN gray value to the original gray values of pixels in the corresponding row, and CFPN are corrected by subtracting the estimated CFPN gray value from the original gray values of pixels in the corresponding column. Experimental results based on a 128-stage TDI-CIS show that, after correcting the FPN in the image captured under uniform illumination with the proposed method, the standard-deviation of row-mean vector decreases from 5.6798 to 0.4214 LSB, and the standard-deviation of column-mean vector decreases from 15.2080 to 13.4623 LSB. Both kinds of FPN in the real images captured by TDI-CIS are eliminated effectively with the proposed method. Full article

In this paper, a 120 frames per second (fps) low noise CMOS Image Sensor (CIS) based on a Two-Step Single Slope ADC (TS SS ADC) and column self-calibration technique is proposed. The TS SS ADC is suitable for high speed video systems because its conversion speed is much faster (by more than 10 times) than that of the Single Slope ADC (SS ADC). However, there exist some mismatching errors between the coarse block and the fine block due to the 2-step operation of the TS SS ADC. In general, this makes it difficult to implement the TS SS ADC beyond a 10-bit resolution. In order to improve such errors, a new 4-input comparator is discussed and a high resolution TS SS ADC is proposed. Further, a feedback circuit that enables column self-calibration to reduce the Fixed Pattern Noise (FPN) is also described. The proposed chip has been fabricated with 0.13 μm Samsung CIS technology and the chip satisfies the VGA resolution. The pixel is based on the 4-TR Active Pixel Sensor (APS). The high frame rate of 120 fps is achieved at the VGA resolution. The measured FPN is 0.38 LSB, and measured dynamic range is about 64.6 dB. Full article