Search Results (10)

Build systems become an indispensable part of the software implementation and deployment process. New programming languages are released with the build system integrated into the language tools, for example, Go, Rust, or Zig. However, in the hardware description domain, no official build systems have been released with the predominant Hardware Description Languages (HDL) such as VHDL or SystemVerilog. Moreover, hardware design projects are often multilingual. This paper characterizes and compares two common approaches for hardware build system implementations. The first one is the direct-Tcl approach, in which the build system code is executed directly by the EDA tool during the design build flow. The second one is the indirect-abstract approach, in which the build system produces a Tcl script, which is later run by a proper EDA tool. As none of the existing direct-Tcl build systems were close to the indirect-abstract build systems in terms of supported functionalities, this paper also presents a new direct-Tcl hardware build system called HBS. The implemented build system was used as a representative of direct-Tcl build systems in comparison with indirect-abstract build systems. The main goals of the system include simplicity, readability, a minimal number of dependencies, ease of integration with the existing EDA tools, and independence from version control systems. The system provides a broad design automation, including support for multiple synthesis EDA tools, listing automatically detected cores and targets, automatic testbench targets detection, parallel testbench running, and dependency graph generation. Full article

Today, the development of electrified commercial vehicles requires efficient validation methods that enable early system testing while maintaining consistency between development and testing models. Hardware-in-the-Loop (HiL) testing provides a suitable approach by combining real hardware with executable real-time simulation models. However, HiL models are typically created manually for specific test cases, resulting in high modeling effort and limited reuse of development knowledge. This paper presents a methodology for the automated synthesis of executable, test-specific system-level HiL simulation models from predefined and reusable simulation components based on function-oriented SysML system architecture models. The approach combines filtering of architectural data, automated analysis of model availability and parameter completeness and configurable selection of the desired model fidelity. Reusable simulation components aligned with the system architecture are automatically selected, parametrized, connected, and aggregated into executable Simulink HiL models including test-bench interfaces. The methodology was validated for three electrified vehicle architectures and deployed on a dSPACE-based HiL test bench for drivetrain functionality and range analyses. The generated system-level HiL models were created in a few seconds while maintaining consistency with the central MBSE system architecture. Full article

Ensuring functional correctness in digital circuitry is arguably the most labor-intensive stage of hardware creation, routinely accounting for upwards of 70% of a project’s total resource allocation. While traditional coverage-driven verification (CDV) attempts to validate every operational state, reaching full coverage closure via manual intervention or constrained–random techniques requires significant engineering time and domain knowledge. To overcome this bottleneck, this study introduces an automated testing architecture that leverages the Advantage Actor–Critic (A2C) Reinforcement Learning (RL) algorithm. This agent intelligently navigates functional coverage closure across five diverse hardware designs: an Advanced Peripheral Bus Universal Asynchronous Receiver-Transmitter (APB UART), an Serial Peripheral Interface (SPI) Memory unit, a synchronous First-In First-Out (FIFO) queue, an APB RAM, and an Advanced High-performance Bus (AHB) Slave interface. By interfacing QuestaSim 2024.1 with a Python-based intelligent agent via a SystemVerilog DPI-C socket, the system dynamically produces test vectors informed by real-time coverage metrics. Based on evaluations across five distinct random seeds, the methodology successfully attains 95.1% to 100% coverage across all testbenches, with three designs achieving 100% and two reaching 95–98%. Notably, the RL-guided system achieved target coverage using approximately 35% fewer simulation cycles than an unguided random baseline, and 22% fewer cycles compared to a traditional constrained–random setup utilizing expert-defined rules. Ultimately, this framework bypasses the necessity for manual constraint formulation and seamlessly scales to novel hardware environments with negligible setup overhead. Full article

Peripheral Component Interconnect Express (PCIe) is a critical interface for FPGA-based accelerators, yet existing controller solutions are often proprietary, costly, and/or incompatible with open-source workflows. We present a fully open-source PCIe controller, written in synthesizable Verilog and optimized for Field-Programmable Gate Array (FPGA) deployment. The core is verified using a Python-based cocotb_2.0.1 and pyuvm_4.0.0 testbench with a modeled Root Complex (RC), complete with data packet generation, automated checks for enumeration, flow control, and retry mechanisms. On an AMD Xilinx AC701 (XC7A200T), the design achieves less than 6% LUT utilization, timing closure at 100 MHz user clock, and demonstrates compatibility with vendor transceivers. Reference builds also meet timing on Altera Agilex devices with similar resource utilization. All RTL, verification infrastructures, and example designs are publicly released, enabling reproducible research and accelerating the development of PCIe-enabled systems for high-speed data acquisition, NVMe front-ends, and custom FPGA accelerators. Full article

This paper proposes a new Unified Namespace (UNS)-based architecture to improve predictive and prescriptive maintenance of industrial equipment and overcome challenges such as incomplete data, poor interoperability, and disconnected IT/OT environments. The framework combines interoperable data formats in real-time sensor data, predictive modeling, prescriptive analytics, and simulations of digital twins, using UNS as a centralized, protocol-agnostic data layer that is scalable and complies with Industry 4.0 and Pharma 4.0 standards. The suggested methodology increases data accessibility, reduces integration complexity, and allows low-latency analytics and automated decision-making. Machine learning predictive models achieved more than 94% accuracy in predicting equipment failures. Prescriptive analytics provides maintenance recommendations to reduce downtime and risks. The feedback loops of digital twins can enhance the accuracy of predictions and allow decision optimization through what-if analysis. A test-bench deployment showed a higher performance compared to traditional point-to-point integration, with lower latency (approximately 18 ms vs. approximately 31 ms), decreasing packet loss (0.40% vs. 3.11%), and higher model accuracy (94.20% vs. 87.51%). The structure avoided more than 4000 simulated breakdowns in the test-bench environment, indicating dependability. The study connects the theoretical applications of the UNS with the actual maintenance processes and provides a sound approach to the industrial analytics and optimization of the equipment. Full article

Gas bubbles are one of the main disturbances encountered when dispensing drugs of microliter volumes using portable miniaturized systems based on piezoelectric diaphragm micropumps. The presence of a gas bubble in the pump chamber leads to the inaccurate administration of the required dose due to its impact on the flowrate. This is particularly important for highly concentrated drugs such as insulin. Different types of sensors are used to detect gas bubbles: inline on the fluidic channels or inside the pump chamber itself. These solutions increase the complexity, size, and cost of the microdosing system. To address these problems, a radically new approach is taken by utilizing the sensing capability of the piezoelectric diaphragm during micropump actuation. This work demonstrates the workflow to build a self-sensing micropump based on artificial intelligence methods on an embedded system. This is completed by the implementation of an electronic circuit that amplifies and samples the loading current of the piezoelectric ceramic with a microcontroller STM32G491RE. Training datasets of 11 micropumps are generated at an automated testbench for gas bubble injections. The training and hyper-parameter optimization of artificial intelligence algorithms from the TensorFlow and scikit-learn libraries are conducted using a grid search approach. The classification accuracy is determined by a cross-training routine, and model deployment on STM32G491RE is conducted utilizing the STM32Cube.AI framework. The finally deployed model on the embedded system has a memory footprint of 15.23 kB, a runtime of 182 µs, and detects gas bubbles with an accuracy of 99.41%. Full article

Incremental nonlinear dynamic inversion (INDI) is a widely used approach to controlling UAVs with highly nonlinear dynamics. One key element of INDI-based controllers is the control allocation realizing pseudo controls using available actuators. However, the tracking of commanded pseudo controls is not the only objective considered during control allocation. Since the approach only works locally due to linearization and the solution is often ambiguous, additional aspects like control efforts or penalizing the deviation of certain states must be considered. Conducting the control allocation by solving a quadratic program this results in a considerable number of weighting parameters, which must be tuned during control design. Currently, this is conducted manually and is therefore time consuming. An automated approach for tuning these parameters is therefore highly beneficial. Thus, this paper presents and evaluates a model-based approach automatically tuning the control allocation parameters of a tiltrotor VTOL using an optimization algorithm. This optimization algorithm searches for optimal parameters minimizing a cost functional that reflects the design target. This cost functional is calculated based on a test mission for the VTOL which is conducted within a simulation environment. The test mission represents the common operating range of the VTOL. The simulation environment consists of an aircraft model as well as a model of the INDI-based controller which is dependent on the control allocation parameters. On this basis, model-based optimization is conducted and the optimal parameters are identified. Finally, successful real-world tests on a 4-degrees-of-freedom testbench using the identified parameters are presented. Since the control allocation parameters can significantly influence the aircraft’s stability, the 4-DOF testbench for the aircraft is required for rapid validation of the parameters at a minimum amount of risk. Full article

The Cache plays an important role in computer architecture by reducing the access time of the processor and improving its performance. The hardware design of the Cache is complex and it is challenging to verify its functions, so the traditional Verilog-based verification method is no longer applicable. This paper proposes a comprehensive and efficient verification testbench based on the SystemVerilog language and universal verification methodology (UVM) for an instruction Cache (I-Cache) controller. Corresponding testcases are designed for each feature of the I-Cache controller and automatically executed using a python script on an electronic design automation (EDA) tool. After simulating a large number of testcases, the statistics reveal that the module’s code coverage is 99.13%. Additionally, both the function coverage and the assertion coverage of the module reach 100%. Our results demonstrate that these coverage metrics meet the requirements and ensure the thoroughness of function verification. Furthermore, the established verification testbench exhibits excellent scalability and reusability, making it easily applicable to higher-level verification scenarios. Full article

The paper presents the developed fiber-optic sensors for monitoring pressure measurement on the elements of mine supports. The sudden destruction of the support leads to the collapse of the mine workings and poses a serious threat to the life and safety of underground workers. A fiber-optic system for monitoring changes in pressures on the elements of mine supports will increase the share of mining automation and reduce the share of manual labor, as well as eliminate measurement errors associated with the human factor. Systematic monitoring of the state of the working elements of the support will allow timely tracking of their deformations caused by an increase in rock pressure on them. Implementation of the system at mining enterprises will expand the use of digital technologies in mining. Timely warning of a mine collapse threat will significantly increase the level of safe mining operations, as well as reduce the cost of supporting mine workings, since elimination of the consequences of destruction is associated with significant material costs. This work presents a developed laboratory testbench that simulates a mine working and elements of an arch support on which are installed the fiber-optic sensors connected to an automated measuring system. The developed hardware and software complex provides the processing of a light spot falling on the surface of a television matrix that is installed at the exit from the optical fiber. The results of visual processing are converted into numerical values, which are used to make a decision about the state of the considered object. In addition to automatic monitoring of the structural integrity condition of the considered object, the system is equipped with a function of a visual display for monitoring results, which makes it possible to track sharp fluctuations and bursts of pressure parameters, based on which the prediction of pre-emergency and emergency situations is performed. Full article

Batteryless Internet-of-Things (IoT) devices need to schedule tasks on very limited energy budgets from intermittent energy harvesting. Creating an energy-aware scheduler allows the device to schedule tasks in an efficient manner to avoid power loss during execution. To achieve this, we need insight in the Worst-Case Energy Consumption (WCEC) of each schedulable task on the device. Different methodologies exist to determine or approximate the energy consumption. However, these approaches are computationally expensive and infeasible to perform on all type of devices; or are not accurate enough to acquire safe upper bounds. We propose a hybrid methodology that combines machine learning-based prediction on small code sections, called hybrid blocks, with static analysis to combine the predictions to a final upper bound estimation for the WCEC. In this paper, we present our work on an automated testbench for the Code Behaviour Framework (COBRA) that measures and profiles the upper bound energy consumption on the target device. Next, we use the upper bound measurements of the testbench to train eight different regression models that need to predict these upper bounds. The results show promising estimates for three regression models that could potentially be used for the methodology with additional tuning and training. Full article