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Emerging Issues in Hardware and IC System Security
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Emerging Issues in Hardware and IC System Security

A special issue of Chips (ISSN 2674-0729).

Deadline for manuscript submissions: 30 November 2026 | Viewed by 2040

Special Issue Editor

Dr. Zain Ul Abideen

E-Mail Website
Guest Editor
Department of Electrical and Computer Engineering, University of Idaho, 875 Perimeter Drive MS 1023, Moscow, ID 83844-1023, USA
Interests: hardware security; secure ASIC design; PUFs; TRNGs; post-quantum cryptography; reliable and fault-tolerant systems; ML/AI-assisted chip design; side-channel attacks

Special Issue Information

Dear Colleagues,

Recently, there has been a significant increase in attacks targeting hardware and its supply chains. These threats have revealed shortcomings in our current solutions. Despite decades of threat analysis, modeling, and prevention efforts, we continue to face challenges in defending against innovative adversaries. This Special Issue aims to solicit novel contributions from the fields of hardware and systems security that expose emerging threats, investigate practical threat models, explore novel hardware defenses, or automate the analysis of solutions.

We welcome papers addressing (but not limited to) the following topics of interest:

  • Side-channel and fault injection attacks, as well as their countermeasures;
  • Cryptographic hardware and reconfigurable-based obfuscation;
  • Hardware security primitives;
  • Security of heterogeneous chiplets;
  • Secure CAD tools and zero root-of-trust;
  • Hardware fuzzing;
  • Security-oriented hardware design;
  • Security for CPS (Cyber–Physical Systems) and IoT (Internet of Things) devices;
  • AI/ML (Artificial Intelligence/Machine Learning) hardware security.

Dr. Zain Ul Abideen
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 250 words) can be sent to the Editorial Office for assessment.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Chips is an international peer-reviewed open access quarterly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1000 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • side-channel and fault injection attacks
  • cryptographic hardware and reconfigurable-based obfuscation
  • hardware security
  • security of heterogeneous chiplets
  • secure CAD tools and zero root-of-trust
  • hardware fuzzing
  • security-oriented hardware design
  • security for CPS and IoT devices
  • artificial intelligence/machine learning

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  • Greater discoverability: Special Issues support the reach and impact of scientific research. Articles in Special Issues are more discoverable and cited more frequently.
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  • Reprint: MDPI Books provides the opportunity to republish successful Special Issues in book format, both online and in print.

Further information on MDPI's Special Issue policies can be found here.

Published Papers (2 papers)

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Research

16 pages, 4838 KB  
Article
Exploring Accelerated Aging Stress for Physical Unclonable Function Self-Corruption
by Eric Hunt-Schroeder and Tian Xia
Chips 2025, 4(4), 48; https://doi.org/10.3390/chips4040048 - 11 Nov 2025
Viewed by 461
Abstract
Silicon-Based Physical Unclonable Functions (PUFs) exploit inherent manufacturing variations to produce a unique, random, and ideally unclonable secret key. As electronic devices are decommissioned and sent for End of Life (EOL) recycling, the encrypted critical program information remains within the device. However, conventional [...] Read more.
Silicon-Based Physical Unclonable Functions (PUFs) exploit inherent manufacturing variations to produce a unique, random, and ideally unclonable secret key. As electronic devices are decommissioned and sent for End of Life (EOL) recycling, the encrypted critical program information remains within the device. However, conventional PUFs remain vulnerable to invasive attacks and reverse engineering that with sufficient time, resources, and effort can enable an adversary to bypass the security enclave of the system and extract this secret data. Recent research has started to explore techniques to respond to tamper attempts using electromigration (EM) and time-dependent dielectric breakdown (TDDB) to the PUF entropy source, preventing future authentication attempts with well-known semiconductor reliability failure mechanisms. This work presents a Pre-Amplifier Physical Unclonable Function (Pre-Amp PUF) with a self-corruption function designed and manufactured in a 3 nm FinFET technology. This PUF can perform a destructive read operation as an EOL anti-counterfeit measure against recycled and reused electronics. The destructive read utilizes an accelerated aging technique that exploits both Hot Carrier Injection (HCI) and Bias Temperature Instability (BTI) degradations directly at the PUF entropy source bitcell data. This work demonstrates a silicon proven ability to irreversibly corrupt the encryption key, invalidating the PUF key, and blocking future authentication attempts. By utilizing HCI and BTI aging effects rather than physical damage a PUF that can self-corrupt its own key without being detectable with imaging techniques is demonstrated for the first time. A feedback loop enables corruption of up to ~30% of the PUF entropy source, which is approximately 3× more data corruption than the prior state of the art self-corrupting PUF. Our technique reuses on-chip stable (repeatable) PUF bitcells identifying circuitry and thereby minimizes the area overhead to support this differentiated feature. Full article
(This article belongs to the Special Issue Emerging Issues in Hardware and IC System Security)
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15 pages, 1412 KB  
Article
Triggered Hardware Trojan Detection in IP Cores for Ensuring Safety in Cyber Physical Systems
by Mahfuzur Rahman Talukder, Md. Eftekhar Alam, Abu Monsur Mohammah Fahim and Fakir Sharif Hossain
Chips 2025, 4(4), 47; https://doi.org/10.3390/chips4040047 - 11 Nov 2025
Viewed by 954
Abstract
Cyber physical systems (CPSs) increasingly depend on complex hardware IP cores to perform critical functions. However, triggered hardware Trojans’ stealthy, malicious modifications activated under rare conditions pose significant threats to the safety and reliability of these systems. This research paper introduces a novel [...] Read more.
Cyber physical systems (CPSs) increasingly depend on complex hardware IP cores to perform critical functions. However, triggered hardware Trojans’ stealthy, malicious modifications activated under rare conditions pose significant threats to the safety and reliability of these systems. This research paper introduces a novel detection framework that integrates multi-modal side-channel analysis with trigger-aware machine learning to identify Trojans embedded within IP cores. A lightweight runtime monitoring mechanism enables real-time Trojan detection while adhering to the stringent safety constraints of CPSs. To further strengthen resilience, cryptographic integrity verification and dynamic mitigation through partial reconfiguration are incorporated. Experimental validation on two representative IP cores, AES-128 and RS232, demonstrates the framework’s effectiveness by achieving high detection accuracy (over 96%) with minimal hardware overhead (<3% LUT utilization) and latency increase of 4.95%. It can also be seen that our trigger-aware methodology more than doubles the toggling probability of rare Trojan trigger nets compared to conventional approaches. Furthermore, results from FPGA prototypes and standard Trojan benchmarks confirm the effectiveness of the proposed framework, and the proposed approach achieves high detection accuracy with minimal resource and performance penalties. This work advances the state of the art in securing CPS hardware against Trojan-based attacks. Full article
(This article belongs to the Special Issue Emerging Issues in Hardware and IC System Security)
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