A Comprehensive Design Flow of D-Band Analog Receiver Blocks for 5G Backhauling in SiGe BiCMOS Technology
, Lorenzo Piotto 2, Andrea Mazzanti 3, Pasquale Tommasino 1,* and Alessandro Trifiletti 1
Round 1
Reviewer 1 Report
Comments and Suggestions for AuthorsI read this paper with potential interest. However, I think I am not satisfied with what have been presented. The level of presentation may be underrepresented, or theme is not clarified. I pose my rationales below, and trust authors are going to revise their paper based on these, and resubmit.
How does the proposed systematic design flow fundamentally change the trade-off between design efficiency and accuracy when operating at D-band frequencies, compared to traditional RF/ mm-wave design approaches?
Given the critical impact of parasitic extraction on frequency accuracy, what limitations does the proposed flow still face as frequencies approach or exceed 165 GHz, and how might these limitations affect scalability to higher bands (e.g., sub-THz systems)?
In the context of high-order modulation schemes such as 256-QAM, how do topology choices (e.g., common-emitter vs. cascode) influence system-level metrics like BER and EVM beyond simple gain and bandwidth considerations?
To what extent can the proposed design flow be generalized across different SiGe BiCMOS technology nodes or even CMOS processes, given the strong dependence on accurate modeling of active and passive parasitics?
Considering the observed frequency down-shift between simulation and measurement, how should future receiver design methodologies balance model complexity, layout effort, and iterative prototyping to ensure first-time-right designs at D-band?
Figure captions need thorough revision, clarification stating what is exactly shown.
Most importantly, authors did not properly cited the background literature. Neither discussed them. Only a mere citations provided. I am highly surprised.
Author Response
I read this paper with potential interest. However, I think I am not satisfied with what have been presented. The level of presentation may be underrepresented, or theme is not clarified. I pose my rationales below, and trust authors are going to revise their paper based on these, and resubmit.
Comment 1: How does the proposed systematic design flow fundamentally change the trade-off between design efficiency and accuracy when operating at D-band frequencies, compared to traditional RF/ mm-wave design approaches?
Response 1: We thank the reviewer for this comment: indeed the proposed design flow does not change the trade-off, simply allows for a systematic approach to the design of D-band blocks, also exploiting the use of previously proposed solutions and topologies as remarked in lines 128-132.
Comment 2: Given the critical impact of parasitic extraction on frequency accuracy, what limitations does the proposed flow still face as frequencies approach or exceed 165 GHz, and how might these limitations affect scalability to higher bands (e.g., sub-THz systems)?
Response 2: We thank the reviewer for this comment. The approach can be extended if both the accuracy of design kit models provided by the foundry, and parasitics simulation is sufficient for sub-THz systems. For what concerns simulation accuracy (in charge to the designer) finer meshing of the circuit in EM simulation is needed. For active devices, parasitics related to connection of the intrinsic device (modelled by the foundry) to the contact metal need accurate evaluation: in this work, a lumped R-C coupled model was extracted for connection to the contact metal but most probably it is not sufficiently accurate, as demonstrated by the frequency downshift: most probably, also for the active device at D-band (and of course at sub-THz frequencies) EM parasitics extraction has to be carried-out.
Comment 3: In the context of high-order modulation schemes such as 256-QAM, how do topology choices (e.g., common-emitter vs. cascode) influence system-level metrics like BER and EVM beyond simple gain and bandwidth considerations?
Response 3: Thank you for pointing this out. Of course linearity of the block is essential and related to the chosen modulation format. This point is now explained in lines 104-108.
Comment 4: To what extent can the proposed design flow be generalized across different SiGe BiCMOS technology nodes or even CMOS processes, given the strong dependence on accurate modeling of active and passive parasitics?
Response 4: The success of the proposed design flow strongly depends on parasitics modelling, but it is general: under the hypothesis of accurate modelling, the approach can be extended to different nodes or processes.
Comment 5: Considering the observed frequency down-shift between simulation and measurement, how should future receiver design methodologies balance model complexity, layout effort, and iterative prototyping to ensure first-time-right designs at D-band?
Response 5: Thank you very much for your comment. Further investigations are needed, but in our opinion a first prototyping is needed for a new technology node only to assess models (mainly the mesh size and accuracy of lumped models for HBT parasitics) and check their accuracy. Design and results carried out in the framework of the SHIFT project and presented in the paper had the main purpose to check models and assess the design flow.
Comment 6: Figure captions need thorough revision, clarification stating what is exactly shown.
Response 6: Yes, that's true. In the revised version, we've tried to improve the clarity of the captions.
Comment 7: Most importantly, authors did not properly cited the background literature. Neither discussed them. Only a mere citations provided. I am highly surprised.
Response 7: We thank the reviewer for this suggestion. We have tried to better discuss the methodology and topological solutions proposed in background literature (lines 69-78) and to relate them to the proposed design flow (lines 128-131).
Author Response File: 
Author Response.pdf
Reviewer 2 Report
Comments and Suggestions for AuthorsTackling the design of a D-band receiver is a very commendable challenge, so I consider the work to be potentially of great interest, but I think it would be helpful to clarify some concepts, which appear quite confusing now. Those implemented functions are not completely new, but authors claim to define a complete flow, which in my opinion should be more detailed.
-In figure 2 you describe what you call a single frequency equivalent model of the composite device. At first glance, it could be considered the small-signal equivalent circuit of a field-effect transistor but I understand that the authors want to represent a cascode of bipolar transistors in a small signal regime. Nevertheless, pins are labeled B base C collector E emitter, which is a bit confusing. The use of this equivalent model later in the procedure is not well explained.
-The referred equivalent model could be useful for LNA simulation, as it is small signal, but not for mixing simulation, which requires large signal models to account for LO pumping modifying strongly transistor bias points. You mention CADENCE environment. I understand that you used Spectre tool. You mention EM simulations of passive parts (EMX?). All those points should be better explained.
-Moreover, how did you extracted and checked suitable models of HBTs to operate in D band in small and in large signal? Are you based on models provided by the foundry libraries? Modeling of devices in D band would require a devoted section. An improper modeling may be quite related to the downshifted response you mention, otherwise quite common in those high frequencies.
-About the down conversion I miss a definition of the LO, RF and IF frequencies. It is not clear in LO is really LO/2. You mention a multiplier, but I suppose is external. Otherwise the mixer would be a sub-harmonically pumped mixer.
-In figure 5 scheme of the down converter mixer circuit is shown. I do not understand the correspondence of LO, RF and IF labels with the pins in the circuit. Usually one could expect LO applied in what you call RFin, RF applied in “IF balun out” and IF extracted from “LO balun in”, or maybe interchange RF and LO, but It is not clear why an E band balun is required for IF. You should also clarify the operation mode of the mixer (balanced?) and if it is conceived for cancelling LO noise, image frequency, etc. which is not clear at all.
-About the results I understand that conversion gain includes LNA gain. Noise of the LNA is not measured? Based on the measured LNA gain, could you indicate estimated conversion losses and compare with simulations?. It would be of interest to show an output spectrum to appreciate for example LO rejection. Also RF LO and IF frequency values should be defined in each measurement.
-Yield results, at least simulated would be also of interest, as well as information about foundry process (Ft, critical lengths, available models, etc. ) for potential interested readers.
Author Response
Tackling the design of a D-band receiver is a very commendable challenge, so I consider the work to be potentially of great interest, but I think it would be helpful to clarify some concepts, which appear quite confusing now.
Comment 1: Those implemented functions are not completely new, but authors claim to define a complete flow, which in my opinion should be more detailed.
Response 1: We thank the reviewer for this suggestion, indeed the description was too succinct. We have tried to explain the proposed design flow by adding more details, as you can see in lines 103-170. In particular, the second step has been split into more detailed sub-steps in this revised version: firstly, passive components are added to the composite active device; then, the single-frequency model is evaluated, and a paper-and pencil calculation of resonant load component is carried-out; finally, performance of the designed core is evaluated by full simulation.
Comment 2: In figure 2 you describe what you call a single frequency equivalent model of the composite device. At first glance, it could be considered the small-signal equivalent circuit of a field-effect transistor but I understand that the authors want to represent a cascode of bipolar transistors in a small signal regime. Nevertheless, pins are labeled B base C collector E emitter, which is a bit confusing. The use of this equivalent model later in the procedure is not well explained.
Response 2: We thank the reviewer for this comment. The single-frequency equivalent model shown in Fig. 2 represents the small-signal behavior of a circuit at the central operating frequency: during the step 2, the circuit is used for pencil-and-paper evaluation of resonant load parameters. It could be a single device, a cascode device, or a stack of common-base transistors, and also it could contain passive components (inductors or zero-ohm lines at the base of the common base of a cascode topology, inductive or resistive degeneration at the emitter side, …), as explained in lines 136-146. Indeed, labels B, C, and E are confusing and have been removed from Figure 2. Parameters Rin, Cin, Rout, Cout of the single-frequency model of the core designed during the step 3 are also used in step 4 for the design of matching networks, as detailed in lines 201-207.
Comment 3: The referred equivalent model could be useful for LNA simulation, as it is small signal, but not for mixing simulation, which requires large signal models to account for LO pumping modifying strongly transistor bias points. You mention CADENCE environment. I understand that you used Spectre tool. You mention EM simulations of passive parts (EMX?). All those points should be better explained.
Response 3: Thank you for pointing this out. Indeed, for the frequency conversion simulation, non-linear models provided by the foundry has been used, as now highlighted in lines 163-165. We used of course Spectre and EMX, as now clarified in lines 219-221.
Comment 4: Moreover, how did you extracted and checked suitable models of HBTs to operate in D band in small and in large signal? Are you based on models provided by the foundry libraries? Modeling of devices in D band would require a devoted section. An improper modeling may be quite related to the downshifted response you mention, otherwise quite common in those high frequencies.
Response 4: Thank you for pointing this out. We have used models provided by the foundry for the design. A simple single-frequency model has been introduced and used mainly in step 2 for pencil-and-paper design of the resonant load, and also in step 4 for matching network design.
Comment 5: About the down conversion I miss a definition of the LO, RF and IF frequencies. It is not clear in LO is really LO/2. You mention a multiplier, but I suppose is external. Otherwise the mixer would be a sub-harmonically pumped mixer.
Response 5: We agree with this comment: indeed the frequency multiplier is external. It is now pointed out in line 335.
Comment 6: In figure 5 scheme of the down converter mixer circuit is shown. I do not understand the correspondence of LO, RF and IF labels with the pins in the circuit. Usually one could expect LO applied in what you call RFin, RF applied in “IF balun out” and IF extracted from “LO balun in”, or maybe interchange RF and LO, but It is not clear why an E band balun is required for IF. You should also clarify the operation mode of the mixer (balanced?) and if it is conceived for cancelling LO noise, image frequency, etc. which is not clear at all.
Response 6: Thank you very much for your comment, Figure 5 of course was wrong… The input of the differential pair is the LO signal, the output is the IF signal. For the choice of mixer topology, please see the comment below.
Comment 7: About the results I understand that conversion gain includes LNA gain. Noise of the LNA is not measured? Based on the measured LNA gain, could you indicate estimated conversion losses and compare with simulations?. It would be of interest to show an output spectrum to appreciate for example LO rejection. Also RF LO and IF frequency values should be defined in each measurement.
Response 7: Thank you for pointing this out. No, the instrumentation available in the Tor Vergata laboratories was not able to provide reliable noise measurements. Evaluation of the mixer loss has been added in lines 348-352, and compared to simulated results shown in Figure 6. For what concerns your comment on the down-converter spectrum, this was a preliminary design to test the technology and the design flow, and a very simple single-balanced mixer was used. Indeed, LO rejection is very poor, as expected. In the final design, a Gilbert cell topology was exploited for the mixer and much better simulated results have been obtained. We are still waiting for dies to perform new measurements.
Comment 8: Yield results, at least simulated would be also of interest, as well as information about foundry process (Ft, critical lengths, available models, etc. ) for potential interested readers.
Response 8: Thank you for your suggestions. Indeed, we carried-out post-layout PVT simulations. Lines 260-263 and Table 1 have been added to show to the Reader the results of PVT simulations for the low-band LNA. Information about fT and fMAX has been added in line 297.
Author Response File: Author Response.pdf
Reviewer 3 Report
Comments and Suggestions for AuthorsThis work presents a systematic flow for the design of the basic building blocks (the low-15
noise amplifier and the down-converting mixer) of an analog receiver for 5G backhauling 16
systems using SiGe BiCMOS technology. The testing results are good.
1） What is the parameters of equivalent model of the (composite) active device in fig.2 in your design?
2) what is the k factor of the lna? how to optimize it ?
3) what is the q of the cap in the lna design
4) in the testing result, do authors measure the temperature effects ?
Author Response
This work presents a systematic flow for the design of the basic building blocks (the low-15 noise amplifier and the down-converting mixer) of an analog receiver for 5G backhauling 16 systems using SiGe BiCMOS technology. The testing results are good.
Comment 1: What is the parameters of equivalent model of the (composite) active device in fig.2 in your design?
Response 1: We thank the reviewer for this comment. The single-frequency equivalent model shown in Fig. 2 represents the small-signal behavior of the (composite) active device extracted from simulations at the target central operating frequency. The model includes the transconductance (gm), the output resistance (Rout) and capacitance (Cout) based on a parallel connection, similarly the input resistance (Rin) and capacitance (Cin), and account for small-signal behavior of the circuit. These parameters are obtained by biasing the devices at the selected operating current density and performing S-parameter simulations. The values of gm, Rin and Cin, Rout and Cout are then derived from the simulated Y-parameters at the design frequency and used for the analytical design of the tuned load and matching networks.
A clarification of the equivalent model parameters and their extraction procedure has been added in Section 2 of the revised manuscript in lines 136-146.
Comment 2: what is the k factor of the lna? how to optimize it?
Response 2: The stability of the proposed LNAs has been evaluated through the stability factor (K-factor) obtained from S-parameter simulations. The simulated results show that the LNA is unconditionally stable (K > 1) over the entire operating frequency range of interest and beyond the D-band. The stability optimization was achieved through proper design of the input and output matching networks, by exploiting the intrinsic losses of the matching elements and device parasitics. Moreover, the use of a cascode topology improves reverse isolation, further enhancing circuit stability. A brief discussion on the stability analysis and the simulated K-factor has been added in Section 3.1 of the revised manuscript in lines 246-252.
Comment 3: what is the q of the cap in the lna design
Response 3: The capacitors used in the LNA design are integrated MIM capacitors provided by the technology design kit. According to PDK specifications and EM-assisted simulations, the quality factor (Q) of these capacitors is approximately in the range of 20 to 40 within the D-band frequency range (130–165 GHz), depending on the capacitance value and layout configuration. This clarification has been added in Section 3.1 of the revised manuscript in lines 300-304.
Comment 4: in the testing result, do authors measure the temperature effects?
Response 4: All experimental measurements reported in this work were performed at room temperature, and temperature-dependent effects were not experimentally characterized in this measurement campaign. However, temperature variations were considered at the simulation level through PVT analyses to verify the robustness of the proposed designs, and have been added in Section 3 of the revised manuscript in lines 260-263 and in Table 1.
Author Response File: Author Response.pdf
Reviewer 4 Report
Comments and Suggestions for Authorssee attached file
Comments for author File: Comments.pdf
Author Response
This work presents a systematic flow for the design of the basic building blocks of an analog receiver for 5G backhauling systems using SiGe BiCMOS technology. It contains some interesting points valuable to readers working in this field, but several key issues should be addressed.
Comment 1: In Section I, array transceivers like doi: 10.1109/LED.2021.3059781 could also be included after ref. 4.
Response 1: We thank the reviewer for the careful reading of the manuscript and for the constructive comments, which helped us to improve the quality and clarity of the paper. We agree with the reviewer that array-based transceivers represent an important research direction for D-band systems. However, the suggested reference (doi: 10.1109/LED.2021.3059781) presents a transceiver designed in CMOS technology, and we have only mentioned BiCMOS-based papers.
Comment 2: For the design-flow, how the level of ‘comprehensive’ is defined could be further clarified in this section.
Response 2: In the revised manuscript, we have clarified the meaning of “comprehensive” by explicitly stating that the proposed design-flow spans all the main stages of receiver block development, starting from device sizing and bias optimization, through core circuit synthesis, layout generation, EM-based parasitic extraction, matching network design, and finally post-layout verification including PVT and Monte Carlo analyses. This clarification (lines 86-89) highlights that the flow is not limited to schematic-level design, but includes layout-aware and parasitic-aware steps up to measurement comparison.
Comment 3: In Fig. 2, what the significance of this single frequency equivalent model is could be further explained.
Response 3: We have expanded the explanation associated with Fig. 2 (lines 136-146) to better emphasize the role of the single-frequency equivalent model. Specifically, we clarified that this model is used as an intermediate abstraction that captures the dominant small-signal behavior of the (composite) active device at the target frequency, enabling analytical design of tuned loads and matching networks. Although it does not account for broadband effects such as feed-through capacitances, it provides sufficient accuracy for narrowband D-band block synthesis and significantly simplifies the initial design steps.
Comment 4: For the frequency derivation, works like doi: 10.1088/1674-1056/ab3e44 could be referred as to enhance the technical impact of the study.
Response 4: We thank the reviewer for the suggestion. However, the suggested reference (doi: 10.1088/1674-1056/ab3e44) deals with analysis and characterization of a led-emitting diode integrated in a CMOS technology. Even if this reference could help to further contextualize the single-frequency model, in our opinion the application is too far from the one presented in our work.
Comment 5: In Fig. 4, how the 2-finger 4 μm dimension effect on the Transition frequency could be further analyzed in detail.
Response 5: Thank you for the suggestion. In lines 232-239, we have explained that transistor size has been selected in order to achieve the specified output 1dB compression point. Moreover, we clarified that, as there is typically a trade-off between the minimum Noise Figure NfMIN and the gain related to the choice of the current density, it is convenient to operate the device at a current density smaller than the one that allows maximum fT: as shown in Figure 4, fT peaks at 14 mA bias cu rrent but a 10 mA bias current has been selected to reduce the NFMIN by 1.5dB with a small reduction in fT.
Comment 6: In Fig. 7, for the Micro-photograph, length/width could be marked in this picture scientifically.
Response 6: The reviewer’s suggestion has been implemented. In the revised manuscript, the die size is presented both in the manuscript (line 298 and 335) and in the captions of Figure 7 and Figure 10.
Comment 7: What the correlation between the two different low-band down-converters & the high-band down-converter is could be presented by combining Fig. 12 and Fig. 13 together into one effectively.
Response 7: Thank you for the suggestion. The measurements reported in Figure 12 and Figure 13 are related to different circuits (the low-band and the high-band down-converters), and have been performed at different RF and LO input frequencies: therefore, it could be confusing for the Reader to put these measurements in the same picture.
Author Response File: Author Response.pdf
Round 2
Reviewer 1 Report
Comments and Suggestions for AuthorsAuthors have revised their paper (shown as red fonts), as expected, which somehow agrees with my concerns previously raised. Thus, I suggest considering this work for possible publication
Comments on the Quality of English Language--
Author Response
Comment: Authors have revised their paper (shown as red fonts), as expected, which somehow agrees with my concerns previously raised. Thus, I suggest considering this work for possible publication.
Response: We sincerely thank the reviewer for his constructive comments at round 1, which allowed us to improve the paper quality.
Reviewer 2 Report
Comments and Suggestions for AuthorsThe authors have now clarified many aspects compared to the previous version.
Please for the sake of clarity include the definition of PTAT and MAG.
Author Response
Comment: The authors have now clarified many aspects compared to the previous version. Please for the sake of clarity include the definition of PTAT and MAG.
Response: We sincerely thank the reviewer for his constructive comments at round 1, which allowed us to improve the paper quality. We have now included the definition of PTAT (at line 265) and MAG (at line 165)
Reviewer 3 Report
Comments and Suggestions for Authorsno comments
Author Response
Comment: No comments.
Response: We sincerely thank the reviewer for his constructive comments at round 1, which allowed us to improve the paper quality.
Reviewer 4 Report
Comments and Suggestions for AuthorsNo further comments
Author Response
Comment: No further comments
Response: We sincerely thank the reviewer for his constructive comments in the first round, which allowed us to improve the quality of the paper.
