BTI Aging Influence Analysis and Mitigation in Flash ADCs

Abstract

Bias Temperature Instability (BTI)-induced aging of transistors is a serious concern in modern electronic circuits, yet its effects on the operation of mixed-signal circuits have not been extensively studied. In this work, initially we analyze how BTI-induced aging degradation influences the analog front end of Flash analog-to-digital converters (ADCs). BTI-induced aging leads to substantial increments in the offset voltage of the ADC comparators, which in turn affect their trip point voltage, leading to the alteration of the ADC’s performance characteristics, such as gain, full-scale error and integral nonlinearity. Thus, erroneous responses are generated. Next, we propose a low-cost BTI-induced aging mitigation technique based on a circuit reconfiguration method which periodically alters the average voltage stress on the ADC comparators’ transistors. The proposed method limits the comparators’ offset voltage development, restricting the shift in their trip point voltage. Consequently, the impact of aging on the performance characteristics of the ADC is drastically reduced, and its reliability is improved. According to our simulations, after two years of operation, the gain error is reduced by 95.43%, the full-scale error is reduced by 63.31% and the integral nonlinearity is reduced by 63.00%, with respect to operation without applying the proposed aging mitigation technique.

1. Introduction

Integrated-circuit designers need to consider an increased number of reliability challenges as CMOS technology scales down. Among them, aging mechanisms emerging over the circuits’ lifetime gradually degrade their performance [1]. Such aging effects result from various physical phenomena, like Bias Temperature Instability (BTI), Hot-Carrier Injection (HCI), Electromigration and Time-Dependent Dielectric Breakdown (TDDB) [2]. BTI, a serious concern in nanotechnology circuits, causes progressive degradation of transistor characteristics, typically observed as an increase in their absolute threshold voltage value V_th. BTI is accelerated when transistors are excessively stressed (elevated gate-to-source voltage (V_GS) levels and operation under elevated temperatures). Consequently, the V_th of a transistor under permanent (DC) BTI stress degrades to a much higher extent with respect to intermittent (AC) BTI stress, as during AC stress, incorporated recovery cycles partially retrieve the V_th shift. For PMOS transistors BTI is described as Negative BTI (NBTI), and for NMOS transistors as Positive BTI (PBTI), in accordance with the polarity of the V_GS stress in each case.

The influence of BTI-induced aging on mixed-signal integrated circuits has been less extensively studied in the literature compared to purely analog or digital integrated circuits. Obviously, mixed-signal circuits are expected to present the same reliability issues as their analog and digital counterparts [2,3]. On-chip monitoring circuits for characterizing the impact of BTI and HCI on the frequency and phase noise degradation of a Phase-Locked Loop (PLL) circuit are discussed in [4]. In [5], a study on the influence of BTI and HCI on a mixed-signal delay-locked loop circuit is presented. Challenges in RF and mixed-signal circuit reliability due to BTI- and HCI-induced aging are analyzed in [6]. A technique for the estimation of BTI-induced aging-related reliability degradation in analog and mixed-signal systems is proposed in [7]. An experimental analysis of the effects of BTI- and HCI-induced aging on RF linear power amplifiers is presented in [8]. The influence of BTI- and HCI-induced aging on differential amplifier circuits is analyzed in [9] and an aging suppression and process variation calibration approach is proposed. A BTI-induced aging mitigation solution for operational-amplifier-based comparators, using body biasing techniques, is presented in [10]. Furthermore, an aging monitoring and recovery scheme for analog circuits utilizing adaptive bias techniques or spare transistors is proposed in [11].

Only a few studies deal with BTI’s influence in analog-to-digital conversion circuits. The authors of [12] investigate the BTI-related degradation of the building blocks inside a Successive Approximation Register (SAR) analog-to-digital converter (ADC). Offset issues in comparator operation are accentuated. An analysis of transistor-aging-induced degradation’s effects on the performance characteristics of a SAR-ADC is also presented in [13]. Circuit design techniques to mitigate short-term BTI-induced aging issues in SAR-ADCs are proposed in [14]. According to the authors, the comparator input nodes are temporally connected to the same voltage level, after each conversion is complete, to equalize the stress on the input transistors and alleviate the influence of aging. In [15], a measurement circuit and a method for the characterization of short-term BTI effects in a SAR-ADC are proposed. Aging-induced offset voltage problems in the comparators of the ADC design are discussed. Furthermore, ref. [16] investigates the impact of aging on mixed-signal CMOS ICs, using as a case study a SAR-ADC. In [17] the influence of BTI-induced transistor aging in the comparators of Flash ADCs is analyzed. Also, in [18] the effect of transistor aging in the operation of the comparators used in ADCs is discussed. The aging mechanisms, including BTI, contribute to device time-dependent variability. As a solution to this variability, the authors proposed the increment of the transistor gate area, which in turn drastically increases the silicon area overhead. Finally, in [19] an aging analysis is presented on a strong-arm latch that can be used as comparator in Flash ADC designs. Both BTI- and HCI-induced aging mechanisms are considered. An anti-aging solution is proposed for HCI-induced aging prevention that involves precharging the drain terminals of the input transistors in the comparators at the reset stage or in the idle state of the ADC.

In this paper, we analyze the effect of BTI-induced aging in the analog front end (comparators) of Flash ADCs and propose a suitable aging mitigation technique. The proposed aging mitigation technique aims to achieve the following:

• Reduce the aging rate of the transistors in the comparators of the ADC and extend the operating lifetime of the circuit.
• Homogenize the transistors’ aging in all comparators, thus diminishing the shift in their trip point voltage, which seriously degrades ADC performance characteristics. Thus, the gradual increase in comparator offset voltage caused by aging is reduced.

The paper is organized as follows. In Section 2, preliminaries of BTI-induced aging and Flash ADCs are provided. Next in Section 3, the influence of BTI on Flash ADC operation is analyzed. Section 4 presents the proposed BTI-induced aging mitigation technique for Flash ADCs. Finally, the conclusions are presented in Section 5.

2. Preliminaries

2.1. Bias Temperature Instability-Induced Aging

Transistor aging phenomena have been present since the first generations of integrated-circuit (IC)-manufacturing technologies. However, extensive studies of these phenomena have been conducted in the nanotechnology era, as they have become extremely relevant and their impact crucial for the reliable operation of circuits as technology evolves [1,2,3].

Transistor aging has become a significant concern in modern electronic systems, since it often leads to substantial system performance degradation over time, reduced efficiency and, ultimately, early system failure.

The BTI-induced aging mechanism predominantly affects field-effect transistors (FETs). As the absolute value of transistors’ V_th gradually increases under BTI’s influence, their driving strength decreases, resulting in degraded performance of the corresponding circuits [5].

Aiming to explore the influence of BTI-induced aging on Flash ADCs, a suitable BTI model is exploited in this work [20,21,22] that provides the transistor threshold voltage shift (ΔV_th) over time under static stress conditions. According to this model, ΔV_th is expressed as follows:

$$\Delta V_{th}=\chi K\sqrt{C_{ox}\left(V_{gs}-V_{th0}\right)}{e}^{-{\displaystyle \frac{E_a}{kT}}}{\left(at\right)}^{{\displaystyle \frac{1}{6}}}$$

(1)

where χ is 0.9 [12] for NMOS and 1 for PMOS, K is a parameter that combines technological and environmental factors and is approximately $2.7V^{{\displaystyle \frac{1}{2}}}{F}^{-{\displaystyle \frac{1}{2}}}{s}^{{\displaystyle \frac{1}{6}}}$, $C_{ox}$ is the oxide capacitance per unit area, k is the Boltzmann constant, T is the temperature, $E_a$ (E_α = 0.49 eV) is the activation energy of the aging mechanism, t is the stress time, and α is the stress ratio of the transistor $0\le \alpha \le 1$. C_ox is evaluated using Equation (2):

$$C_{oxn,p}={(U}_{on,p}\ast ESPOX)/ T_{oxn,p}$$

(2)

Table 1. Technological features used in Equations (1) and (2).

	Vdd = 1 V	ESPOX = 3.9
	nMOS Transistors	pMOS Transistors
Nominal threshold voltage	Vth0n = 1 mV	Vth0p = 58.1 mV
Carrier mobility	Uon = 0.23 m2/(V·s)	Uop = 9.26 m2/(V·s)
Gate oxide thickness	Toxn = 2.25 nm	Toxp = 2.45 nm

presents the features of the technology used for the estimation of the BTI-induced threshold voltage shift.

In the simulations that follow, the influence of BTI-induced aging on a transistor (either PBTI or NBTI) is modeled using a voltage source with proper polarity at the gate terminal of the device, as shown in Figure 1. The voltage level of this source is equal to the expected threshold voltage shift ΔV_th on the corresponding transistor.

2.2. Flash Analog-to-Digital Converter

A Flash ADC is a high-speed and efficient circuit for converting an analog signal into a digital representation. The fundamental components of a typical Flash ADC are a resistor ladder network, comparators and a Thermometer-to-BCD code converter [7]. The general topology of a log₂(n + 1)-bit Flash ADC is presented in Figure 2, where n is the number of comparators in the design.

The resistor ladder network incorporates a network of serially connected precision resistors (R_K = 5 KΩ for fine trimming and R = 1 KΩ for unit steps), and each node produces a unique voltage reference. These resistors divide the power supply voltage into discrete voltage levels to be used as references for the comparators of the converter. Comparators compare the input voltage signal with the reference voltages of the ladder network (one comparator for each reference level). Each comparator determines whether the input voltage is higher or not with respect to its related reference voltage, thereby generating a binary result for each comparison [8]. The comparators’ digital responses are provided in the thermometer code. To attain a Binary-Coded Decimal (BCD) representation of this response, a decoder circuit converts the thermometer code into BCD code, which represents the final digital output of the ADC [9].

Flash ADCs are characterized by high conversion speeds due to the parallel nature of their comparison operation. They can achieve high sampling rates, making them appropriate for applications requiring fast conversion of signals.

3. Influence of BTI-Induced Aging on Flash ADCs

The impact of the BTI-induced aging mechanism on Flash ADC operation is a serious concern, since transistors within the comparators are subjected to permanent stress, which can be either weak or strong [17,18,19]. Considering the topology of the typical Flash ADC, shown in Figure 2, we observe that for each comparator, one of its inputs is driven by a constant voltage from the corresponding tap of the ladder. This implies that DC V_GS stress (either strong or weak depending on the position of the comparator with respect to the resistor ladder) affects the relevant transistors of the comparator, which induces BTI-related aging. As expected, the ΔV_th shift is more pronounced in the transistors on the side of the ladder that experiences permanently higher V_GS stress, so their aging is accelerated. In contrast, the other input of the comparators is driven by a varying analog input signal, so the corresponding transistors experience more balanced BTI stress. This leads to uneven ΔV_th shifts between the two transistor groups as well as among the transistors of comparators located on opposite sides of the resistor ladder, which significantly impacts the comparator functionality (e.g., offset voltage rise) and, consequently, the reliability of the ADC. Thus, over time, the ADC may generate erroneous responses.

To investigate the effect of BTI-induced aging on comparator transistors in a Flash ADC and validate the proposed mitigation technique, we designed the analog front end of a 4-bit Flash ADC circuit (n = 15), as shown in Figure 2, employing the CMOS 90 nm technology of UMC (SP option–V_dd = 1 V) and using the Virtuoso platform of Cadence. The min and the max reference voltage values of the resistor ladder are 285.1 mV and 887.6 mV, respectively. Without loss of generality, for the scope of this study, the comparator used in the ADC design is shown in Figure 3 [10], with the specific characteristics of the transistors presented in

Table 2. Comparator transistors’ characteristics.

nMOS Transistors	pMOS Transistors
Length = 160 nm	Length = 160 nm
Width = 720 nm	Width = 720 nm
Bulk @ GND	Bulk @ Vdd

. It consists of the input differential pair, transistors N1 and N2, along with current mirror loads P1–P2 and P3–P4, respectively. The output currents of the current mirrors are compared using the cross-coupled transistors N5 and N6, and the resulting digital response is latched at the output. The clock signal drives transistor N4 and resets the comparator when this transistor is ON.

In the simulations, performed using the Spectre platform, the input signal (V_in) that was common to all comparators was set to the mean value of the signal swing (V_mean = 586.35 mV). Exploiting the transistor BTI-induced aging model presented in Sub Section 2.1, the expected ΔV_th of the affected transistors in each comparator for the “fresh” (non-aged) state (just after manufacturing), as well as for different operating years, was determined and is presented in Figure 4.

As expected, in the comparators permanently fed by the resistor ladder with higher reference voltage levels (above V_mean), the NMOS input transistors N1 (see Figure 3) are significantly more affected by BTI-induced aging, and their threshold voltage shift becomes higher over time with respect to the relevant transistors of the comparators that are fed with lower reference voltage levels (below V_mean). Moreover, in these cases, NMOS input transistor N1 is more affected by BTI with respect to NMOS input transistor N2, as lower mean V_GS levels are statistically expected on transistor N2. A higher influence of BTI is also expected for PMOS transistors P1 and P2 in the left current mirrors than for transistors P3 and P4 of the right current mirrors, as a result of the lower voltage levels of node LN than RN due to the higher conductivity of transistor N1 than N2.

The opposite situation stands for the comparators that are fed with lower reference voltage levels of the ladder (below V_mean). In this case, transistor N2, when driven by the input signal, will present a higher threshold voltage shift over time with respect to transistor N1. Also, transistors P3 and P4 of the right current mirrors will present a higher influence of BTI than transistors P1 and P2 of the left current mirrors, as a result of the statistically lower voltage levels of node RN than LN due to the higher conductivity of transistor N2 than N1. According to the above analysis, transistors P1, P2, N1, and N3 are under constant voltage (V_GS) stress conditions, so for the calculation of ΔV_th, we set parameter α to 1 in Equation (1). The V_GS of transistors P3, P4, and N2 are varied over time so that these transistors experience AC stress, and for the calculation of ΔV_th, we set α to 0.25 in Equation (1).

Figure 4 a–d presents the transistors’ threshold voltage shifts in the differential stage of the comparators for various operating times and at a temperature of 125 °C. Note that in each pair of current mirror transistors, P1–P2 and P3–P4, the influence of aging is the same, as both transistors share the same V_GS stress.

Nevertheless, in both situations above, the unbalanced aging of the transistors at the two branches of the differential stage in each comparator will result in offset generation, which is not identical among the comparators across the ladder. These results are in agreement with those in [17]. Due to this offset, the trip point voltage of each comparator changes over time, as shown in the simulation results of Figure 5, after several years of operation. The trip point voltage of a comparator corresponds to the specific voltage level where the crossing of the input voltage causes its output to switch state. Consequently, we expect that over time, the ADC will provide erroneous responses, leading to drastically reduced reliability.

Note that transistor N3 is biased with a low voltage level (V_bias = 330 mV), so its aging is limited, while it evenly affects both branches of the differential stage. Moreover, transistors N4–N6 of the latch at the output of the comparator are expected to have a very slow aging rate due to the frequent flipping of their state. Thus, transistors N4–N6 are not considered in the aging analysis according to common practice [23].

4. Proposed Aging Mitigation Technique

The goals of the proposed technique for aging mitigation in Flash ADCs are twofold:

• It initially aims to reduce the aging rate of the comparators’ transistors to extend the circuit’s operating lifetime;
• In parallel, it intends to equalize transistor aging across all comparators, aiming to homogenize and restrict the offset voltage developed over time due to aging, thereby diminishing trip point shifts and enhancing their reliability.

4.1. Design for Aging Mitigation

The aging mitigation strategy is based on the implementation of a reconfigurable analog front end, where the comparators can periodically exchange their roles with respect to the ladder topology. In more detail, and according to the experimental results in the previous section, we observe that the comparators in the middle of the ladder (comparators 7–9) present a substantially more restrained influence of aging on their trip point voltage with respect to comparators near the two edges of the ladder. For example, comparator 8 presents a relative trip point shift of −0.89%, while comparators 1 and 15 present relative trip point shifts of 18.59% and −4.92%, respectively, after 10 years of operation. Moreover, the trip point shifts of the comparators at the bottom of the ladder (see Figure 2) are positive (increase over time), while the trip point shifts of the comparators at the top of the ladder are negative (decrease overtime). Therefore, symmetrical and periodic switching of the comparators’ roles, with respect to the central comparator (n + 1)/2 (comparator 8 in our design paradigm), was adopted for aging influence mitigation. Thus, the comparators at the two ends of the ladder periodically exchange their roles (comparators 1 and 15 in the paradigm). Consequently, in a periodical manner, the bottom comparator (comparator 1) is fed either with the lowest or the highest reference voltage of the ladder, ladder while the complementary situation stands for the top comparator (comparator 15); in parallel, the immediately adjacent comparators to the previous ones also exchange their roles (e.g., comparators 2 and 14), and this pattern continues up to the pair of comparators (n − 1)/2 and (n + 3)/2 (comparators 7 and 9 in the paradigm). The central comparator (n + 1)/2 (comparator 8 in the design paradigm) remains unaltered.

The above aging mitigation technique can be simply implemented by periodically switching the voltage bias at the ladder edges between V_dd and Gnd. A reconfigurable ADC topology is adopted where four extra transistors are required; a pair of PMOS-NMOS transistors at each edge (bottom and top) of the ladder topology, as shown in Figure 6.

Table 3. Ladder transistors’ characteristics.

nMOS Transistors	pMOS Transistors
Length = 160 nm	Length = 160 nm
Width = 2 μm	Width = 2 μm
Bulk @ GND	Bulk @ Vdd

presents the characteristics of these transistors. The bottom transistors are controlled by the signal SW, while the top ones are controlled by its complementary signal SWb. In order to switch the ladder between the two states, the ADC operation is halted for just one clock cycle after quite a large number of cycles between two aging mitigation actions, so that in practice no influence on its throughput is expected. Moreover, this modification at the ladder side must be followed by the addition of a switching network (a network of (n − 1) 2-to-1 multiplexers composed of simple pass gates) between the comparators and the Thermometer-to-BCD Decoder, as illustrated in Figure 6. Figure 7 illustrates the proposed 2-to-1 multiplexer implemented in the switching network, and

Table 4. The 2-to-1 multiplexer transistors’ characteristics.

nMOS Transistors	pMOS Transistors
Length = 80 nm	Length = 80 nm
Width = 240 nm	Width = 120 nm
Bulk @ GND	Bulk @ Vdd

presents the relevant transistors’ characteristics. All multiplexers are controlled by the SW signal. Thus, in every state of circuit operation, each comparator feeds the correct input of the Thermometer-to-BCD Decoder according to its role with respect to the ladder’s state of operation.

Considering the simulation results that follow, by adopting the above technique, it is feasible to mitigate uneven transistor aging in the comparators and achieve more uniform transistor V_th degradation across all comparators while in parallel slowing down the V_th degradation of highly stressed comparators. Thus, for each comparator the deviation of the trip point from the expected value is reduced so that the influence of BTI-induced aging on the ADC performance characteristics is restricted.

4.2. Simulation Results on Aging Mitigation

The proposed aging mitigation technique is applied in the design of the 4-bit Flash ADC under consideration, as shown in Figure 6. For the estimation of the evolution of the threshold voltage shift over time, we recursively apply Equation (1) for each transistor of each comparator and for each periodic ladder state, using as the initial V_th value of the current state the final V_th value of the previous state, and this pattern continues until the process is complete. Thus, we sequentially accumulate the incremental ΔV_th predicted for each device at successive τ periods. This approach ensures continuity and yields a representative mid-stress evolution.

In Figure 8, we present the evolution of the transistors’ threshold voltage shifts in each comparator due to aging, after ten years of operation and under various resistor ladder switching rates, ranging from one switch per 1 s, 30 min, 12 h, 1 week and 4 months. For comparisons, the transistors’ threshold voltage shifts after 10 years of operation without any resistor ladder switching activity (typical stress conditions) are also illustrated in this figure.

We observe that by increasing the switching rate, the threshold voltage shift tends to homogenize among the corresponding transistors in the comparators. This is indicated by the tendency of the curve to become flat as the switching rate increases. Thus, for those transistors in the comparators that are highly stressed in the original ADC design (without switching activity), the application of the proposed aging mitigation technique results in a reduced total threshold voltage shift. The opposite stands for the transistors experiencing low stress, where the total threshold voltage shift is increased when the new technique is applied. Overall, and according to Figure 8, the application of the proposed technique results in balanced threshold voltage degradation across the respective transistors of all comparators, and in parallel between the corresponding transistors in the two branches of each comparator. As a consequence, this balanced threshold voltage degradation substantially restricts the deviation of the comparators’ trip point from the expected value, according to the simulation results in Figure 9 and Figure 10.

Both figures present the response characteristic of the ADC circuit in the “fresh” (non-aged) condition and after two and ten years of operation, respectively, without and with the application of the proposed aging mitigation technique. In these curves, it is easy to observe the trip point shift of the comparators over the years and its significant reduction after the application of the proposed aging mitigation technique. For example, in Figure 10a, after ten years of operation without applying the proposed technique, a significant trip point deviation appears in all comparators, with the highest values obtained for comparator 1 (53.1 mV, which corresponds to a 18.63% deviation) and comparator 15 (47.9 mV, which corresponds to a 5.4% deviation), as also illustrated in Figure 11. On the contrary, using the aging mitigation technique, after ten years of operation, the trip point deviation is drastically reduced, and in comparator 5, it is almost eliminated. According to Figure 11, for comparator 1 the trip point deviation reduces to 37.5 mV (a reduction of 29.37%), while for comparator 15 it reduces to 23.9 mV (a reduction of 54.99%).

Obviously, the influence of aging on the comparators’ trip point also affects, as a side effect, the ADC performance metrics (gain, full-scale error, integral nonlinearity (INL)). Thus, by reducing the aging-induced trip point deviation of the comparators, the ADC performance metrics are improved. In Figure 12, the reductions in the aging-related gain, and in the full-scale and INL errors, achieved by applying the proposed technique (with a switching period of 1 s), after 2 and 10 years of operation are presented. The gain error reductions are 95.54% and 50.65% after 2 and 10 years of operation, respectively. In addition, for the same operating times, the full-scale error reductions are 63.31% and 39.32%, and the INL error reductions are 63.00% and 39.21%, respectively.

5. Conclusions

In this paper we investigate the impact of transistor BTI-induced aging on the analog front end of Flash ADCs, and we propose an aging mitigation technique aiming to retain the ADC’s performance and extend its operating lifetime. BTI-induced aging crucially affects the offset voltage of the used comparators and, consequently, their trip point voltage. In turn, the ADC performance characteristics, such as gain, full-scale error and integral nonlinearity, are also affected.

The proposed BTI-induced aging mitigation technique is based on a simple and low-silicon-area-cost circuit reconfiguration mechanism that periodically alters comparators’ functionality, reducing the average voltage stress on their transistors. As a result, the comparators’ offset voltage development is restricted, and the same stands for the shift in their trip point voltage. Thus, the impact of aging on the ADC performance characteristics is drastically reduced, ensuring long-term reliable operation. For two years of circuit operation, the ADC with the application of the proposed aging mitigation technique presents a gain error reduction of 95.43%, full-scale error reduction of 63.31% and integral nonlinearity reduction of 63.00%, with respect to the original ADC. Finally, note that the silicon area overhead of the proposed solution is only four transistors on the resistor ladder side and one digital 2-to-1 multiplexer at the output of each comparator, plus a control signal.