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Keywords = memory IC package

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16 pages, 3196 KB  
Article
Deep Learning Study on Memory IC Package Warpage Using Deep Neural Network and Finite Element Simulation
by Sunil Kumar Panigrahy, Fa Xing Che, Yeow Chon Ong, Hong Wan Ng and Gokul Kumar
Chips 2025, 4(3), 35; https://doi.org/10.3390/chips4030035 - 27 Aug 2025
Viewed by 873
Abstract
In recent years, many electronic device industries have shown interest in using artificial intelligence (AI) to quickly estimate package warpage. Machine learning is one of the AI techniques which will give an express prediction on package warpage with the help of several attributes [...] Read more.
In recent years, many electronic device industries have shown interest in using artificial intelligence (AI) to quickly estimate package warpage. Machine learning is one of the AI techniques which will give an express prediction on package warpage with the help of several attributes of the data and different algorithms. This study uses a deep learning (DL) model which combines with a deep neural network (DNN) technique and finite element analysis (FEA) to estimate the package warpage of a mobile universal flash storage (UFS) package. Developing a DL model requires a training database from finite element simulation results and a DNN algorithm. The developed DL model accuracy for package warpage is calculated by validating FEA simulation results and experiment data. The error between the DL model prediction and FEA simulation result is less than 7%. This proposed approach can help effectively and efficiently assess package warpage for new product introduction (NPI) with less FEA simulation work and less test vehicle of a real package for warpage measurement and assessment. Full article
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22 pages, 4808 KB  
Review
SRAM Cell Design Challenges in Modern Deep Sub-Micron Technologies: An Overview
by Waqas Gul, Maitham Shams and Dhamin Al-Khalili
Micromachines 2022, 13(8), 1332; https://doi.org/10.3390/mi13081332 - 17 Aug 2022
Cited by 30 | Viewed by 8817
Abstract
Microprocessors use static random-access memory (SRAM) cells in the cache memory design. As a part of the central computing component, their performance is critical. Modern system-on-chips (SoC) escalate performance pressure because only 10–15% of the transistors accounts for logic, while the remaining transistors [...] Read more.
Microprocessors use static random-access memory (SRAM) cells in the cache memory design. As a part of the central computing component, their performance is critical. Modern system-on-chips (SoC) escalate performance pressure because only 10–15% of the transistors accounts for logic, while the remaining transistors are for the cache memory. Moreover, modern implantable, portable and wearable electronic devices rely on artificial intelligence (AI), demanding an efficient and reliable SRAM design for compute-in-memory (CIM). For performance benchmark achievements, maintaining reliability is a major concern in recent technological nodes. Specifically, battery-operated applications utilize low-supply voltages, putting the SRAM cell’s stability at risk. In modern devices, the off-state current of a transistor is becoming comparable to the on-state current. On the other hand, process variations change the transistor design parameters and eventually compromise design integrity. Furthermore, sensitive information processing, environmental conditions and charge emission from IC packaging materials undermine the SRAM cell’s reliability. FinFET-SRAMs, with aggressive scaling, have taken operation to the limit, where a minute anomaly can cause failure. This article comprehensively reviews prominent challenges to the SRAM cell design after classifying them into five distinct categories. Each category explains underlying mathematical relations followed by viable solutions. Full article
(This article belongs to the Special Issue Emerging CMOS Devices)
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