Ultra-Small Temperature Sensing Units with Fitting Functions for Accurate Thermal Management
Round 1
Reviewer 1 Report
Comments and Suggestions for Authors
This paper presents a novel temperature sensing architecture focused on minimizing sensing unit area by modeling the current-temperature relationship using fitting functions. The motivation is well justified, and the idea is innovative, and simulations are extensive. One of my biggest concerns is that the paper is totally based on simulations, lacks circuit-level validation and implementation as well as discussion of practical implementation constraints. The following are some other comments.
- Line 23: The specific choice of w = 400 nm, l = 180 nm for the diode-connected PMOS should be justified here with some indication of its benefit as well as the novelty of proposed sensing unit.
- Line 63: The claim that “temperature can be measured among compact circuits” would benefit from numerical comparisons with existing sensor sizes.
- Line 70: The claim that “any increase in accuracy will increase performance” needs a supporting reference or quantifiable justification. I would be very interested to know the accuracy of the existing sensors.
- Line 77: It would be better to give the full name of all the abbreviations when mention them first time, such as SAR, IDAC.
- Figure 2: It would be better to describe figure 2 in sufficient detail. Labeling all components clearly and referencing them in the text is recommended.
- Line 77: Explain how the SAR, IDAC, and comparator work together to approximate current — a step-by-step signal path explanation would be helpful.
- Line 100: It would be better to quantify how much path area is reduced compared to voltage-mode sensors.
- Line 118: The inaccuracy goal of ±0.16 °C needs more background—what is the state-of-the-art, and why is this chosen?
- Figure 3: It would be better to describe figure 3 in sufficient detail.
- Line 165: It would be better to explain the motivation for normalizing both current and temperature, does this reduce error?
- Line 221: The simplifications in the diode equation are not validated. Consider showing error data or simulation convergence comparisons.
- Table 2: What is the “Diode-ndio_m”?
- Line 238: The 8 m°C step size is unusually small. Justify its choice and its impact on simulation runtime and result granularity.
- Table 3: In Table 3, it is not clear how the chosen Vref values were optimized or selected.
- Line 252: Define what constitutes “reasonable” current values for IDAC. It would be better to give a ballpark specification.
- Line 276: It would be better to mention how noise or mismatch was accounted for in the 400 MC simulations.
- Line 280: It would be better to explain the physical trimming method or circuitry.
- Line 320: If the sensing unit design is not portable to other processes, discuss how the design methodology can still generalize.
- Line 326: If multiple fitting functions per sensing unit are used, how will selection/aggregation (e.g., median) be implemented in hardware?
Author Response
- Line 23: The specific choice of w = 400 nm, l = 180 nm for the diode-connected PMOS should be justified here with some indication of its benefit as well as the novelty of proposed sensing unit. Response: This has been updated with more detail. Near line 23.
- Line 63: The claim that “temperature can be measured among compact circuits” would benefit from numerical comparisons with existing sensor sizes. Response: I believe the comparison table will be sufficient for this purpose. (Table 6)
- Line 70: The claim that “any increase in accuracy will increase performance” needs a supporting reference or quantifiable justification. I would be very interested to know the accuracy of the existing sensors. Response: This statement has been softened. This claim is also conceptually supported by sources 9-12.
- Line 77: It would be better to give the full name of all the abbreviations when mention them first time, such as SAR, IDAC. Response: This is resolved.
- Figure 2: It would be better to describe figure 2 in sufficient detail. Labeling all components clearly and referencing them in the text is recommended. Response: More detail has been added on this.
- Line 77: Explain how the SAR, IDAC, and comparator work together to approximate current — a step-by-step signal path explanation would be helpful. Response: More detail has been added.
- Line 100: It would be better to quantify how much path area is reduced compared to voltage-mode sensors. Response: This work assumes ideal conditions. This is only a conceptual argument. I have softened the first sentence to reflect this.
- Line 118: The inaccuracy goal of ±0.16 °C needs more background—what is the state-of-the-art, and why is this chosen? Response: Table 6 provides more information on state-of-the-art. This was chosen based on comparison to other work. Another value could have been chosen. Figure 4 indicates that INL spec may be a function of yield.
- Figure 3: It would be better to describe figure 3 in sufficient detail. Response: Further description has been added below.
- Line 165: It would be better to explain the motivation for normalizing both current and temperature, does this reduce error? Response: More detail has been added. Lines 181-183
- Line 221: The simplifications in the diode equation are not validated. Consider showing error data or simulation convergence comparisons. Response: There are many papers already focusing on modeling diodes. Due to convergence issues in the python program it was simplified. Further work can be done in this area to show how the diode can be modeled when fitting temperature-current data.
- Table 2: What is the “Diode-ndio_m”? Response: explanation added lines 252-253
- Line 238: The 8 m°C step size is unusually small. Justify its choice and its impact on simulation runtime and result granularity. Response: Lines 258-260 add more detail
- Table 3: In Table 3, it is not clear how the chosen Vref values were optimized or selected. Response: Line 264 has more detail
- Line 252: Define what constitutes “reasonable” current values for IDAC. It would be better to give a ballpark specification. Response: A ballpark specification has been provided. Line 275
- Line 276: It would be better to mention how noise or mismatch was accounted for in the 400 MC simulations. Response: These were introduced using the standard process and mismath variations. This has been updated. Line 300
- Line 280: It would be better to explain the physical trimming method or circuitry. Response: This was done using simulation which has been clarified in line 295. The following paragraph (line 296-304) explained the process in detail.
- Line 320: If the sensing unit design is not portable to other processes, discuss how the design methodology can still generalize. Response: Detail has been added. Lines 349-351
- Line 326: If multiple fitting functions per sensing unit are used, how will selection/aggregation (e.g., median) be implemented in hardware? Response: This is for future work. However, digital comparators could be used with a MUX for selection in hardware.
Author Response File: Author Response.pdf
Reviewer 2 Report
Comments and Suggestions for Authors
The manuscript entitled “Ultra-Small Temperature Sensing Units with Fitting Functions for Accurate Thermal Management” has been reviewed. Before it can be accepted for publication, I would like to raise the following minor revision points:
- In Figure 2, the authors should more clearly explain the abbreviations SAR and IDAC. Additionally, it would be helpful to elaborate on how the schematic addresses or improves upon existing designs.
- The authors should clarify how they define "temperature inaccuracies". Are these based on standard deviation, maximum error, or another metric?
- Figure 3 lacks sufficient explanation. There are no indicators or labels to guide the reader's understanding. Please revise it to improve clarity.
Comments for author File: Comments.pdf
Author Response
- In Figure 2, the authors should more clearly explain the abbreviations SAR and IDAC. Additionally, it would be helpful to elaborate on how the schematic addresses or improves upon existing designs. Response: These abbreviations have been described in lines 82-83. How these sub-circuit components are used is described in more detail in lines 83-86.
- The authors should clarify how they define "temperature inaccuracies". Are these based on standard deviation, maximum error, or another metric? Response: I have added the following to clear the confusion. "In this work, simulations will be performed instead of measurements, so the ± 0.16 °C inaccuracy definition will only be generally referenced."
- Figure 3 lacks sufficient explanation. There are no indicators or labels to guide the reader's understanding. Please revise it to improve clarity. Response: More detail has been added in lines 144-147 to describe the figure.
Author Response File: Author Response.pdf
Reviewer 3 Report
Comments and Suggestions for Authors
The paper proposes an innovative on-chip temperature sensing architecture aimed at realizing ultra-small temperature sensing units in the TSMC 180nm process, combining fitting functions for digital domain temperature estimation. The research objectives are clear, the theoretical analysis is sound, the simulation design is detailed, and the results demonstrate promising application potential. The work exhibits notable innovation and engineering practicality, providing a valuable design reference for future thermal management in high-density integrated circuits. There are some problems, which must be solved before it is considered for publication.
1.The conclusions of this work are entirely based on simulation results, without any silicon measurement or experimental validation. To strengthen the credibility of the proposed design, it is recommended to include chip-level measurement data that verifies performance under real process variations, temperature changes, and supply/noise conditions.
2.While the proposed architecture is conceptually sound, the manuscript lacks discussion on the circuit-level implementation of key blocks such as the SAR logic, IDAC, comparator, and the reference voltage generator. Estimations of their area, power, or latency would help assess the feasibility of deploying this design in a real chip.
3.INL (Integral Non-Linearity) is frequently used as the primary accuracy metric throughout the paper. However, there is no clear explanation of how INL is defined or calculated. A formal description in the methodology section would improve clarity and reproducibility.
4.There is at least one error in the manuscript, such as, in page 8, TABLE 5, "797.5%" under "-20°C" is erroneous. Please check the manuscript carefully.
5.Figure 4 lacks clear labeling of the x-axis units and the distribution density. It is recommended to improve the figure caption and axis annotations to ensure clarity and completeness.
6.The paper suggests that using a current-domain approach alleviates the need for wide routing paths, but no quantitative analysis is provided on path resistance or voltage drop. Including simulation data or boundary condition assumptions would strengthen this claim.
7.Most references cited are from the past decade, but some key review papers are missing. It is recommended to add more foundational literature in the introduction or discussion to strengthen the theoretical coherence of the study.
Author Response
1.The conclusions of this work are entirely based on simulation results, without any silicon measurement or experimental validation. To strengthen the credibility of the proposed design, it is recommended to include chip-level measurement data that verifies performance under real process variations, temperature changes, and supply/noise conditions. Response: Due to budget constraints, this was not done for this paper. Silicon results are also not done because of the following, "While these specifications are important, the most beneficial parts of this work might be the characterization and design process. The specific results, like the sensing unit selected, may not translate to other processes like other temperature sensors usually would, because the specifics of the temperature-current relationship may look different in any given process. However, the architectural characterization, and the sensing unit selection process might be the most valuable components of this research."
2.While the proposed architecture is conceptually sound, the manuscript lacks discussion on the circuit-level implementation of key blocks such as the SAR logic, IDAC, comparator, and the reference voltage generator. Estimations of their area, power, or latency would help assess the feasibility of deploying this design in a real chip. Response: Yes, this is a very important issue that will need to be investigated. The feasibility of using non-ideal sub-circuit components will likely be discussed in a future paper. This paper assumes that these components are ideal as they have been heavily researched already. This paper seeks to show that this architecture is feasible based on the most novel components.
3.INL (Integral Non-Linearity) is frequently used as the primary accuracy metric throughout the paper. However, there is no clear explanation of how INL is defined or calculated. A formal description in the methodology section would improve clarity and reproducibility. Response: The following has been added in lines 131-132. "INL is the largest temperature error seen across the operating temperature range of -40 to 125 °C for a given sensing unit, reference voltage, and fitting function."
4.There is at least one error in the manuscript, such as, in page 8, TABLE 5, "797.5%" under "-20°C" is erroneous. Please check the manuscript carefully. Response: This has been resolved.
5.Figure 4 lacks clear labeling of the x-axis units and the distribution density. It is recommended to improve the figure caption and axis annotations to ensure clarity and completeness. Response: This has been updated.
6.The paper suggests that using a current-domain approach alleviates the need for wide routing paths, but no quantitative analysis is provided on path resistance or voltage drop. Including simulation data or boundary condition assumptions would strengthen this claim. Response: This is an important issue to consider. This argument is made conceptually but this simulation may be presented in future research. This paper will focus on showing that this concept is feasible.
7.Most references cited are from the past decade, but some key review papers are missing. It is recommended to add more foundational literature in the introduction or discussion to strengthen the theoretical coherence of the study. Response: I would be curious to hear what papers you are seeing. I think that the current references provide sufficient background and show need for further research in the area.
Author Response File: Author Response.pdf
Round 2
Reviewer 1 Report
Comments and Suggestions for Authors
I have no further comments.
Author Response
No additional changes have been made.
Reviewer 3 Report
Comments and Suggestions for Authors
The authors have answered all the questions and revised their manuscript accordingly.
Author Response
No additional changes have been made.