Investigation on Performance of Single Precision Floating Point Multiplier (SPFPM) Using CSA Multiplier and Different Types of Adders ^†

Nowadays, floating point multiplier (FPM) plays an essential role in computers. The IEEE 754 norm for floating point numbers is the most widely recognized portrayal for real numbers on today’s PCs. Addition, multiplication, subtraction, and division are the four important functions of single precision floating arithmetic, amongst which multiplication has the most extensive use in every algorithm. Fast multipliers are of critical need in modern high-performance applications, especially in digital signal processing, because DSP involves many important multiplication-based operations, e.g., fast Fourier transform (FFT) and convolution. These speedy computations can be implemented on field programmable gate arrays (FPGAs), because they can provide a high speed and a large number of on-board digital resources. FPGAs are involved in many modern applications such as cryptography and communication computations, arithmetic and scientific computation, digital image and signal processing, etc. There are many forms of FPM available. This paper describes an efficient way to implement single precision FPM in IEEE 754 standard format, where Verilog hardware description language (VHDL) is used to implement the design for Xilinx Spartan 6 FPGA. Here, the 32-bit number will be divided into three parts: sign bit, exponent, and mantissa. This paper is implemented by using different types of adders, which includes carry increment adder (CIA), carry select adder (CSA), ripple carry adder (RCA), and carry look-ahead adder (CLA). Carry save array (CSA) multiplication is used for performing the mantissa multiplication.